<s>
In	O
computing	O
,	O
a	O
vector	B-Operating_System
processor	I-Operating_System
or	O
array	B-Operating_System
processor	I-Operating_System
is	O
a	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	B-General_Concept
)	O
that	O
implements	O
an	O
instruction	B-General_Concept
set	I-General_Concept
where	O
its	O
instructions	O
are	O
designed	O
to	O
operate	O
efficiently	O
and	O
effectively	O
on	O
large	O
one-dimensional	O
arrays	O
of	O
data	O
called	O
vectors	O
.	O
</s>
<s>
This	O
is	O
in	O
contrast	O
to	O
scalar	B-General_Concept
processors	I-General_Concept
,	O
whose	O
instructions	O
operate	O
on	O
single	O
data	O
items	O
only	O
,	O
and	O
in	O
contrast	O
to	O
some	O
of	O
those	O
same	O
scalar	B-General_Concept
processors	I-General_Concept
having	O
additional	O
single	B-Device
instruction	I-Device
,	I-Device
multiple	I-Device
data	I-Device
(	O
SIMD	B-Device
)	O
or	O
SWAR	B-General_Concept
Arithmetic	O
Units	O
.	O
</s>
<s>
Vector	B-Operating_System
processors	I-Operating_System
can	O
greatly	O
improve	O
performance	O
on	O
certain	O
workloads	O
,	O
notably	O
numerical	B-Application
simulation	I-Application
and	O
similar	O
tasks	O
.	O
</s>
<s>
Vector	B-Operating_System
processing	I-Operating_System
techniques	O
also	O
operate	O
in	O
video-game	B-Device
console	I-Device
hardware	O
and	O
in	O
graphics	B-Architecture
accelerators	I-Architecture
.	O
</s>
<s>
Vector	O
machines	O
appeared	O
in	O
the	O
early	O
1970s	O
and	O
dominated	O
supercomputer	B-Architecture
design	O
through	O
the	O
1970s	O
into	O
the	O
1990s	O
,	O
notably	O
the	O
various	O
Cray	O
platforms	O
.	O
</s>
<s>
The	O
rapid	O
fall	O
in	O
the	O
price-to-performance	O
ratio	O
of	O
conventional	O
microprocessor	B-Architecture
designs	O
led	O
to	O
a	O
decline	O
in	O
vector	O
supercomputers	B-Architecture
during	O
the	O
1990s	O
.	O
</s>
<s>
Vector	B-Operating_System
processing	I-Operating_System
development	O
began	O
in	O
the	O
early	O
1960s	O
at	O
Westinghouse	O
in	O
their	O
"	O
Solomon	O
"	O
project	O
.	O
</s>
<s>
Solomon	O
's	O
goal	O
was	O
to	O
dramatically	O
increase	O
math	O
performance	O
by	O
using	O
a	O
large	O
number	O
of	O
simple	O
math	B-General_Concept
co-processors	I-General_Concept
under	O
the	O
control	O
of	O
a	O
single	O
master	O
CPU	B-General_Concept
.	O
</s>
<s>
The	O
CPU	B-General_Concept
fed	O
a	O
single	O
common	O
instruction	O
to	O
all	O
of	O
the	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
(	O
ALUs	O
)	O
,	O
one	O
per	O
cycle	O
,	O
but	O
with	O
a	O
different	O
data	O
point	O
for	O
each	O
one	O
to	O
work	O
on	O
.	O
</s>
<s>
This	O
allowed	O
the	O
Solomon	O
machine	O
to	O
apply	O
a	O
single	O
algorithm	O
to	O
a	O
large	O
data	B-General_Concept
set	I-General_Concept
,	O
fed	O
in	O
the	O
form	O
of	O
an	O
array	O
.	O
</s>
<s>
In	O
1962	O
,	O
Westinghouse	O
cancelled	O
the	O
project	O
,	O
but	O
the	O
effort	O
was	O
restarted	O
at	O
the	O
University	O
of	O
Illinois	O
as	O
the	O
ILLIAC	B-Device
IV	I-Device
.	O
</s>
<s>
The	O
ILLIAC	O
approach	O
of	O
using	O
separate	O
ALUs	O
for	O
each	O
data	O
element	O
is	O
not	O
common	O
to	O
later	O
designs	O
,	O
and	O
is	O
often	O
referred	O
to	O
under	O
a	O
separate	O
category	O
,	O
massively	B-Operating_System
parallel	I-Operating_System
computing	I-Operating_System
.	O
</s>
<s>
A	O
computer	B-General_Concept
for	I-General_Concept
operations	I-General_Concept
with	I-General_Concept
functions	I-General_Concept
was	O
presented	O
and	O
developed	O
by	O
Kartsev	O
in	O
1967	O
.	O
</s>
<s>
The	O
first	O
vector	O
supercomputers	B-Architecture
are	O
the	O
Control	O
Data	O
Corporation	O
STAR-100	B-Device
and	O
Texas	O
Instruments	O
Advanced	B-Device
Scientific	I-Device
Computer	I-Device
(	O
ASC	O
)	O
,	O
which	O
were	O
introduced	O
in	O
1974	O
and	O
1972	O
,	O
respectively	O
.	O
</s>
<s>
The	O
basic	O
ASC	O
(	O
i.e.	O
,	O
"	O
one	O
pipe	O
"	O
)	O
ALU	O
used	O
a	O
pipeline	B-General_Concept
architecture	I-General_Concept
that	O
supported	O
both	O
scalar	O
and	O
vector	O
computations	O
,	O
with	O
peak	O
performance	O
reaching	O
approximately	O
20	O
MFLOPS	O
,	O
readily	O
achieved	O
when	O
processing	O
long	O
vectors	O
.	O
</s>
<s>
The	O
STAR-100	B-Device
was	O
otherwise	O
slower	O
than	O
CDC	O
's	O
own	O
supercomputers	B-Architecture
like	O
the	O
CDC	B-Device
7600	I-Device
,	O
but	O
at	O
data-related	O
tasks	O
they	O
could	O
keep	O
up	O
while	O
being	O
much	O
smaller	O
and	O
less	O
expensive	O
.	O
</s>
<s>
However	O
the	O
machine	O
also	O
took	O
considerable	O
time	O
decoding	O
the	O
vector	O
instructions	O
and	O
getting	O
ready	O
to	O
run	O
the	O
process	O
,	O
so	O
it	O
required	O
very	O
specific	O
data	B-General_Concept
sets	I-General_Concept
to	O
work	O
on	O
before	O
it	O
actually	O
sped	O
anything	O
up	O
.	O
</s>
<s>
The	O
vector	O
technique	O
was	O
first	O
fully	O
exploited	O
in	O
1976	O
by	O
the	O
famous	O
Cray-1	B-Device
.	O
</s>
<s>
Instead	O
of	O
leaving	O
the	O
data	O
in	O
memory	O
like	O
the	O
STAR-100	B-Device
and	O
ASC	O
,	O
the	O
Cray	O
design	O
had	O
eight	O
vector	O
registers	O
,	O
which	O
held	O
sixty-four	O
64-bit	O
words	O
each	O
.	O
</s>
<s>
Whereas	O
the	O
STAR-100	B-Device
would	O
apply	O
a	O
single	O
operation	O
across	O
a	O
long	O
vector	O
in	O
memory	O
and	O
then	O
move	O
on	O
to	O
the	O
next	O
operation	O
,	O
the	O
Cray	O
design	O
would	O
load	O
a	O
smaller	O
section	O
of	O
the	O
vector	O
into	O
registers	O
and	O
then	O
apply	O
as	O
many	O
operations	O
as	O
it	O
could	O
to	O
that	O
data	O
,	O
thereby	O
avoiding	O
many	O
of	O
the	O
much	O
slower	O
memory	O
access	O
operations	O
.	O
</s>
<s>
The	O
Cray	O
design	O
used	O
pipeline	B-General_Concept
parallelism	I-General_Concept
to	O
implement	O
vector	O
instructions	O
rather	O
than	O
multiple	O
ALUs	O
.	O
</s>
<s>
In	O
addition	O
,	O
the	O
design	O
had	O
completely	O
separate	O
pipelines	B-General_Concept
for	O
different	O
instructions	O
,	O
for	O
example	O
,	O
addition/subtraction	O
was	O
implemented	O
in	O
different	O
hardware	O
than	O
multiplication	O
.	O
</s>
<s>
This	O
allowed	O
a	O
batch	O
of	O
vector	O
instructions	O
to	O
be	O
pipelined	O
into	O
each	O
of	O
the	O
ALU	O
subunits	O
,	O
a	O
technique	O
they	O
called	O
vector	B-Device
chaining	I-Device
.	O
</s>
<s>
The	O
Cray-1	B-Device
normally	O
had	O
a	O
performance	O
of	O
about	O
80	O
MFLOPS	O
,	O
but	O
with	O
up	O
to	O
three	O
chains	O
running	O
it	O
could	O
peak	O
at	O
240MFLOPS	O
and	O
averaged	O
around	O
150	O
–	O
far	O
faster	O
than	O
any	O
machine	O
of	O
the	O
era	O
.	O
</s>
<s>
Control	O
Data	O
Corporation	O
tried	O
to	O
re-enter	O
the	O
high-end	O
market	O
again	O
with	O
its	O
ETA-10	B-Operating_System
machine	O
,	O
but	O
it	O
sold	O
poorly	O
and	O
they	O
took	O
that	O
as	O
an	O
opportunity	O
to	O
leave	O
the	O
supercomputing	B-Architecture
field	O
entirely	O
.	O
</s>
<s>
In	O
the	O
early	O
and	O
mid-1980s	O
Japanese	O
companies	O
(	O
Fujitsu	O
,	O
Hitachi	O
and	O
Nippon	O
Electric	O
Corporation	O
(	O
NEC	O
)	O
introduced	O
register-based	O
vector	O
machines	O
similar	O
to	O
the	O
Cray-1	B-Device
,	O
typically	O
being	O
slightly	O
faster	O
and	O
much	O
smaller	O
.	O
</s>
<s>
Oregon-based	O
Floating	O
Point	O
Systems	O
(	O
FPS	O
)	O
built	O
add-on	O
array	B-Operating_System
processors	I-Operating_System
for	O
minicomputers	B-Architecture
,	O
later	O
building	O
their	O
own	O
minisupercomputers	B-Device
.	O
</s>
<s>
Throughout	O
,	O
Cray	O
continued	O
to	O
be	O
the	O
performance	O
leader	O
,	O
continually	O
beating	O
the	O
competition	O
with	O
a	O
series	O
of	O
machines	O
that	O
led	O
to	O
the	O
Cray-2	B-Device
,	O
Cray	B-Device
X-MP	I-Device
and	O
Cray	B-Device
Y-MP	I-Device
.	O
</s>
<s>
Since	O
then	O
,	O
the	O
supercomputer	B-Architecture
market	O
has	O
focused	O
much	O
more	O
on	O
massively	B-Operating_System
parallel	I-Operating_System
processing	I-Operating_System
rather	O
than	O
better	O
implementations	O
of	O
vector	B-Operating_System
processors	I-Operating_System
.	O
</s>
<s>
However	O
,	O
recognising	O
the	O
benefits	O
of	O
vector	B-Operating_System
processing	I-Operating_System
,	O
IBM	O
developed	O
Virtual	B-Device
Vector	I-Device
Architecture	I-Device
for	O
use	O
in	O
supercomputers	B-Architecture
coupling	O
several	O
scalar	B-General_Concept
processors	I-General_Concept
to	O
act	O
as	O
a	O
vector	B-Operating_System
processor	I-Operating_System
.	O
</s>
<s>
Although	O
vector	O
supercomputers	B-Architecture
resembling	O
the	O
Cray-1	B-Device
are	O
less	O
popular	O
these	O
days	O
,	O
NEC	O
has	O
continued	O
to	O
make	O
this	O
type	O
of	O
computer	O
up	O
to	O
the	O
present	O
day	O
with	O
their	O
SX	B-Device
series	I-Device
of	O
computers	O
.	O
</s>
<s>
Most	O
recently	O
,	O
the	O
SX-Aurora	B-Device
TSUBASA	I-Device
places	O
the	O
processor	O
and	O
either	O
24	O
or	O
48	O
gigabytes	O
of	O
memory	O
on	O
an	O
HBM	O
2	O
module	O
within	O
a	O
card	O
that	O
physically	O
resembles	O
a	O
graphics	B-Architecture
coprocessor	I-Architecture
,	O
but	O
instead	O
of	O
serving	O
as	O
a	O
co-processor	B-General_Concept
,	O
it	O
is	O
the	O
main	O
computer	O
with	O
the	O
PC-compatible	O
computer	O
into	O
which	O
it	O
is	O
plugged	O
serving	O
support	O
functions	O
.	O
</s>
<s>
Modern	O
graphics	B-Architecture
processing	I-Architecture
units	I-Architecture
(	O
GPUs	B-Architecture
)	O
include	O
an	O
array	O
of	O
shader	O
pipelines	B-General_Concept
which	O
may	O
be	O
driven	O
by	O
compute	B-Operating_System
kernels	I-Operating_System
,	O
and	O
can	O
be	O
considered	O
vector	B-Operating_System
processors	I-Operating_System
(	O
using	O
a	O
similar	O
strategy	O
for	O
hiding	O
memory	B-General_Concept
latencies	I-General_Concept
)	O
.	O
</s>
<s>
As	O
shown	O
in	O
Flynn	B-Operating_System
's	I-Operating_System
1972	I-Operating_System
paper	I-Operating_System
the	O
key	O
distinguishing	O
factor	O
of	O
SIMT-based	O
GPUs	B-Architecture
is	O
that	O
it	O
has	O
a	O
single	O
instruction	O
decoder-broadcaster	O
but	O
that	O
the	O
cores	O
receiving	O
and	O
executing	O
that	O
same	O
instruction	O
are	O
otherwise	O
reasonably	O
normal	O
:	O
their	O
own	O
ALUs	O
,	O
their	O
own	O
register	O
files	O
,	O
their	O
own	O
Load/Store	O
units	O
and	O
their	O
own	O
independent	O
L1	O
data	O
caches	O
.	O
</s>
<s>
This	O
is	O
significantly	O
more	O
complex	O
and	O
involved	O
than	O
"	O
Packed	O
SIMD	B-Device
"	O
,	O
which	O
is	O
strictly	O
limited	O
to	O
execution	O
of	O
parallel	O
pipelined	O
arithmetic	O
operations	O
only	O
.	O
</s>
<s>
Although	O
the	O
exact	O
internal	O
details	O
of	O
today	O
's	O
commercial	O
GPUs	B-Architecture
are	O
proprietary	O
secrets	O
,	O
the	O
MIAOW	O
team	O
was	O
able	O
to	O
piece	O
together	O
anecdotal	O
information	O
sufficient	O
to	O
implement	O
a	O
subset	O
of	O
the	O
AMDGPU	O
architecture	O
.	O
</s>
<s>
Several	O
modern	O
CPU	B-General_Concept
architectures	O
are	O
being	O
designed	O
as	O
vector	B-Operating_System
processors	I-Operating_System
.	O
</s>
<s>
The	O
RISC-V	B-Device
vector	O
extension	O
follows	O
similar	O
principles	O
as	O
the	O
early	O
vector	B-Operating_System
processors	I-Operating_System
,	O
and	O
is	O
being	O
implemented	O
in	O
commercial	O
products	O
such	O
as	O
the	O
Andes	O
Technology	O
AX45MPV	O
.	O
</s>
<s>
There	O
are	O
also	O
several	O
open	B-License
source	I-License
vector	B-Operating_System
processor	I-Operating_System
architectures	O
being	O
developed	O
,	O
including	O
ForwardCom	O
and	O
Libre-SOC	B-General_Concept
.	O
</s>
<s>
most	O
commodity	O
CPUs	O
implement	O
architectures	O
that	O
feature	O
fixed-length	O
SIMD	B-Device
instructions	O
.	O
</s>
<s>
On	O
first	O
inspection	O
these	O
can	O
be	O
considered	O
a	O
form	O
of	O
vector	B-Operating_System
processing	I-Operating_System
because	O
they	O
operate	O
on	O
multiple	O
(	O
vectorized	O
,	O
explicit	O
length	O
)	O
data	B-General_Concept
sets	I-General_Concept
,	O
and	O
borrow	O
features	O
from	O
vector	B-Operating_System
processors	I-Operating_System
.	O
</s>
<s>
However	O
by	O
definition	O
the	O
addition	O
of	O
SIMD	B-Device
cannot	O
by	O
itself	O
qualify	O
a	O
processor	O
as	O
an	O
actual	O
Vector	B-Operating_System
Processor	I-Operating_System
because	O
SIMD	B-Device
is	O
fixed-length	O
and	O
Vectors	O
are	O
variable	O
.	O
</s>
<s>
The	O
difference	O
is	O
illustrated	O
below	O
with	O
examples	O
,	O
showing	O
and	O
comparing	O
the	O
three	O
categories	O
:	O
Pure	O
SIMD	B-Device
,	O
Predicated	O
SIMD	B-Device
,	O
and	O
Pure	O
Vector	B-Operating_System
Processing	I-Operating_System
.	O
</s>
<s>
Pure	O
(	O
fixed	O
)	O
SIMD	B-Device
-	O
also	O
known	O
as	O
"	O
Packed	O
SIMD	B-Device
"	O
,	O
SIMD	B-General_Concept
within	I-General_Concept
a	I-General_Concept
Register	I-General_Concept
(	O
SWAR	B-General_Concept
)	O
,	O
and	O
Pipelined	B-General_Concept
Processor	I-General_Concept
in	O
Flynn	B-Operating_System
's	I-Operating_System
Taxonomy	I-Operating_System
.	O
</s>
<s>
Common	O
examples	O
using	O
SIMD	B-Device
with	O
features	O
inspired	O
by	O
Vector	B-Operating_System
processors	I-Operating_System
include	O
Intel	B-Operating_System
x86	I-Operating_System
's	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
and	O
AVX	B-General_Concept
instructions	O
,	O
AMD	O
's	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
extensions	O
,	O
ARM	O
NEON	O
,	O
Sparc	O
's	O
VIS	B-General_Concept
extension	O
,	O
PowerPC	B-Architecture
's	O
AltiVec	B-General_Concept
and	O
MIPS	O
 '	O
MSA	O
.	O
</s>
<s>
In	O
2000	O
,	O
IBM	O
,	O
Toshiba	O
and	O
Sony	O
collaborated	O
to	O
create	O
the	O
Cell	B-General_Concept
processor	I-General_Concept
,	O
which	O
is	O
also	O
SIMD	B-Device
.	O
</s>
<s>
Predicated	O
SIMD	B-Device
-	O
also	O
known	O
as	O
associative	O
processing	O
.	O
</s>
<s>
Pure	O
Vectors	O
-	O
as	O
categorised	O
in	O
Duncan	O
's	O
taxonomy	O
-these	O
include	O
the	O
original	O
Cray-1	B-Device
,	O
RISC-V	B-Device
RVV	O
and	O
SX-Aurora	B-Device
TSUBASA	I-Device
.	O
</s>
<s>
Although	O
memory-based	O
the	O
STAR-100	B-Device
was	O
also	O
a	O
Vector	B-Operating_System
Processor	I-Operating_System
.	O
</s>
<s>
Other	O
CPU	B-General_Concept
designs	O
include	O
some	O
multiple	O
instructions	O
for	O
vector	B-Operating_System
processing	I-Operating_System
on	O
multiple	O
(	O
vectorised	O
)	O
data	B-General_Concept
sets	I-General_Concept
,	O
typically	O
known	O
as	O
MIMD	B-Operating_System
(	O
Multiple	B-Operating_System
Instruction	I-Operating_System
,	I-Operating_System
Multiple	I-Operating_System
Data	I-Operating_System
)	O
and	O
realized	O
with	O
VLIW	B-General_Concept
(	O
Very	B-General_Concept
Long	I-General_Concept
Instruction	I-General_Concept
Word	I-General_Concept
)	O
.	O
</s>
<s>
The	O
Fujitsu	B-General_Concept
FR-V	I-General_Concept
VLIW/vector	O
processor	O
combines	O
both	O
technologies	O
.	O
</s>
<s>
SIMD	B-Device
instruction	B-General_Concept
sets	I-General_Concept
lack	O
crucial	O
features	O
when	O
compared	O
to	O
vector	B-Operating_System
processor	I-Operating_System
instruction	B-General_Concept
sets	I-General_Concept
.	O
</s>
<s>
The	O
most	O
important	O
of	O
these	O
is	O
that	O
vector	B-Operating_System
processors	I-Operating_System
,	O
inherently	O
by	O
definition	O
and	O
design	O
,	O
have	O
always	O
been	O
variable-length	O
since	O
their	O
inception	O
.	O
</s>
<s>
Where	O
pure	O
(	O
fixed-width	O
,	O
no	O
predication	B-General_Concept
)	O
SIMD	B-Device
is	O
commonly	O
mistakenly	O
claimed	O
to	O
be	O
"	O
vectors	O
"	O
(	O
because	O
SIMD	B-Device
processes	O
data	O
which	O
happens	O
to	O
be	O
vectors	O
)	O
,	O
through	O
close	O
analysis	O
and	O
comparison	O
of	O
historic	O
and	O
modern	O
ISAs	O
,	O
actual	O
vector	B-Operating_System
processors	I-Operating_System
may	O
be	O
observed	O
to	O
have	O
the	O
following	O
features	O
that	O
no	O
SIMD	B-Device
ISA	O
has	O
:	O
</s>
<s>
RISC-V	B-Device
vectors	O
as	O
of	O
version	O
0.10	O
have	O
reduction	O
only	O
,	O
whilst	O
the	O
SX-Aurora	O
and	O
later	O
Cray	O
systems	O
have	O
iteration	O
as	O
well	O
as	O
reduction	O
.	O
</s>
<s>
Predicated	O
SIMD	B-Device
(	O
part	O
of	O
Flynn	B-Operating_System
's	I-Operating_System
taxonomy	I-Operating_System
)	O
which	O
is	O
comprehensive	O
individual	O
element-level	O
predicate	B-General_Concept
masks	I-General_Concept
on	O
every	O
vector	O
instruction	O
as	O
is	O
now	O
available	O
in	O
ARM	O
SVE2	O
.	O
</s>
<s>
and	O
AVX-512	B-General_Concept
,	O
almost	O
qualifies	O
as	O
a	O
vector	B-Operating_System
processor	I-Operating_System
.	O
</s>
<s>
Predicated	O
SIMD	B-Device
uses	O
fixed-width	O
SIMD	B-Device
ALUs	O
but	O
allows	O
locally	O
controlled	O
(	O
predicated	O
)	O
activation	O
of	O
units	O
to	O
provide	O
the	O
appearance	O
of	O
variable	O
length	O
vectors	O
.	O
</s>
<s>
SIMD	B-Device
,	O
due	O
to	O
it	O
being	O
fixed	O
width	O
batch	O
processing	O
,	O
is	O
unable	O
by	O
design	O
to	O
cope	O
with	O
iteration	O
and	O
reduction	O
.	O
</s>
<s>
Additionally	O
,	O
vector	B-Operating_System
processors	I-Operating_System
can	O
be	O
more	O
resource-efficient	O
(	O
use	O
slower	O
hardware	O
,	O
saving	O
power	O
,	O
but	O
still	O
achieving	O
throughput	O
)	O
and	O
have	O
less	O
latency	O
than	O
SIMD	B-Device
,	O
through	O
vector	B-Device
chaining	I-Device
.	O
</s>
<s>
Consider	O
both	O
a	O
SIMD	B-Device
processor	O
and	O
a	O
vector	B-Operating_System
processor	I-Operating_System
working	O
on	O
4	O
64-bit	O
elements	O
,	O
doing	O
a	O
LOAD	O
,	O
ADD	O
,	O
MULTIPLY	O
and	O
STORE	O
sequence	O
.	O
</s>
<s>
If	O
the	O
SIMD	B-Device
width	O
is	O
4	O
,	O
then	O
the	O
SIMD	B-Device
processor	O
must	O
LOAD	O
four	O
elements	O
entirely	O
before	O
it	O
can	O
move	O
on	O
to	O
the	O
ADDs	O
,	O
must	O
complete	O
all	O
the	O
ADDs	O
before	O
it	O
can	O
move	O
on	O
to	O
the	O
MULTIPLYs	O
,	O
and	O
likewise	O
must	O
complete	O
all	O
of	O
the	O
MULTIPLYs	O
before	O
it	O
can	O
start	O
the	O
STOREs	O
.	O
</s>
<s>
To	O
avoid	O
these	O
high	O
costs	O
,	O
a	O
SIMD	B-Device
processor	O
would	O
have	O
to	O
have	O
1-wide	O
64-bit	O
LOAD	O
,	O
1-wide	O
64-bit	O
STORE	O
,	O
and	O
only	O
2-wide	O
64-bit	O
ALUs	O
.	O
</s>
<s>
As	O
shown	O
in	O
the	O
diagram	O
,	O
which	O
assumes	O
a	O
multi-issue	B-General_Concept
execution	I-General_Concept
model	I-General_Concept
,	O
the	O
consequences	O
are	O
that	O
the	O
operations	O
now	O
take	O
longer	O
to	O
complete	O
.	O
</s>
<s>
If	O
there	O
are	O
only	O
4-wide	O
64-bit	O
SIMD	B-Device
ALUs	O
,	O
the	O
completion	O
time	O
is	O
even	O
worse	O
:	O
only	O
when	O
all	O
four	O
LOADs	O
have	O
completed	O
may	O
the	O
SIMD	B-Device
operations	O
start	O
,	O
and	O
only	O
when	O
all	O
ALU	O
operations	O
have	O
completed	O
may	O
the	O
STOREs	O
begin	O
.	O
</s>
<s>
A	O
vector	B-Operating_System
processor	I-Operating_System
by	O
contrast	O
,	O
even	O
if	O
it	O
is	O
single-issue	O
and	O
uses	O
no	O
SIMD	B-Device
ALUs	O
,	O
only	O
having	O
1-wide	O
64-bit	O
LOAD	O
,	O
1-wide	O
64-bit	O
STORE	O
(	O
and	O
,	O
as	O
in	O
the	O
Cray-1	B-Device
,	O
the	O
ability	O
to	O
run	O
MULTIPLY	O
simultaneously	O
with	O
ADD	O
)	O
,	O
may	O
complete	O
the	O
four	O
operations	O
faster	O
than	O
a	O
SIMD	B-Device
processor	O
with	O
1-wide	O
LOAD	O
,	O
1-wide	O
STORE	O
,	O
and	O
2-wide	O
SIMD	B-Device
.	O
</s>
<s>
This	O
more	O
efficient	O
resource	O
utilisation	O
,	O
due	O
to	O
vector	B-Device
chaining	I-Device
,	O
is	O
a	O
key	O
advantage	O
and	O
difference	O
compared	O
to	O
SIMD	B-Device
.	O
</s>
<s>
SIMD	B-Device
by	O
design	O
and	O
definition	O
cannot	O
perform	O
chaining	B-Device
except	O
to	O
the	O
entire	O
group	O
of	O
results	O
.	O
</s>
<s>
For	O
instance	O
,	O
most	O
CPUs	O
have	O
an	O
instruction	O
that	O
essentially	O
says	O
"	O
add	O
A	O
to	O
B	O
and	O
put	O
the	O
result	O
in	O
C	B-Language
"	O
.	O
</s>
<s>
The	O
data	O
for	O
A	O
,	O
B	O
and	O
C	B-Language
could	O
be	O
—	O
in	O
theory	O
at	O
least	O
—	O
encoded	O
directly	O
into	O
the	O
instruction	O
.	O
</s>
<s>
Decoding	O
this	O
address	O
and	O
getting	O
the	O
data	O
out	O
of	O
the	O
memory	O
takes	O
some	O
time	O
,	O
during	O
which	O
the	O
CPU	B-General_Concept
traditionally	O
would	O
sit	O
idle	O
waiting	O
for	O
the	O
requested	O
data	O
to	O
show	O
up	O
.	O
</s>
<s>
As	O
CPU	B-General_Concept
speeds	O
have	O
increased	O
,	O
this	O
memory	B-General_Concept
latency	I-General_Concept
has	O
historically	O
become	O
a	O
large	O
impediment	O
to	O
performance	O
;	O
see	O
Memory	O
wall	O
.	O
</s>
<s>
In	O
order	O
to	O
reduce	O
the	O
amount	O
of	O
time	O
consumed	O
by	O
these	O
steps	O
,	O
most	O
modern	O
CPUs	O
use	O
a	O
technique	O
known	O
as	O
instruction	B-General_Concept
pipelining	I-General_Concept
in	O
which	O
the	O
instructions	O
pass	O
through	O
several	O
sub-units	O
in	O
turn	O
.	O
</s>
<s>
With	O
pipelining	B-General_Concept
the	O
"	O
trick	O
"	O
is	O
to	O
start	O
decoding	O
the	O
next	O
instruction	O
even	O
before	O
the	O
first	O
has	O
left	O
the	O
CPU	B-General_Concept
,	O
in	O
the	O
fashion	O
of	O
an	O
assembly	O
line	O
,	O
so	O
the	O
address	B-Device
decoder	I-Device
is	O
constantly	O
in	O
use	O
.	O
</s>
<s>
Any	O
particular	O
instruction	O
takes	O
the	O
same	O
amount	O
of	O
time	O
to	O
complete	O
,	O
a	O
time	O
known	O
as	O
the	O
latency	O
,	O
but	O
the	O
CPU	B-General_Concept
can	O
process	O
an	O
entire	O
batch	O
of	O
operations	O
,	O
in	O
an	O
overlapping	O
fashion	O
,	O
much	O
faster	O
and	O
more	O
efficiently	O
than	O
if	O
it	O
did	O
so	O
one	O
at	O
a	O
time	O
.	O
</s>
<s>
Vector	B-Operating_System
processors	I-Operating_System
take	O
this	O
concept	O
one	O
step	O
further	O
.	O
</s>
<s>
Instead	O
of	O
pipelining	B-General_Concept
just	O
the	O
instructions	O
,	O
they	O
also	O
pipeline	B-General_Concept
the	O
data	O
itself	O
.	O
</s>
<s>
To	O
the	O
CPU	B-General_Concept
,	O
this	O
would	O
look	O
something	O
like	O
this	O
:	O
</s>
<s>
But	O
to	O
a	O
vector	B-Operating_System
processor	I-Operating_System
,	O
this	O
task	O
looks	O
considerably	O
different	O
:	O
</s>
<s>
With	O
the	O
length	O
(	O
equivalent	O
to	O
SIMD	B-Device
width	O
)	O
not	O
being	O
hard-coded	O
into	O
the	O
instruction	O
,	O
not	O
only	O
is	O
the	O
encoding	O
more	O
compact	O
,	O
it	O
's	O
also	O
"	O
future-proof	O
"	O
and	O
allows	O
even	O
embedded	B-Architecture
processor	I-Architecture
designs	O
to	O
consider	O
using	O
vectors	O
purely	O
to	O
gain	O
all	O
the	O
other	O
advantages	O
,	O
rather	O
than	O
go	O
for	O
high	O
performance	O
.	O
</s>
<s>
Additionally	O
,	O
in	O
more	O
modern	O
vector	B-Operating_System
processor	I-Operating_System
ISAs	O
,	O
"	O
Fail	O
on	O
First	O
"	O
or	O
"	O
Fault	O
First	O
"	O
has	O
been	O
introduced	O
(	O
see	O
below	O
)	O
which	O
brings	O
even	O
more	O
advantages	O
.	O
</s>
<s>
But	O
more	O
than	O
that	O
,	O
a	O
high	O
performance	O
vector	B-Operating_System
processor	I-Operating_System
may	O
have	O
multiple	O
functional	B-General_Concept
units	I-General_Concept
adding	O
those	O
numbers	O
in	O
parallel	O
.	O
</s>
<s>
Including	O
these	O
types	O
of	O
instructions	O
necessarily	O
adds	O
complexity	O
to	O
the	O
core	O
CPU	B-General_Concept
.	O
</s>
<s>
(	O
This	O
can	O
be	O
somewhat	O
mitigated	O
by	O
keeping	O
the	O
entire	O
ISA	O
to	O
RISC	B-Architecture
principles	O
:	O
RVV	O
only	O
adds	O
around	O
190	O
vector	O
instructions	O
even	O
with	O
the	O
advanced	O
features	O
.	O
)	O
</s>
<s>
Vector	B-Operating_System
processors	I-Operating_System
were	O
traditionally	O
designed	O
to	O
work	O
best	O
only	O
when	O
there	O
are	O
large	O
amounts	O
of	O
data	O
to	O
be	O
worked	O
on	O
.	O
</s>
<s>
For	O
this	O
reason	O
,	O
these	O
sorts	O
of	O
CPUs	O
were	O
found	O
primarily	O
in	O
supercomputers	B-Architecture
,	O
as	O
the	O
supercomputers	B-Architecture
themselves	O
were	O
,	O
in	O
general	O
,	O
found	O
in	O
places	O
such	O
as	O
weather	O
prediction	O
centers	O
and	O
physics	O
labs	O
,	O
where	O
huge	O
amounts	O
of	O
data	O
are	O
"	O
crunched	O
"	O
.	O
</s>
<s>
However	O
,	O
as	O
shown	O
above	O
and	O
demonstrated	O
by	O
RISC-V	B-Device
RVV	O
the	O
efficiency	O
of	O
vector	O
ISAs	O
brings	O
other	O
benefits	O
which	O
are	O
compelling	O
even	O
for	O
Embedded	O
use-cases	O
.	O
</s>
<s>
The	O
vector	O
pseudocode	O
example	O
above	O
comes	O
with	O
a	O
big	O
assumption	O
that	O
the	O
vector	B-Operating_System
computer	I-Operating_System
can	O
process	O
more	O
than	O
ten	O
numbers	O
in	O
one	O
batch	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
the	O
vector	B-Operating_System
processor	I-Operating_System
either	O
gains	O
the	O
ability	O
to	O
perform	O
loops	O
itself	O
,	O
or	O
exposes	O
some	O
sort	O
of	O
vector	O
control	O
(	O
status	O
)	O
register	O
to	O
the	O
programmer	O
,	O
usually	O
known	O
as	O
a	O
vector	O
Length	O
.	O
</s>
<s>
The	O
self-repeating	O
instructions	O
are	O
found	O
in	O
early	O
vector	B-Operating_System
computers	I-Operating_System
like	O
the	O
STAR-100	B-Device
,	O
where	O
the	O
above	O
action	O
would	O
be	O
described	O
in	O
a	O
single	O
instruction	O
(	O
somewhat	O
like	O
)	O
.	O
</s>
<s>
They	O
are	O
also	O
found	O
in	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
as	O
the	O
prefix	O
.	O
</s>
<s>
Since	O
all	O
operands	O
have	O
to	O
be	O
in	O
memory	O
for	O
the	O
STAR-100	B-Device
architecture	O
,	O
the	O
latency	O
caused	O
by	O
access	O
became	O
huge	O
too	O
.	O
</s>
<s>
Interestingly	O
,	O
though	O
,	O
Broadcom	O
included	O
space	O
in	O
all	O
vector	O
operations	O
of	O
the	O
Videocore	B-General_Concept
IV	O
ISA	O
for	O
a	O
field	O
,	O
but	O
unlike	O
the	O
STAR-100	B-Device
which	O
uses	O
memory	O
for	O
its	O
repeats	O
,	O
the	O
Videocore	B-General_Concept
IV	O
repeats	O
are	O
on	O
all	O
operations	O
including	O
arithmetic	O
vector	O
operations	O
.	O
</s>
<s>
The	O
Cray-1	B-Device
introduced	O
the	O
idea	O
of	O
using	O
processor	B-General_Concept
registers	I-General_Concept
to	O
hold	O
vector	O
data	O
in	O
batches	O
.	O
</s>
<s>
The	O
batch	O
lengths	O
(	O
vector	O
length	O
,	O
VL	O
)	O
could	O
be	O
dynamically	O
set	O
with	O
a	O
special	O
instruction	O
,	O
the	O
significance	O
compared	O
to	O
Videocore	B-General_Concept
IV	O
(	O
and	O
,	O
crucially	O
as	O
will	O
be	O
shown	O
below	O
,	O
SIMD	B-Device
as	O
well	O
)	O
being	O
that	O
the	O
repeat	O
length	O
does	O
not	O
have	O
to	O
be	O
part	O
of	O
the	O
instruction	O
encoding	O
.	O
</s>
<s>
This	O
is	O
sometimes	O
claimed	O
to	O
be	O
a	O
disadvantage	O
of	O
Cray-style	O
vector	B-Operating_System
processors	I-Operating_System
:	O
in	O
reality	O
it	O
is	O
part	O
of	O
achieving	O
high	O
performance	O
throughput	O
,	O
as	O
seen	O
in	O
GPUs	B-Architecture
,	O
which	O
face	O
exactly	O
the	O
same	O
issue	O
.	O
</s>
<s>
Modern	O
SIMD	B-Device
computers	O
claim	O
to	O
improve	O
on	O
early	O
Cray	O
by	O
directly	O
using	O
multiple	O
ALUs	O
,	O
for	O
a	O
higher	O
degree	O
of	O
parallelism	O
compared	O
to	O
only	O
using	O
the	O
normal	O
scalar	O
pipeline	B-General_Concept
.	O
</s>
<s>
Modern	O
vector	B-Operating_System
processors	I-Operating_System
(	O
such	O
as	O
the	O
SX-Aurora	B-Device
TSUBASA	I-Device
)	O
combine	O
both	O
,	O
by	O
issuing	O
multiple	O
data	O
to	O
multiple	O
internal	O
pipelined	O
SIMD	B-Device
ALUs	O
,	O
the	O
number	O
issued	O
being	O
dynamically	O
chosen	O
by	O
the	O
vector	O
program	O
at	O
runtime	O
.	O
</s>
<s>
Masks	O
can	O
be	O
used	O
to	O
selectively	O
load	O
and	O
store	O
data	O
in	O
memory	O
locations	O
,	O
and	O
use	O
those	O
same	O
masks	O
to	O
selectively	O
disable	O
processing	O
element	O
of	O
SIMD	B-Device
ALUs	O
.	O
</s>
<s>
Some	O
processors	O
with	O
SIMD	B-Device
(	O
AVX-512	B-General_Concept
,	O
ARM	O
SVE2	O
)	O
are	O
capable	O
of	O
this	O
kind	O
of	O
selective	O
,	O
per-element	O
(	O
"	B-General_Concept
predicated	I-General_Concept
"	I-General_Concept
)	O
processing	O
,	O
and	O
it	O
is	O
these	O
which	O
somewhat	O
deserve	O
the	O
nomenclature	O
"	O
vector	B-Operating_System
processor	I-Operating_System
"	O
or	O
at	O
least	O
deserve	O
the	O
claim	O
of	O
being	O
capable	O
of	O
"	O
vector	B-Operating_System
processing	I-Operating_System
"	O
.	O
</s>
<s>
(	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
AltiVec	B-General_Concept
)	O
categorically	O
do	O
not	O
.	O
</s>
<s>
Modern	O
GPUs	B-Architecture
,	O
which	O
have	O
many	O
small	O
compute	O
units	O
each	O
with	O
their	O
own	O
independent	O
SIMD	B-Device
ALUs	O
,	O
use	O
Single	B-General_Concept
Instruction	I-General_Concept
Multiple	I-General_Concept
Threads	I-General_Concept
(	O
SIMT	O
)	O
.	O
</s>
<s>
The	O
"	O
vector	O
registers	O
"	O
are	O
very	O
wide	O
and	O
the	O
pipelines	B-General_Concept
tend	O
to	O
be	O
long	O
.	O
</s>
<s>
In	O
addition	O
,	O
GPUs	B-Architecture
such	O
as	O
the	O
Broadcom	O
Videocore	B-General_Concept
IV	O
and	O
other	O
external	O
vector	B-Operating_System
processors	I-Operating_System
like	O
the	O
NEC	B-Device
SX-Aurora	I-Device
TSUBASA	I-Device
may	O
use	O
fewer	O
vector	O
units	O
than	O
the	O
width	O
implies	O
:	O
instead	O
of	O
having	O
64	O
units	O
for	O
a	O
64-number-wide	O
register	O
,	O
the	O
hardware	O
might	O
instead	O
do	O
a	O
pipelined	O
loop	O
over	O
16	O
units	O
for	O
a	O
hybrid	O
approach	O
.	O
</s>
<s>
The	O
Broadcom	O
Videocore	B-General_Concept
IV	O
is	O
also	O
capable	O
of	O
this	O
hybrid	O
approach	O
:	O
nominally	O
stating	O
that	O
its	O
SIMD	B-Device
QPU	O
Engine	O
supports	O
16-long	O
FP	O
array	O
operations	O
in	O
its	O
instructions	O
,	O
it	O
actually	O
does	O
them	O
4	O
at	O
a	O
time	O
,	O
as	O
(	O
another	O
)	O
form	O
of	O
"	O
threads	O
"	O
.	O
</s>
<s>
This	O
example	O
starts	O
with	O
an	O
algorithm	O
(	O
"	O
IAXPY	O
"	O
)	O
,	O
first	O
show	O
it	O
in	O
scalar	O
instructions	O
,	O
then	O
SIMD	B-Device
,	O
then	O
predicated	O
SIMD	B-Device
,	O
and	O
finally	O
vector	O
instructions	O
.	O
</s>
<s>
This	O
incrementally	O
helps	O
illustrate	O
the	O
difference	O
between	O
a	O
traditional	O
vector	B-Operating_System
processor	I-Operating_System
and	O
a	O
modern	O
SIMD	B-Device
one	O
.	O
</s>
<s>
The	O
example	O
starts	O
with	O
a	O
32-bit	O
integer	O
variant	O
of	O
the	O
"	O
DAXPY	O
"	O
function	O
,	O
in	O
C	B-Language
:	O
</s>
<s>
The	O
STAR-like	O
code	O
remains	O
concise	O
,	O
but	O
because	O
the	O
STAR-100	B-Device
'	O
s	O
vectorisation	O
was	O
by	O
design	O
based	O
around	O
memory	O
accesses	O
,	O
an	O
extra	O
slot	O
of	O
memory	O
is	O
now	O
required	O
to	O
process	O
the	O
information	O
.	O
</s>
<s>
A	O
modern	O
packed	O
SIMD	B-Device
architecture	O
,	O
known	O
by	O
many	O
names	O
(	O
listed	O
in	O
Flynn	B-Operating_System
's	I-Operating_System
taxonomy	I-Operating_System
)	O
,	O
can	O
do	O
most	O
of	O
the	O
operation	O
in	O
batches	O
.	O
</s>
<s>
It	O
is	O
assumed	O
that	O
both	O
x	O
and	O
y	O
are	O
properly	B-Application
aligned	I-Application
here	O
(	O
only	O
start	O
on	O
a	O
multiple	O
of	O
16	O
)	O
and	O
that	O
n	O
is	O
a	O
multiple	O
of	O
4	O
,	O
as	O
otherwise	O
some	O
setup	O
code	O
would	O
be	O
needed	O
to	O
calculate	O
a	O
mask	O
or	O
to	O
run	O
a	O
scalar	O
version	O
.	O
</s>
<s>
It	O
can	O
also	O
be	O
assumed	O
,	O
for	O
simplicity	O
,	O
that	O
the	O
SIMD	B-Device
instructions	O
have	O
an	O
option	O
to	O
automatically	O
repeat	O
scalar	O
operands	O
,	O
like	O
ARM	O
NEON	O
can	O
.	O
</s>
<s>
If	O
it	O
does	O
not	O
,	O
a	O
"	O
splat	O
"	O
(	O
broadcast	O
)	O
must	O
be	O
used	O
,	O
to	O
copy	O
the	O
scalar	O
argument	O
across	O
a	O
SIMD	B-Device
register	O
:	O
</s>
<s>
The	O
decision	O
was	O
made	O
that	O
the	O
algorithm	O
shall	O
only	O
cope	O
with	O
4-wide	O
SIMD	B-Device
,	O
therefore	O
the	O
constant	O
is	O
hard-coded	O
into	O
the	O
program	O
.	O
</s>
<s>
Unfortunately	O
for	O
SIMD	B-Device
,	O
the	O
clue	O
was	O
in	O
the	O
assumption	O
above	O
,	O
"	O
that	O
n	O
is	O
a	O
multiple	O
of	O
4	O
"	O
as	O
well	O
as	O
"	O
aligned	O
access	O
"	O
,	O
which	O
,	O
clearly	O
,	O
is	O
a	O
limited	O
specialist	O
use-case	O
.	O
</s>
<s>
Realistically	O
,	O
for	O
general-purpose	O
loops	O
such	O
as	O
in	O
portable	O
libraries	O
,	O
where	O
n	O
cannot	O
be	O
limited	O
in	O
this	O
way	O
,	O
the	O
overhead	O
of	O
setup	O
and	O
cleanup	O
for	O
SIMD	B-Device
in	O
order	O
to	O
cope	O
with	O
non-multiples	O
of	O
the	O
SIMD	B-Device
width	O
,	O
can	O
far	O
exceed	O
the	O
instruction	O
count	O
inside	O
the	O
loop	O
itself	O
.	O
</s>
<s>
Assuming	O
worst-case	O
that	O
the	O
hardware	O
cannot	O
do	O
misaligned	O
SIMD	B-Device
memory	O
accesses	O
,	O
a	O
real-world	O
algorithm	O
will	O
:	O
</s>
<s>
first	O
have	O
to	O
have	O
a	O
preparatory	O
section	O
which	O
works	O
on	O
the	O
beginning	O
unaligned	O
data	O
,	O
up	O
to	O
the	O
first	O
point	O
where	O
SIMD	B-Device
memory-aligned	O
operations	O
can	O
take	O
over	O
.	O
</s>
<s>
this	O
will	O
either	O
involve	O
(	O
slower	O
)	O
scalar-only	O
operations	O
or	O
smaller-sized	O
packed	O
SIMD	B-Device
operations	O
.	O
</s>
<s>
Eight-wide	O
SIMD	B-Device
requires	O
repeating	O
the	O
inner	O
loop	O
algorithm	O
first	O
with	O
four-wide	O
SIMD	B-Device
elements	O
,	O
then	O
two-wide	O
SIMD	B-Device
,	O
then	O
one	O
(	O
scalar	O
)	O
,	O
with	O
a	O
test	O
and	O
branch	O
in	O
between	O
each	O
one	O
,	O
in	O
order	O
to	O
cover	O
the	O
first	O
and	O
last	O
remaining	O
SIMD	B-Device
elements	O
(	O
0	O
<=	O
n	O
<=	O
7	O
)	O
.	O
</s>
<s>
This	O
can	O
easily	O
be	O
demonstrated	O
by	O
compiling	O
the	O
iaxpy	O
example	O
for	O
AVX-512	B-General_Concept
,	O
using	O
the	O
options	O
to	O
gcc	B-Application
.	O
</s>
<s>
Over	O
time	O
as	O
the	O
ISA	O
evolves	O
to	O
keep	O
increasing	O
performance	O
,	O
it	O
results	O
in	O
ISA	O
Architects	O
adding	O
2-wide	O
SIMD	B-Device
,	O
then	O
4-wide	O
SIMD	B-Device
,	O
then	O
8-wide	O
and	O
upwards	O
.	O
</s>
<s>
It	O
can	O
therefore	O
be	O
seen	O
why	O
AVX-512	B-General_Concept
exists	O
in	O
x86	B-Operating_System
.	O
</s>
<s>
Without	O
predication	B-General_Concept
,	O
the	O
wider	O
the	O
SIMD	B-Device
width	O
the	O
worse	O
the	O
problems	O
get	O
,	O
leading	O
to	O
massive	O
opcode	O
proliferation	O
,	O
degraded	O
performance	O
,	O
extra	O
power	O
consumption	O
and	O
unnecessary	O
software	O
complexity	O
.	O
</s>
<s>
Vector	B-Operating_System
processors	I-Operating_System
on	O
the	O
other	O
hand	O
are	O
designed	O
to	O
issue	O
computations	O
of	O
variable	O
length	O
for	O
an	O
arbitrary	O
count	O
,	O
n	O
,	O
and	O
thus	O
require	O
very	O
little	O
setup	O
,	O
and	O
no	O
cleanup	O
.	O
</s>
<s>
Even	O
compared	O
to	O
those	O
SIMD	B-Device
ISAs	O
which	O
have	O
masks	O
(	O
but	O
no	O
instruction	O
)	O
,	O
Vector	B-Operating_System
processors	I-Operating_System
produce	O
much	O
more	O
compact	O
code	O
because	O
they	O
do	O
not	O
need	O
to	O
perform	O
explicit	O
mask	O
calculation	O
to	O
cover	O
the	O
last	O
few	O
elements	O
(	O
illustrated	O
below	O
)	O
.	O
</s>
<s>
Assuming	O
a	O
hypothetical	O
predicated	O
(	O
mask	O
capable	O
)	O
SIMD	B-Device
ISA	O
,	O
and	O
again	O
assuming	O
that	O
the	O
SIMD	B-Device
instructions	O
can	O
cope	O
with	O
misaligned	O
data	O
,	O
the	O
instruction	O
loop	O
would	O
look	O
like	O
this	O
:	O
</s>
<s>
Here	O
it	O
can	O
be	O
seen	O
that	O
the	O
code	O
is	O
much	O
cleaner	O
but	O
a	O
little	O
complex	O
:	O
at	O
least	O
,	O
however	O
,	O
there	O
is	O
no	O
setup	O
or	O
cleanup	O
:	O
on	O
the	O
last	O
iteration	O
of	O
the	O
loop	O
,	O
the	O
predicate	O
mask	O
wil	O
be	O
set	O
to	O
either	O
0b0000	O
,	O
0b0001	O
,	O
0b0011	O
,	O
0b0111	O
or	O
0b1111	O
,	O
resulting	O
in	O
between	O
0	O
and	O
4	O
SIMD	B-Device
element	O
operations	O
being	O
performed	O
,	O
respectively	O
.	O
</s>
<s>
One	O
additional	O
potential	O
complication	O
:	O
some	O
RISC	B-Architecture
ISAs	O
do	O
not	O
have	O
a	O
"	O
min	O
"	O
instruction	O
,	O
needing	O
instead	O
to	O
use	O
a	O
branch	O
or	O
scalar	O
predicated	O
compare	O
.	O
</s>
<s>
It	O
is	O
clear	O
how	O
predicated	O
SIMD	B-Device
at	O
least	O
merits	O
the	O
term	O
"	O
vector	O
capable	O
"	O
,	O
because	O
it	O
can	O
cope	O
with	O
variable-length	O
vectors	O
by	O
using	O
predicate	B-General_Concept
masks	I-General_Concept
.	O
</s>
<s>
The	O
final	O
evolving	O
step	O
to	O
a	O
"	O
true	O
"	O
vector	O
ISA	O
,	O
however	O
,	O
is	O
to	O
not	O
have	O
any	O
evidence	O
in	O
the	O
ISA	O
at	O
all	O
of	O
a	O
SIMD	B-Device
width	O
,	O
leaving	O
that	O
entirely	O
up	O
to	O
the	O
hardware	O
.	O
</s>
<s>
Note	O
that	O
,	O
as	O
seen	O
in	O
SX-Aurora	O
and	O
Videocore	B-General_Concept
IV	O
,	O
MVL	O
may	O
be	O
an	O
actual	O
hardware	O
lane	O
quantity	O
or	O
a	O
virtual	O
one	O
.	O
</s>
<s>
This	O
can	O
be	O
a	O
little	O
disconcerting	O
after	O
years	O
of	O
SIMD	B-Device
mindset	O
)	O
.	O
</s>
<s>
Below	O
is	O
the	O
Cray-style	O
vector	O
assembler	O
for	O
the	O
same	O
SIMD	B-Device
style	O
loop	O
,	O
above	O
.	O
</s>
<s>
This	O
is	O
essentially	O
not	O
very	O
different	O
from	O
the	O
SIMD	B-Device
version	O
(	O
processes	O
4	O
data	O
elements	O
per	O
loop	O
)	O
,	O
or	O
from	O
the	O
initial	O
Scalar	O
version	O
(	O
processes	O
just	O
the	O
one	O
)	O
.	O
</s>
<s>
A	O
number	O
of	O
things	O
to	O
note	O
,	O
when	O
comparing	O
against	O
the	O
Predicated	O
SIMD	B-Device
assembly	O
variant	O
:	O
</s>
<s>
Where	O
the	O
SIMD	B-Device
variant	O
hard-coded	O
both	O
the	O
width	O
(	O
4	O
)	O
into	O
the	O
creation	O
of	O
the	O
mask	O
and	O
in	O
the	O
SIMD	B-Device
width	O
(	O
load32x4	O
etc	O
.	O
)	O
</s>
<s>
Where	O
with	O
predicated	O
SIMD	B-Device
the	O
mask	O
bitlength	O
is	O
limited	O
to	O
that	O
which	O
may	O
be	O
held	O
in	O
a	O
scalar	O
(	O
or	O
special	O
mask	O
)	O
register	O
,	O
vector	O
ISA	O
's	O
mask	O
registers	O
have	O
no	O
such	O
limitation	O
.	O
</s>
<s>
Also	O
note	O
,	O
that	O
just	O
like	O
the	O
predicated	O
SIMD	B-Device
variant	O
,	O
the	O
pointers	O
to	O
x	O
and	O
y	O
are	O
advanced	O
by	O
t0	O
times	O
four	O
because	O
they	O
both	O
point	O
to	O
32	O
bit	O
data	O
,	O
but	O
that	O
n	O
is	O
decremented	O
by	O
straight	O
t0	O
.	O
</s>
<s>
Compared	O
to	O
the	O
fixed-size	O
SIMD	B-Device
assembler	O
there	O
is	O
very	O
little	O
apparent	O
difference	O
:	O
x	O
and	O
y	O
are	O
advanced	O
by	O
hard-coded	O
constant	O
16	O
,	O
n	O
is	O
decremented	O
by	O
a	O
hard-coded	O
4	O
,	O
so	O
initially	O
it	O
is	O
hard	O
to	O
appreciate	O
the	O
significance	O
.	O
</s>
<s>
The	O
difference	O
comes	O
in	O
the	O
realisation	O
that	O
the	O
vector	O
hardware	O
could	O
be	O
capable	O
of	O
doing	O
4	O
simultaneous	O
operations	O
,	O
or	O
64	O
,	O
or	O
10	O
,	O
000	O
,	O
it	O
would	O
be	O
the	O
exact	O
same	O
vector	O
assembler	O
for	O
all	O
of	O
them	O
and	O
there	O
would	O
still	O
be	O
no	O
SIMD	B-Device
cleanup	O
code	O
.	O
</s>
<s>
Even	O
compared	O
to	O
the	O
predicate-capable	O
SIMD	B-Device
,	O
it	O
is	O
still	O
more	O
compact	O
,	O
clearer	O
,	O
more	O
elegant	O
and	O
uses	O
less	O
resources	O
.	O
</s>
<s>
This	O
sets	O
the	O
vector	O
length	O
to	O
zero	O
,	O
which	O
effectively	O
disables	O
all	O
vector	O
instructions	O
,	O
turning	O
them	O
into	O
no-ops	B-Language
,	O
at	O
runtime	O
.	O
</s>
<s>
Thus	O
,	O
unlike	O
non-predicated	O
SIMD	B-Device
,	O
even	O
when	O
there	O
are	O
no	O
elements	O
to	O
process	O
there	O
is	O
still	O
no	O
wasted	O
cleanup	O
code	O
.	O
</s>
<s>
Just	O
as	O
with	O
the	O
previous	O
example	O
,	O
it	O
will	O
be	O
first	O
shown	O
in	O
scalar	O
instructions	O
,	O
then	O
SIMD	B-Device
,	O
and	O
finally	O
vector	O
instructions	O
,	O
starting	O
in	O
c	B-Language
:	O
</s>
<s>
SIMD	B-Device
by	O
design	O
is	O
incapable	O
of	O
doing	O
arithmetic	O
operations	O
"	O
inter-element	O
"	O
.	O
</s>
<s>
Element	O
0	O
of	O
one	O
SIMD	B-Device
register	O
may	O
be	O
added	O
to	O
Element	O
0	O
of	O
another	O
register	O
,	O
but	O
Element	O
0	O
may	O
not	O
be	O
added	O
to	O
anything	O
other	O
than	O
another	O
Element	O
0	O
.	O
</s>
<s>
but	O
with	O
4-wide	O
SIMD	B-Device
being	O
incapable	O
by	O
design	O
of	O
adding	O
for	O
example	O
,	O
things	O
go	O
rapidly	O
downhill	O
just	O
as	O
they	O
did	O
with	O
the	O
general	O
case	O
of	O
using	O
SIMD	B-Device
for	O
general-purpose	O
IAXPY	O
loops	O
.	O
</s>
<s>
To	O
sum	O
the	O
four	O
partial	O
results	O
,	O
two-wide	O
SIMD	B-Device
can	O
be	O
used	O
,	O
followed	O
by	O
a	O
single	O
scalar	O
add	O
,	O
to	O
finally	O
produce	O
the	O
answer	O
,	O
but	O
,	O
frequently	O
,	O
the	O
data	O
must	O
be	O
transferred	O
out	O
of	O
dedicated	O
SIMD	B-Device
registers	O
before	O
the	O
last	O
scalar	O
computation	O
can	O
be	O
performed	O
.	O
</s>
<s>
Even	O
with	O
a	O
general	O
loop	O
(	O
n	O
not	O
fixed	O
)	O
,	O
the	O
only	O
way	O
to	O
use	O
4-wide	O
SIMD	B-Device
is	O
to	O
assume	O
four	O
separate	O
"	O
streams	O
"	O
,	O
each	O
offset	O
by	O
four	O
elements	O
.	O
</s>
<s>
Vector	O
instruction	B-General_Concept
sets	I-General_Concept
have	O
arithmetic	O
reduction	O
operations	O
built-in	O
to	O
the	O
ISA	O
.	O
</s>
<s>
The	O
simplicity	O
of	O
the	O
algorithm	O
is	O
stark	O
in	O
comparison	O
to	O
SIMD	B-Device
.	O
</s>
<s>
This	O
example	O
again	O
highlights	O
a	O
key	O
critical	O
fundamental	O
difference	O
between	O
true	O
vector	B-Operating_System
processors	I-Operating_System
and	O
those	O
SIMD	B-Device
processors	O
,	O
including	O
most	O
commercial	O
GPUs	B-Architecture
,	O
which	O
are	O
inspired	O
by	O
features	O
of	O
vector	B-Operating_System
processors	I-Operating_System
.	O
</s>
<s>
Compared	O
to	O
any	O
SIMD	B-Device
processor	O
claiming	O
to	O
be	O
a	O
vector	B-Operating_System
processor	I-Operating_System
,	O
the	O
order	O
of	O
magnitude	O
reduction	O
in	O
program	O
size	O
is	O
almost	O
shocking	O
.	O
</s>
<s>
From	O
the	O
IAXPY	O
example	O
,	O
it	O
can	O
be	O
seen	O
that	O
unlike	O
SIMD	B-Device
processors	O
,	O
which	O
can	O
simplify	O
their	O
internal	O
hardware	O
by	O
avoiding	O
dealing	O
with	O
misaligned	O
memory	O
access	O
,	O
a	O
vector	B-Operating_System
processor	I-Operating_System
cannot	O
get	O
away	O
with	O
such	O
simplification	O
:	O
algorithms	O
are	O
written	O
which	O
inherently	O
rely	O
on	O
Vector	O
Load	O
and	O
Store	O
being	O
successful	O
,	O
regardless	O
of	O
alignment	O
of	O
the	O
start	O
of	O
the	O
vector	O
.	O
</s>
<s>
Whilst	O
from	O
the	O
reduction	O
example	O
it	O
can	O
be	O
seen	O
that	O
,	O
aside	O
from	O
permute	B-Algorithm
instructions	I-Algorithm
,	O
SIMD	B-Device
by	O
definition	O
avoids	O
inter-lane	O
operations	O
entirely	O
(	O
element	O
0	O
can	O
only	O
be	O
added	O
to	O
another	O
element	O
0	O
)	O
,	O
vector	B-Operating_System
processors	I-Operating_System
tackle	O
this	O
head-on	O
.	O
</s>
<s>
What	O
programmers	O
are	O
forced	O
to	O
do	O
in	O
software	O
(	O
using	O
shuffle	O
and	O
other	O
tricks	O
,	O
to	O
swap	O
data	O
into	O
the	O
right	O
"	O
lane	O
"	O
)	O
vector	B-Operating_System
processors	I-Operating_System
must	O
do	O
in	O
hardware	O
,	O
automatically	O
.	O
</s>
<s>
These	O
stark	O
differences	O
are	O
what	O
distinguishes	O
a	O
vector	B-Operating_System
processor	I-Operating_System
from	O
one	O
that	O
has	O
SIMD	B-Device
.	O
</s>
<s>
Where	O
many	O
SIMD	B-Device
ISAs	O
borrow	O
or	O
are	O
inspired	O
by	O
the	O
list	O
below	O
,	O
typical	O
features	O
that	O
a	O
vector	B-Operating_System
processor	I-Operating_System
will	O
have	O
are	O
:	O
</s>
<s>
Vector	O
Load	O
and	O
Store	O
–	O
Vector	O
architectures	O
with	O
a	O
register-to-register	O
design	O
(	O
analogous	O
to	O
loadstore	O
architectures	O
for	O
scalar	B-General_Concept
processors	I-General_Concept
)	O
have	O
instructions	O
for	O
transferring	O
multiple	O
elements	O
between	O
the	O
memory	O
and	O
the	O
vector	O
registers	O
.	O
</s>
<s>
Segment	O
loads	O
read	O
a	O
vector	O
from	O
memory	O
,	O
where	O
each	O
element	O
is	O
a	O
data	B-General_Concept
structure	I-General_Concept
containing	O
multiple	O
members	O
.	O
</s>
<s>
The	O
members	O
are	O
extracted	O
from	O
data	B-General_Concept
structure	I-General_Concept
(	O
element	O
)	O
,	O
and	O
each	O
extracted	O
member	O
is	O
placed	O
into	O
a	O
different	O
vector	O
register	O
.	O
</s>
<s>
Masked	O
Operations	O
–	O
predicate	B-General_Concept
masks	I-General_Concept
allow	O
parallel	O
if/then/else	O
constructs	O
without	O
resorting	O
to	O
branches	O
.	O
</s>
<s>
Compress	O
and	O
Expand	O
–	O
usually	O
using	O
a	O
bit-mask	O
,	O
data	O
is	O
linearly	O
compressed	O
or	O
expanded	O
(	O
redistributed	O
)	O
based	O
on	O
whether	O
bits	O
in	O
the	O
mask	O
are	O
set	O
or	O
clear	O
,	O
whilst	O
always	O
preserving	O
the	O
sequential	O
order	O
and	O
never	O
duplicating	O
values	O
(	O
unlike	O
Gather-Scatter	B-General_Concept
aka	O
permute	O
)	O
.	O
</s>
<s>
These	O
instructions	O
feature	O
in	O
AVX-512	B-General_Concept
.	O
</s>
<s>
Gather/scatter	B-General_Concept
is	O
more	O
complex	O
to	O
implement	O
than	O
compress/expand	O
,	O
and	O
,	O
being	O
inherently	O
non-sequential	O
,	O
can	O
interfere	O
with	O
vector	B-Device
chaining	I-Device
.	O
</s>
<s>
Not	O
to	O
be	O
confused	O
with	O
Gather-scatter	B-General_Concept
Memory	O
Load/Store	O
modes	O
,	O
Gather/scatter	B-General_Concept
vector	O
operations	O
act	O
on	O
the	O
vector	O
registers	O
,	O
and	O
are	O
often	O
termed	O
a	O
permute	B-Algorithm
instruction	I-Algorithm
instead	O
.	O
</s>
<s>
Reduction	O
and	O
Iteration	O
–	O
operations	O
that	O
perform	O
mapreduce	B-Operating_System
on	O
a	O
vector	O
(	O
for	O
example	O
,	O
find	O
the	O
one	O
maximum	O
value	O
of	O
an	O
entire	O
vector	O
,	O
or	O
sum	O
all	O
elements	O
)	O
.	O
</s>
<s>
IBM	O
POWER10	O
provides	O
MMA	O
instructions	O
although	O
for	O
arbitrary	O
Matrix	O
widths	O
that	O
do	O
not	O
fit	O
the	O
exact	O
SIMD	B-Device
size	O
data	O
repetition	O
techniques	O
are	O
needed	O
which	O
is	O
wasteful	O
of	O
register	O
file	O
resources	O
.	O
</s>
<s>
NVidia	O
provides	O
a	O
high-level	O
Matrix	O
CUDA	B-Architecture
API	O
although	O
the	O
internal	O
details	O
are	O
not	O
available	O
.	O
</s>
<s>
Bit	B-Algorithm
manipulation	I-Algorithm
–	O
including	O
vectorised	O
versions	O
of	O
bit-level	O
permutation	O
operations	O
,	O
bitfield	O
insert	O
and	O
extract	O
,	O
centrifuge	O
operations	O
,	O
population	O
count	O
,	O
and	O
many	B-Device
others	I-Device
.	O
</s>
<s>
With	O
many	O
3D	O
shader	O
applications	O
needing	O
trigonometric	O
operations	O
as	O
well	O
as	O
short	O
vectors	O
for	O
common	O
operations	O
(	O
RGB	O
,	O
ARGB	O
,	O
XYZ	O
,	O
XYZW	O
)	O
support	O
for	O
the	O
following	O
is	O
typically	O
present	O
in	O
modern	O
GPUs	B-Architecture
,	O
in	O
addition	O
to	O
those	O
found	O
in	O
vector	B-Operating_System
processors	I-Operating_System
:	O
</s>
<s>
Sub-vectors	O
are	O
also	O
introduced	O
in	O
RISC-V	B-Device
RVV	O
(	O
termed	O
"	O
LMUL	O
"	O
)	O
.	O
</s>
<s>
Subvectors	O
are	O
a	O
critical	O
integral	O
part	O
of	O
the	O
Vulkan	B-Application
SPIR-V	B-Application
spec	O
.	O
</s>
<s>
Sub-vector	O
Swizzle	O
–	O
aka	O
"	O
Lane	O
Shuffling	O
"	O
which	O
allows	O
sub-vector	O
inter-element	O
computations	O
without	O
needing	O
extra	O
(	O
costly	O
,	O
wasteful	O
)	O
instructions	O
to	O
move	O
the	O
sub-elements	O
into	O
the	O
correct	O
SIMD	B-Device
"	O
lanes	O
"	O
and	O
also	O
saves	O
predicate	O
mask	O
bits	O
.	O
</s>
<s>
Effectively	O
this	O
is	O
an	O
in-flight	O
mini-permute	B-Algorithm
of	O
the	O
sub-vector	O
,	O
heavily	O
features	O
in	O
3D	O
Shader	O
binaries	O
,	O
and	O
is	O
sufficiently	O
important	O
as	O
to	O
be	O
part	O
of	O
the	O
Vulkan	B-Application
SPIR-V	B-Application
spec	O
.	O
</s>
<s>
The	O
Broadcom	O
Videocore	B-General_Concept
IV	O
uses	O
the	O
terminology	O
"	O
Lane	O
rotate	O
"	O
where	O
the	O
rest	O
of	O
the	O
industry	O
uses	O
the	O
term	O
"	B-General_Concept
swizzle	I-General_Concept
"	I-General_Concept
.	O
</s>
<s>
Transcendentals	O
–	O
trigonometric	O
operations	O
such	O
as	O
sine	O
,	O
cosine	O
and	O
logarithm	O
obviously	O
feature	O
much	O
more	O
predominantly	O
in	O
3D	O
than	O
in	O
many	O
demanding	O
HPC	B-Architecture
workloads	O
.	O
</s>
<s>
Of	O
interest	O
,	O
however	O
,	O
is	O
that	O
speed	O
is	O
far	O
more	O
important	O
than	O
accuracy	O
in	O
3D	O
for	O
GPUs	B-Architecture
,	O
where	O
computation	O
of	O
pixel	O
coordinates	O
simply	O
do	O
not	O
require	O
high	O
precision	O
.	O
</s>
<s>
The	O
Vulkan	B-Application
specification	O
recognises	O
this	O
and	O
sets	O
surprisingly	O
low	O
accuracy	O
requirements	O
,	O
so	O
that	O
GPU	B-Architecture
Hardware	O
can	O
reduce	O
power	O
usage	O
.	O
</s>
<s>
The	O
concept	O
of	O
reducing	O
accuracy	O
where	O
it	O
is	O
simply	O
not	O
needed	O
is	O
explored	O
in	O
the	O
MIPS-3D	B-General_Concept
extension	O
.	O
</s>
<s>
Introduced	O
in	O
ARM	O
SVE2	O
and	O
RISC-V	B-Device
RVV	O
is	O
the	O
concept	O
of	O
speculative	O
sequential	O
Vector	O
Loads	O
.	O
</s>
<s>
Contrast	O
this	O
situation	O
with	O
SIMD	B-Device
,	O
which	O
is	O
a	O
fixed	O
(	O
inflexible	O
)	O
load	O
width	O
and	O
fixed	O
data	O
processing	O
width	O
,	O
unable	O
to	O
cope	O
with	O
loads	O
that	O
cross	O
page	O
boundaries	O
,	O
and	O
even	O
if	O
they	O
were	O
they	O
are	O
unable	O
to	O
adapt	O
to	O
what	O
actually	O
succeeded	O
,	O
yet	O
,	O
paradoxically	O
,	O
if	O
the	O
SIMD	B-Device
program	O
were	O
to	O
even	O
attempt	O
to	O
find	O
out	O
in	O
advance	O
(	O
in	O
each	O
inner	O
loop	O
,	O
every	O
time	O
)	O
what	O
might	O
optimally	O
succeed	O
,	O
those	O
instructions	O
only	O
serve	O
to	O
hinder	O
performance	O
because	O
they	O
would	O
,	O
by	O
necessity	O
,	O
be	O
part	O
of	O
the	O
critical	O
inner	O
loop	O
.	O
</s>
<s>
This	O
begins	O
to	O
hint	O
at	O
the	O
reason	O
why	O
is	O
so	O
innovative	O
,	O
and	O
is	O
best	O
illustrated	O
by	O
memcpy	O
or	O
strcpy	O
when	O
implemented	O
with	O
standard	O
128-bit	O
non-predicated	O
SIMD	B-Device
.	O
</s>
<s>
The	O
above	O
SIMD	B-Device
example	O
could	O
potentially	O
fault	O
and	O
fail	O
at	O
the	O
end	O
of	O
memory	O
,	O
due	O
to	O
attempts	O
to	O
read	O
too	O
many	O
values	O
:	O
it	O
could	O
also	O
cause	O
significant	O
numbers	O
of	O
page	O
or	O
misaligned	O
faults	O
by	O
similarly	O
crossing	O
over	O
boundaries	O
.	O
</s>
