<s>
The	O
VIA	B-Device
Nano	I-Device
(	O
formerly	O
code-named	O
VIA	B-Device
Isaiah	I-Device
)	O
is	O
a	O
64-bit	B-Device
CPU	I-Device
for	O
personal	B-Device
computers	I-Device
.	O
</s>
<s>
The	O
VIA	B-Device
Nano	I-Device
was	O
released	O
by	O
VIA	O
Technologies	O
in	O
2008	O
after	O
five	O
years	O
of	O
development	O
by	O
its	O
CPU	B-Device
division	O
,	O
Centaur	O
Technology	O
.	O
</s>
<s>
This	O
new	O
Isaiah	O
64-bit	B-Device
architecture	I-Device
was	O
designed	O
from	O
scratch	O
,	O
unveiled	O
on	O
24	O
January	O
2008	O
,	O
and	O
launched	O
on	O
29	O
May	O
,	O
including	O
low-voltage	O
variants	O
and	O
the	O
Nano	O
brand	O
name	O
.	O
</s>
<s>
The	O
processor	O
supports	O
a	O
number	O
of	O
VIA-specific	O
x86	B-Operating_System
extensions	O
designed	O
to	O
boost	O
efficiency	O
in	O
low-power	O
appliances	O
.	O
</s>
<s>
Unlike	O
Intel	O
and	O
AMD	O
,	O
VIA	O
uses	O
two	O
distinct	O
development	O
code	O
names	O
for	O
each	O
of	O
its	O
CPU	B-Device
cores	O
.	O
</s>
<s>
It	O
is	O
expected	O
that	O
the	O
VIA	B-Device
Isaiah	I-Device
will	O
be	O
twice	O
as	O
fast	O
in	O
integer	O
performance	O
and	O
four	O
times	O
as	O
fast	O
in	O
floating-point	B-Algorithm
performance	O
as	O
the	O
previous	O
generation	O
VIA	B-Device
Esther	I-Device
at	O
an	O
equivalent	O
clock	O
speed	O
.	O
</s>
<s>
Power	O
consumption	O
is	O
also	O
expected	O
to	O
be	O
on	O
par	O
with	O
the	O
previous-generation	O
VIA	O
CPUs	B-Device
,	O
with	O
thermal	B-General_Concept
design	I-General_Concept
power	I-General_Concept
ranging	O
from	O
5W	O
to	O
25W	O
.	O
</s>
<s>
Being	O
a	O
completely	O
new	O
design	O
,	O
the	O
Isaiah	O
architecture	O
was	O
built	O
with	O
support	O
for	O
features	O
like	O
the	O
x86-64	B-Device
instruction	O
set	O
and	O
x86	B-General_Concept
virtualization	I-General_Concept
which	O
were	O
unavailable	O
on	O
its	O
predecessors	O
,	O
the	O
VIA	B-Device
C7	I-Device
line	O
,	O
while	O
retaining	O
their	O
encryption	O
extensions	O
.	O
</s>
<s>
Several	O
independent	O
tests	O
showed	O
that	O
the	O
VIA	B-Device
Nano	I-Device
performs	O
better	O
than	O
the	O
single-core	O
Intel	B-Device
Atom	I-Device
across	O
a	O
variety	O
of	O
workloads	O
.	O
</s>
<s>
In	O
a	O
2008	O
Ars	O
Technica	O
test	O
,	O
a	O
VIA	B-Device
Nano	I-Device
gained	O
significant	O
performance	O
in	O
memory	O
subsystem	O
after	O
its	O
CPUID	O
changed	O
to	O
Intel	O
,	O
hinting	O
at	O
the	O
possibility	O
that	O
the	O
benchmark	O
software	O
only	O
checks	O
the	O
CPUID	O
instead	O
of	O
the	O
actual	O
features	O
supported	O
by	O
the	O
CPU	B-Device
to	O
choose	O
a	O
code	O
path	O
.	O
</s>
<s>
The	O
benchmark	O
software	O
used	O
had	O
been	O
released	O
before	O
the	O
release	O
of	O
VIA	B-Device
Nano	I-Device
.	O
</s>
<s>
Benchmarks	O
run	O
by	O
VIA	O
claim	O
that	O
a	O
1.6GHz	O
3000-series	O
Nano	O
can	O
outperform	O
the	O
ageing	O
Intel	B-Device
Atom	I-Device
N270	O
by	O
about	O
40	O
–	O
54%	O
.	O
</s>
<s>
The	O
3000	O
series	O
adds	O
the	O
SSE4	B-General_Concept
SIMD	B-Device
instruction	O
set	O
extensions	O
,	O
which	O
were	O
first	O
introduced	O
with	O
45nm	O
revisions	O
of	O
the	O
Intel	B-Device
Core	I-Device
2	I-Device
architecture	O
.	O
</s>
<s>
On	O
November	O
11	O
,	O
2011	O
,	O
VIA	O
released	O
the	O
VIA	B-Device
Nano	I-Device
X2	O
Dual-Core	O
Processor	O
with	O
their	O
first-ever	O
dual-core	O
pico-itx	O
mainboard	O
.	O
</s>
<s>
The	O
VIA	B-Device
Nano	I-Device
X2	O
is	O
built	O
on	O
a	O
40nm	O
process	O
and	O
supports	O
the	O
SSE4	B-General_Concept
SIMD	B-Device
instruction	O
set	O
extensions	O
,	O
critical	O
to	O
modern	O
floating	B-Algorithm
point	I-Algorithm
dependent	O
applications	O
.	O
</s>
<s>
Via	O
claims	O
30%	O
higher	O
performance	O
in	O
comparison	O
to	O
Intel	O
's	O
Atom	B-Device
with	O
a	O
50%	O
higher	O
clock	O
.	O
</s>
<s>
The	O
Zhaoxin	B-Device
joint	O
venture	O
processors	O
,	O
released	O
in	O
2014	O
,	O
are	O
based	O
on	O
the	O
VIA	B-Device
Nano	I-Device
series	O
.	O
</s>
<s>
Out-of-order	B-General_Concept
and	O
superscalar	B-General_Concept
design	O
:	O
Providing	O
much	O
better	O
performance	O
than	O
its	O
predecessor	O
,	O
the	O
VIA	B-Device
C7	I-Device
processor	O
,	O
which	O
was	O
in-order	O
.	O
</s>
<s>
Instructions	O
fusion	O
:	O
Allows	O
the	O
processor	O
to	O
combine	O
some	O
instructions	O
as	O
a	O
single	O
instruction	O
,	O
reducing	O
power	O
requirements	O
and	O
giving	O
higher	O
performance	O
(	O
the	O
Atom	B-Device
uses	O
a	O
similar	O
strategy	O
in	O
processing	O
x86	B-Device
instructions	I-Device
in	O
a	O
more	O
'	O
whole	O
 '	O
manner	O
,	O
rather	O
than	O
breaking	O
them	O
into	O
RISC-like	O
micro-ops	B-General_Concept
)	O
.	O
</s>
<s>
Improved	O
branch	B-General_Concept
prediction	I-General_Concept
:	O
Uses	O
eight	O
predictors	O
in	O
two	O
pipeline	O
stages	O
.	O
</s>
<s>
CPU	B-General_Concept
cache	I-General_Concept
design	O
:	O
An	O
exclusive	O
cache	O
design	O
means	O
that	O
contents	O
of	O
the	O
L1	O
cache	O
is	O
not	O
duplicated	O
in	O
the	O
L2	O
cache	O
,	O
providing	O
a	O
larger	O
total	O
cache	O
.	O
</s>
<s>
Fetches	O
four	O
x86	B-Device
instructions	I-Device
per	O
cycle	B-General_Concept
as	O
opposed	O
to	O
Intel	O
's	O
three	O
to	O
five	O
cycles	O
.	O
</s>
<s>
Execution	B-General_Concept
units	I-General_Concept
:	O
Seven	O
execution	B-General_Concept
units	I-General_Concept
are	O
available	O
,	O
which	O
allows	O
up	O
to	O
seven	O
micro-ops	B-General_Concept
to	O
be	O
executed	O
per	O
clock	O
.	O
</s>
<s>
Two	O
media	O
units	O
(	O
MEDIA-A	O
and	O
MEDIA-B	O
)	O
with	O
a	O
128-bit	O
wide	O
datapath	B-General_Concept
,	O
supporting	O
4	O
single	O
precision	O
or	O
2	O
double-precision	O
operations	O
.	O
</s>
<s>
MEDIA-A	O
executes	O
floating-point	B-Algorithm
"	O
add	O
"	O
instructions	O
(	O
2-clock	O
latency	O
for	O
single-precision	O
and	O
double-precision	O
)	O
,	O
integer	O
SIMD	B-Device
,	O
encryption	O
,	O
divide	O
,	O
and	O
square	O
root	O
.	O
</s>
<s>
MEDIA-B	O
executes	O
floating-point	B-Algorithm
"	O
multiply	O
"	O
instructions	O
(	O
2-clock	O
latency	O
for	O
single-precision	O
,	O
3-clock	O
latency	O
for	O
double-precision	O
)	O
.	O
</s>
<s>
A	O
new	O
implementation	O
of	O
FP-addition	O
with	O
the	O
lowest	O
clock	O
latency	O
for	O
an	O
x86	B-Operating_System
processor	O
so	O
far	O
.	O
</s>
<s>
Almost	O
all	O
integer	O
SIMD	B-Device
instructions	O
execute	O
in	O
one	O
clock	O
.	O
</s>
