<s>
The	O
VIA	B-Device
C3	I-Device
is	O
a	O
family	O
of	O
x86	B-Operating_System
central	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
for	O
personal	B-Device
computers	I-Device
designed	O
by	O
Centaur	O
Technology	O
and	O
sold	O
by	O
VIA	O
Technologies	O
.	O
</s>
<s>
In	O
addition	O
to	O
x86	B-Operating_System
instructions	O
,	O
VIA	B-Device
C3	I-Device
CPUs	O
contain	O
an	O
undocumented	O
Alternate	B-Device
Instruction	I-Device
Set	I-Device
allowing	O
lower-level	O
access	O
to	O
the	O
CPU	O
and	O
in	O
some	O
cases	O
privilege	O
escalation	O
.	O
</s>
<s>
VIA	B-Device
Cyrix	I-Device
III	I-Device
was	O
renamed	O
VIA	B-Device
C3	I-Device
with	O
the	O
switch	O
to	O
the	O
advanced	O
"	O
Samuel	O
2	O
"	O
(	O
C5B	O
)	O
core	O
.	O
</s>
<s>
The	O
addition	O
of	O
an	O
on-die	O
L2	B-General_Concept
cache	I-General_Concept
improved	O
performance	O
somewhat	O
.	O
</s>
<s>
The	O
VIA	B-Device
C3	I-Device
processor	O
continued	O
an	O
emphasis	O
on	O
minimizing	O
power	O
consumption	O
with	O
the	O
next	O
die	O
shrink	O
to	O
a	O
mixed	O
130/150nm	O
process	O
.	O
</s>
<s>
VIA	O
enjoyed	O
the	O
lowest	O
power	O
usage	O
in	O
the	O
x86	B-Operating_System
CPU	O
market	O
for	O
several	O
years	O
.	O
</s>
<s>
The	O
company	O
addressed	O
numerous	O
design	O
shortcomings	O
of	O
the	O
older	O
cores	O
,	O
including	O
the	O
half-speed	O
FPU	B-General_Concept
.	O
</s>
<s>
It	O
also	O
removes	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
instructions	O
in	O
favour	O
of	O
implementing	O
SSE	B-General_Concept
.	O
</s>
<s>
However	O
,	O
it	O
was	O
still	O
based	O
upon	O
the	O
aging	O
Socket	B-Device
370	I-Device
,	O
running	O
the	O
single	B-General_Concept
data	I-General_Concept
rate	I-General_Concept
front-side	B-Architecture
bus	I-Architecture
at	O
just	O
133MHz	O
.	O
</s>
<s>
The	O
"	O
Nehemiah+	O
"	O
(	O
C5P	O
)	O
(	O
stepping	O
8	O
)	O
revision	O
brought	O
a	O
few	O
more	O
advancements	O
,	O
including	O
a	O
high-performance	O
AES	B-Algorithm
encryption	I-Algorithm
engine	O
along	O
with	O
a	O
notably	O
small	O
ball	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
chip	O
package	O
the	O
size	O
of	O
a	O
US	O
1	O
cent	O
coin	O
.	O
</s>
<s>
The	O
new	O
200	O
MHz	O
FSB	O
chips	O
are	O
only	O
available	O
in	O
BGA	O
packages	O
,	O
as	O
they	O
are	O
not	O
compatible	O
with	O
existing	O
Socket	B-Device
370	I-Device
motherboards	O
.	O
</s>
<s>
While	O
slower	O
than	O
x86	B-Operating_System
CPUs	O
being	O
sold	O
by	O
AMD	O
and	O
Intel	O
,	O
both	O
in	O
absolute	O
terms	O
and	O
on	O
a	O
clock-for-clock	O
basis	O
,	O
VIA	O
's	O
chips	O
were	O
much	O
smaller	O
,	O
cheaper	O
to	O
manufacture	O
,	O
and	O
lower	O
power	O
.	O
</s>
<s>
This	O
also	O
enabled	O
VIA	O
to	O
continue	O
to	O
scale	O
the	O
frequencies	O
of	O
their	O
chips	O
with	O
each	O
manufacturing	O
process	O
die	O
shrink	O
,	O
while	O
competitive	O
products	O
from	O
Intel	O
(	O
such	O
as	O
the	O
P4	O
Prescott	O
)	O
encountered	O
severe	O
thermal	O
management	O
issues	O
,	O
although	O
the	O
later	O
Intel	B-Device
Core	I-Device
generation	O
of	O
chips	O
were	O
substantially	O
cooler	O
.	O
</s>
<s>
Because	O
memory	O
performance	O
is	O
the	O
limiting	O
factor	O
in	O
many	O
benchmarks	O
,	O
VIA	O
processors	O
implement	O
large	O
primary	O
caches	O
,	O
large	O
TLBs	B-Architecture
,	O
and	O
aggressive	O
prefetching	B-General_Concept
,	O
among	O
other	O
enhancements	O
.	O
</s>
<s>
Complex	O
features	O
such	O
as	O
out-of-order	B-General_Concept
instruction	I-General_Concept
execution	I-General_Concept
are	O
deliberately	O
not	O
implemented	O
,	O
because	O
they	O
impact	O
the	O
ability	O
to	O
increase	O
the	O
clock	O
rate	O
,	O
require	O
a	O
lot	O
of	O
extra	O
die	O
space	O
and	O
power	O
,	O
and	O
have	O
little	O
impact	O
on	O
performance	O
in	O
several	O
common	O
application	O
scenarios	O
.	O
</s>
<s>
The	O
pipeline	O
is	O
arranged	O
to	O
provide	O
one-clock	O
execution	O
of	O
the	O
heavily	O
used	O
register	O
–	O
memory	O
and	O
memory	O
–	O
register	O
forms	O
of	O
x86	B-Operating_System
instructions	O
.	O
</s>
<s>
Several	O
frequently	O
used	O
instructions	O
require	O
fewer	O
pipeline	O
clocks	O
than	O
on	O
other	O
x86	B-Operating_System
processors	O
.	O
</s>
<s>
Infrequently	O
used	O
x86	B-Operating_System
instructions	O
are	O
implemented	O
in	O
microcode	B-Device
and	O
emulated	O
.	O
</s>
<s>
These	O
design	O
guidelines	O
are	O
derivative	O
from	O
the	O
original	O
RISC	B-Architecture
advocates	O
,	O
who	O
stated	O
a	O
smaller	O
set	O
of	O
instructions	O
,	O
better	O
optimized	O
,	O
would	O
deliver	O
faster	O
overall	O
CPU	O
performance	O
.	O
</s>
<s>
As	O
it	O
makes	O
heavy	O
use	O
of	O
memory	O
operands	O
,	O
both	O
as	O
source	O
and	O
destination	O
,	O
the	O
C3	O
design	O
itself	O
cannot	O
qualify	O
as	O
RISC	B-Architecture
however	O
.	O
</s>
<s>
On	O
the	O
basis	O
of	O
the	O
negotiating	O
leverage	O
these	O
patents	O
offered	O
,	O
in	O
2003	O
VIA	O
arrived	O
at	O
an	O
agreement	O
with	O
Intel	O
that	O
allowed	O
for	O
a	O
ten-year	O
patent	O
cross	O
license	O
,	O
enabling	O
VIA	O
to	O
continue	O
to	O
design	O
and	O
manufacture	O
x86	B-Operating_System
compatible	I-Operating_System
CPUs	O
.	O
</s>
