<s>
The	O
VHSIC	B-Language
Hardware	I-Language
Description	I-Language
Language	I-Language
(	O
VHDL	B-Language
)	O
is	O
a	O
hardware	O
description	O
language	O
(	O
HDL	O
)	O
that	O
can	O
model	O
the	O
behavior	O
and	O
structure	O
of	O
digital	O
systems	O
at	O
multiple	O
levels	O
of	O
abstraction	O
,	O
ranging	O
from	O
the	O
system	O
level	O
down	O
to	O
that	O
of	O
logic	O
gates	O
,	O
for	O
design	O
entry	O
,	O
documentation	O
,	O
and	O
verification	O
purposes	O
.	O
</s>
<s>
Since	O
1987	O
,	O
VHDL	B-Language
has	O
been	O
standardized	O
by	O
the	O
Institute	O
of	O
Electrical	O
and	O
Electronics	O
Engineers	O
(	O
IEEE	O
)	O
as	O
IEEE	O
Std	O
1076	O
;	O
the	O
latest	O
version	O
of	O
which	O
is	O
IEEE	O
Std	O
1076-2019	O
.	O
</s>
<s>
To	O
model	O
analog	O
and	O
mixed-signal	O
systems	O
,	O
an	O
IEEE-standardized	O
HDL	O
based	O
on	O
VHDL	B-Language
called	O
VHDL-AMS	B-Language
(	O
officially	O
IEEE1076.1	O
)	O
has	O
been	O
developed	O
.	O
</s>
<s>
VHDL	B-Language
is	O
named	O
after	O
the	O
United	O
States	O
Department	O
of	O
Defense	O
program	O
that	O
created	O
it	O
,	O
the	O
Very	O
High	O
Speed	O
Integrated	O
Circuits	O
Program	O
(	O
VHSIC	O
)	O
.	O
</s>
<s>
The	O
product	O
of	O
this	O
effort	O
was	O
VHDL	B-Language
Version	O
7.2	O
,	O
released	O
in	O
1985	O
.	O
</s>
<s>
VHDL	B-Language
,	O
developed	O
in	O
1983	O
at	O
the	O
request	O
of	O
the	O
U.S.	O
Department	O
of	O
Defense	O
,	O
is	O
used	O
to	O
document	O
and	O
simulate	O
the	O
behavior	O
of	O
ASICs	O
in	O
electronic	O
equipment	O
.	O
</s>
<s>
VHDL	B-Language
borrows	O
heavily	O
from	O
the	O
Ada	B-Language
programming	I-Language
language	I-Language
in	O
terms	O
of	O
syntax	B-Application
and	O
concepts	O
.	O
</s>
<s>
The	O
initial	O
version	O
of	O
VHDL	B-Language
(	O
IEEE	O
1076-1987	O
)	O
included	O
a	O
wide	O
range	O
of	O
data	O
types	O
.	O
</s>
<s>
In	O
2008	O
,	O
VHDL	B-Language
4.0	O
(	O
informally	O
known	O
as	O
VHDL	B-Language
2008	O
)	O
was	O
approved	O
,	O
addressing	O
issues	O
from	O
the	O
trial	O
period	O
of	O
version	O
3.0	O
and	O
enhancing	O
generic	O
types	O
.	O
</s>
<s>
VHDL	B-Language
is	O
commonly	O
used	O
to	O
write	O
text	O
models	O
that	O
describe	O
logic	O
circuits	O
,	O
which	O
are	O
then	O
processed	O
by	O
synthesis	O
programs	O
and	O
tested	O
using	O
simulation	O
models	O
in	O
a	O
testbench	O
.	O
</s>
<s>
The	O
language	O
has	O
constructs	O
to	O
handle	O
parallelism	B-Operating_System
inherent	O
in	O
hardware	O
designs	O
and	O
includes	O
features	O
specific	O
to	O
hardware	O
operations	O
.	O
</s>
<s>
Although	O
VHDL	B-Language
can	O
be	O
used	O
for	O
text	O
processing	O
,	O
it	O
is	O
more	O
commonly	O
utilized	O
in	O
simulation	O
testbenches	O
for	O
stimulus	O
or	O
verification	O
data	O
.	O
</s>
<s>
VHDL	B-Language
is	O
used	O
for	O
system	O
design	O
,	O
modeling	O
,	O
and	O
verification	O
before	O
synthesis	O
into	O
hardware	O
.	O
</s>
<s>
It	O
allows	O
concurrent	B-Operating_System
system	I-Operating_System
descriptions	O
and	O
is	O
considered	O
a	O
dataflow	B-Application
language	I-Application
with	O
simultaneous	O
statement	O
execution	O
.	O
</s>
<s>
VHDL	B-Language
projects	O
are	O
multipurpose	O
,	O
portable	O
,	O
and	O
have	O
a	O
full	O
type	O
system	O
.	O
</s>
<s>
VHDL	B-Language
is	O
used	O
for	O
simulation	O
and	O
synthesis	O
of	O
electronic	O
designs	O
,	O
with	O
a	O
common	O
synthesizable	O
subset	O
.	O
</s>
<s>
In	O
1983	O
,	O
VHDL	B-Language
was	O
originally	O
developed	O
at	O
the	O
behest	O
of	O
the	O
U.S.	O
Department	O
of	O
Defense	O
in	O
order	O
to	O
document	O
the	O
behavior	O
of	O
the	O
ASICs	O
that	O
supplier	O
companies	O
were	O
including	O
in	O
equipment	O
.	O
</s>
<s>
The	O
standard	O
MIL-STD-454N	O
in	O
Requirement	O
64	O
in	O
section	O
4.5.1	O
"	O
ASIC	O
documentation	O
in	O
VHDL	B-Language
"	O
explicitly	O
requires	O
documentation	O
of	O
"	O
Microelectronic	O
Devices	O
"	O
in	O
VHDL	B-Language
.	O
</s>
<s>
The	O
idea	O
of	O
being	O
able	O
to	O
simulate	O
the	O
ASICs	O
from	O
the	O
information	O
in	O
this	O
documentation	O
was	O
so	O
obviously	O
attractive	O
that	O
logic	O
simulators	O
were	O
developed	O
that	O
could	O
read	O
the	O
VHDL	B-Language
files	O
.	O
</s>
<s>
The	O
next	O
step	O
was	O
the	O
development	O
of	O
logic	O
synthesis	O
tools	O
that	O
read	O
the	O
VHDL	B-Language
and	O
output	O
a	O
definition	O
of	O
the	O
physical	O
implementation	O
of	O
the	O
circuit	O
.	O
</s>
<s>
Due	O
to	O
the	O
Department	O
of	O
Defense	O
requiring	O
as	O
much	O
of	O
the	O
syntax	B-Application
as	O
possible	O
to	O
be	O
based	O
on	O
Ada	B-Language
,	O
in	O
order	O
to	O
avoid	O
re-inventing	O
concepts	O
that	O
had	O
already	O
been	O
thoroughly	O
tested	O
in	O
the	O
development	O
of	O
Ada	B-Language
,	O
VHDL	B-Language
borrows	O
heavily	O
from	O
the	O
Ada	B-Language
programming	I-Language
language	I-Language
in	O
both	O
concept	O
and	O
syntax	B-Application
.	O
</s>
<s>
The	O
initial	O
version	O
of	O
VHDL	B-Language
,	O
designed	O
to	O
IEEE	O
standard	O
IEEE	O
1076-1987	O
,	O
included	O
a	O
wide	O
range	O
of	O
data	O
types	O
,	O
including	O
numerical	O
(	O
integer	O
and	O
real	O
)	O
,	O
logical	O
(	O
bit	O
and	O
boolean	O
)	O
,	O
character	O
and	O
time	O
,	O
plus	O
arrays	O
of	O
bit	O
called	O
bit_vector	O
and	O
of	O
character	O
called	O
string	O
.	O
</s>
<s>
The	O
updated	O
IEEE	B-Language
1076	I-Language
,	O
in	O
1993	O
,	O
made	O
the	O
syntax	B-Application
more	O
consistent	O
,	O
allowed	O
more	O
flexibility	O
in	O
naming	O
,	O
extended	O
the	O
character	O
type	O
to	O
allow	O
ISO-8859-1	O
printable	O
characters	O
,	O
added	O
the	O
xnor	O
operator	O
,	O
etc	O
.	O
</s>
<s>
Minor	O
changes	O
in	O
the	O
standard	O
(	O
2000	O
and	O
2002	O
)	O
added	O
the	O
idea	O
of	O
protected	O
types	O
(	O
similar	O
to	O
the	O
concept	O
of	O
class	O
in	O
C++	B-Language
)	O
and	O
removed	O
some	O
restrictions	O
from	O
port	O
mapping	O
rules	O
.	O
</s>
<s>
IEEE	O
standard	O
1076.3	O
introduced	O
signed	B-Algorithm
and	I-Algorithm
unsigned	I-Algorithm
types	O
to	O
facilitate	O
arithmetical	O
operations	O
on	O
vectors	O
.	O
</s>
<s>
IEEE	O
standard	O
1076.1	O
(	O
known	O
as	O
VHDL-AMS	B-Language
)	O
provided	O
analog	O
and	O
mixed-signal	O
circuit	O
design	O
extensions	O
.	O
</s>
<s>
Some	O
other	O
standards	O
support	O
wider	O
use	O
of	O
VHDL	B-Language
,	O
notably	O
VITAL	B-Language
(	O
VHDL	B-Language
Initiative	O
Towards	O
ASIC	O
Libraries	O
)	O
and	O
microwave	O
circuit	O
design	O
extensions	O
.	O
</s>
<s>
In	O
June	O
2006	O
,	O
the	O
VHDL	B-Language
Technical	O
Committee	O
of	O
Accellera	O
(	O
delegated	O
by	O
IEEE	O
to	O
work	O
on	O
the	O
next	O
update	O
of	O
the	O
standard	O
)	O
approved	O
so-called	O
Draft	O
3.0	O
of	O
VHDL-2006	O
.	O
</s>
<s>
While	O
maintaining	O
full	O
compatibility	O
with	O
older	O
versions	O
,	O
this	O
proposed	O
standard	O
provides	O
numerous	O
extensions	O
that	O
make	O
writing	O
and	O
managing	O
VHDL	B-Language
code	O
easier	O
.	O
</s>
<s>
Key	O
changes	O
include	O
incorporation	O
of	O
child	O
standards	O
(	O
1164	O
,	O
1076.2	O
,	O
1076.3	O
)	O
into	O
the	O
main	O
1076	O
standard	O
,	O
an	O
extended	O
set	O
of	O
operators	O
,	O
more	O
flexible	O
syntax	B-Application
of	O
case	O
and	O
generate	O
statements	O
,	O
incorporation	O
of	O
VHPI	O
(	O
VHDL	B-Language
Procedural	O
Interface	O
)	O
(	O
interface	O
to	O
C/C	O
++	O
languages	O
)	O
and	O
a	O
subset	O
of	O
PSL	O
(	O
Property	B-Language
Specification	I-Language
Language	I-Language
)	O
.	O
</s>
<s>
These	O
changes	O
should	O
improve	O
quality	O
of	O
synthesizable	O
VHDL	B-Language
code	O
,	O
make	O
testbenches	O
more	O
flexible	O
,	O
and	O
allow	O
wider	O
use	O
of	O
VHDL	B-Language
for	O
system-level	O
descriptions	O
.	O
</s>
<s>
In	O
February	O
2008	O
,	O
Accellera	O
approved	O
VHDL	B-Language
4.0	O
,	O
also	O
informally	O
known	O
as	O
VHDL	B-Language
2008	O
,	O
which	O
addressed	O
more	O
than	O
90	O
issues	O
discovered	O
during	O
the	O
trial	O
period	O
for	O
version	O
3.0	O
and	O
includes	O
enhanced	O
generic	O
types	O
.	O
</s>
<s>
In	O
2008	O
,	O
Accellera	O
released	O
VHDL	B-Language
4.0	O
to	O
the	O
IEEE	O
for	O
balloting	O
for	O
inclusion	O
in	O
IEEE	O
1076-2008	O
.	O
</s>
<s>
The	O
VHDL	B-Language
standard	O
IEEE	O
1076-2008	O
was	O
published	O
in	O
January	O
2009	O
.	O
</s>
<s>
The	O
IEEE	O
Standard	O
1076	O
defines	O
the	O
VHSIC	B-Language
Hardware	I-Language
Description	I-Language
Language	I-Language
,	O
or	O
VHDL	B-Language
.	O
</s>
<s>
Introduced	O
VHPI	O
,	O
the	O
VHDL	B-Language
procedural	O
interface	O
,	O
which	O
provides	O
software	O
with	O
the	O
means	O
to	O
access	O
the	O
VHDL	B-Language
model	O
.	O
</s>
<s>
The	O
VHDL	B-Language
language	O
required	O
minor	O
modifications	O
to	O
accommodate	O
the	O
VHPI	O
.	O
</s>
<s>
VHDL	B-Language
is	O
generally	O
used	O
to	O
write	O
text	O
models	O
that	O
describe	O
a	O
logic	O
circuit	O
.	O
</s>
<s>
A	O
VHDL	B-Language
simulator	O
is	O
typically	O
an	O
event-driven	O
simulator	O
.	O
</s>
<s>
Zero	O
delay	O
is	O
also	O
allowed	O
,	O
but	O
still	O
needs	O
to	O
be	O
scheduled	O
:	O
for	O
these	O
cases	O
delta	B-Application
delay	I-Application
is	O
used	O
,	O
which	O
represent	O
an	O
infinitely	O
small	O
time	O
step	O
.	O
</s>
<s>
VHDL	B-Language
has	O
constructs	O
to	O
handle	O
the	O
parallelism	B-Operating_System
inherent	O
in	O
hardware	O
designs	O
,	O
but	O
these	O
constructs	O
(	O
processes	O
)	O
differ	O
in	O
syntax	B-Application
from	O
the	O
parallel	O
constructs	O
in	O
Ada	B-Language
(	O
tasks	O
)	O
.	O
</s>
<s>
Like	O
Ada	B-Language
,	O
VHDL	B-Language
is	O
strongly	O
typed	O
and	O
is	O
not	O
case	O
sensitive	O
.	O
</s>
<s>
In	O
order	O
to	O
directly	O
represent	O
operations	O
which	O
are	O
common	O
in	O
hardware	O
,	O
there	O
are	O
many	O
features	O
of	O
VHDL	B-Language
which	O
are	O
not	O
found	O
in	O
Ada	B-Language
,	O
such	O
as	O
an	O
extended	O
set	O
of	O
Boolean	O
operators	O
including	O
nand	O
and	O
nor	O
.	O
</s>
<s>
VHDL	B-Language
has	O
file	O
input	O
and	O
output	O
capabilities	O
,	O
and	O
can	O
be	O
used	O
as	O
a	O
general-purpose	O
language	O
for	O
text	O
processing	O
,	O
but	O
files	O
are	O
more	O
commonly	O
used	O
by	O
a	O
simulation	O
testbench	O
for	O
stimulus	O
or	O
verification	O
data	O
.	O
</s>
<s>
There	O
are	O
some	O
VHDL	B-Language
compilers	O
which	O
build	O
executable	O
binaries	O
.	O
</s>
<s>
In	O
this	O
case	O
,	O
it	O
might	O
be	O
possible	O
to	O
use	O
VHDL	B-Language
to	O
write	O
a	O
testbench	O
to	O
verify	O
the	O
functionality	O
of	O
the	O
design	O
using	O
files	O
on	O
the	O
host	O
computer	O
to	O
define	O
stimuli	O
,	O
to	O
interact	O
with	O
the	O
user	O
,	O
and	O
to	O
compare	O
results	O
with	O
those	O
expected	O
.	O
</s>
<s>
One	O
particular	O
pitfall	O
is	O
the	O
accidental	O
production	O
of	O
transparent	O
latches	B-General_Concept
rather	O
than	O
D-type	O
flip-flops	B-General_Concept
as	O
storage	O
elements	O
.	O
</s>
<s>
One	O
can	O
design	O
hardware	O
in	O
a	O
VHDL	B-Language
IDE	O
(	O
for	O
FPGA	B-Architecture
implementation	O
such	O
as	O
Xilinx	O
ISE	O
,	O
Altera	O
Quartus	O
,	O
Synopsys	O
Synplify	O
or	O
Mentor	O
Graphics	O
HDL	O
Designer	O
)	O
to	O
produce	O
the	O
RTL	O
schematic	O
of	O
the	O
desired	O
circuit	O
.	O
</s>
<s>
To	O
generate	O
an	O
appropriate	O
testbench	O
for	O
a	O
particular	O
circuit	O
or	O
VHDL	B-Language
code	O
,	O
the	O
inputs	O
have	O
to	O
be	O
defined	O
correctly	O
.	O
</s>
<s>
A	O
final	O
point	O
is	O
that	O
when	O
a	O
VHDL	B-Language
model	O
is	O
translated	O
into	O
the	O
"	O
gates	O
and	O
wires	O
"	O
that	O
are	O
mapped	O
onto	O
a	O
programmable	O
logic	O
device	O
such	O
as	O
a	O
CPLD	B-General_Concept
or	O
FPGA	B-Architecture
,	O
then	O
it	O
is	O
the	O
actual	O
hardware	O
being	O
configured	O
,	O
rather	O
than	O
the	O
VHDL	B-Language
code	O
being	O
"	O
executed	O
"	O
as	O
if	O
on	O
some	O
form	O
of	O
a	O
processor	O
chip	O
.	O
</s>
<s>
The	O
key	O
advantage	O
of	O
VHDL	B-Language
,	O
when	O
used	O
for	O
systems	O
design	O
,	O
is	O
that	O
it	O
allows	O
the	O
behavior	O
of	O
the	O
required	O
system	O
to	O
be	O
described	O
(	O
modeled	O
)	O
and	O
verified	O
(	O
simulated	O
)	O
before	O
synthesis	O
tools	O
translate	O
the	O
design	O
into	O
real	O
hardware	O
(	O
gates	O
and	O
wires	O
)	O
.	O
</s>
<s>
Another	O
benefit	O
is	O
that	O
VHDL	B-Language
allows	O
the	O
description	O
of	O
a	O
concurrent	B-Operating_System
system	I-Operating_System
.	O
</s>
<s>
VHDL	B-Language
is	O
a	O
dataflow	B-Application
language	I-Application
in	O
which	O
every	O
statement	O
is	O
considered	O
for	O
execution	O
simultaneously	O
,	O
unlike	O
procedural	O
computing	O
languages	O
such	O
as	O
BASIC	O
,	O
C	O
,	O
and	O
assembly	O
code	O
,	O
where	O
a	O
sequence	O
of	O
statements	O
is	O
run	O
sequentially	O
one	O
instruction	O
at	O
a	O
time	O
.	O
</s>
<s>
A	O
VHDL	B-Language
project	O
is	O
multipurpose	O
.	O
</s>
<s>
A	O
VHDL	B-Language
project	O
is	O
portable	O
.	O
</s>
<s>
A	O
big	O
advantage	O
of	O
VHDL	B-Language
compared	O
to	O
original	O
Verilog	B-Language
is	O
that	O
VHDL	B-Language
has	O
a	O
full	O
type	O
system	O
.	O
</s>
<s>
In	O
VHDL	B-Language
,	O
a	O
design	O
consists	O
at	O
a	O
minimum	O
of	O
an	O
entity	O
which	O
describes	O
the	O
interface	O
and	O
an	O
architecture	O
which	O
contains	O
the	O
actual	O
implementation	O
.	O
</s>
<s>
In	O
the	O
examples	O
that	O
follow	O
,	O
you	O
will	O
see	O
that	O
VHDL	B-Language
code	O
can	O
be	O
written	O
in	O
a	O
very	O
compact	O
form	O
.	O
</s>
<s>
VHDL	B-Language
is	O
frequently	O
used	O
for	O
two	O
different	O
goals	O
:	O
simulation	O
of	O
electronic	O
designs	O
and	O
synthesis	O
of	O
such	O
designs	O
.	O
</s>
<s>
Synthesis	O
is	O
a	O
process	O
where	O
a	O
VHDL	B-Language
is	O
compiled	O
and	O
mapped	O
into	O
an	O
implementation	O
technology	O
such	O
as	O
an	O
FPGA	B-Architecture
or	O
an	O
ASIC	O
.	O
</s>
<s>
Not	O
all	O
constructs	O
in	O
VHDL	B-Language
are	O
suitable	O
for	O
synthesis	O
.	O
</s>
<s>
While	O
different	O
synthesis	O
tools	O
have	O
different	O
capabilities	O
,	O
there	O
exists	O
a	O
common	O
synthesizable	O
subset	O
of	O
VHDL	B-Language
that	O
defines	O
what	O
language	O
constructs	O
and	O
idioms	O
map	O
into	O
common	O
hardware	O
for	O
many	O
synthesis	O
tools	O
.	O
</s>
<s>
The	O
multiplexer	B-Protocol
,	O
or	O
'	O
MUX	O
 '	O
as	O
it	O
is	O
usually	O
called	O
,	O
is	O
a	O
simple	O
construct	O
very	O
common	O
in	O
hardware	O
design	O
.	O
</s>
<s>
Note	O
that	O
there	O
are	O
many	O
other	O
ways	O
to	O
express	O
the	O
same	O
MUX	O
in	O
VHDL	B-Language
.	O
</s>
<s>
A	O
transparent	O
latch	B-General_Concept
is	O
basically	O
one	O
bit	O
of	O
memory	O
which	O
is	O
updated	O
when	O
an	O
enable	O
signal	O
is	O
raised	O
.	O
</s>
<s>
Again	O
,	O
there	O
are	O
many	O
other	O
ways	O
this	O
can	O
be	O
expressed	O
in	O
VHDL	B-Language
.	O
</s>
<s>
The	O
D-type	O
flip-flop	B-General_Concept
samples	O
an	O
incoming	O
signal	O
at	O
the	O
rising	O
(	O
or	O
falling	O
)	O
edge	O
of	O
a	O
clock	O
.	O
</s>
<s>
Another	O
common	O
way	O
to	O
write	O
edge-triggered	O
behavior	O
in	O
VHDL	B-Language
is	O
with	O
the	O
'	O
event	O
 '	O
signal	O
attribute	O
.	O
</s>
<s>
It	O
demonstrates	O
the	O
use	O
of	O
the	O
'	O
unsigned	B-Algorithm
 '	O
type	O
,	O
type	O
conversions	O
between	O
'	O
unsigned	B-Algorithm
 '	O
and	O
'	O
std_logic_vector	O
 '	O
and	O
VHDL	B-Language
generics	O
.	O
</s>
<s>
The	O
generics	O
are	O
very	O
close	O
to	O
arguments	O
or	O
templates	O
in	O
other	O
traditional	O
programming	O
languages	O
like	O
C++	B-Language
.	O
</s>
<s>
The	O
example	O
is	O
in	O
VHDL	B-Language
2008	O
language	O
.	O
</s>
<s>
A	O
large	O
subset	O
of	O
VHDL	B-Language
cannot	O
be	O
translated	O
into	O
hardware	O
.	O
</s>
<s>
This	O
subset	O
is	O
known	O
as	O
the	O
non-synthesizable	O
or	O
the	O
simulation-only	O
subset	O
of	O
VHDL	B-Language
and	O
can	O
only	O
be	O
used	O
for	O
prototyping	O
,	O
simulation	O
and	O
debugging	O
.	O
</s>
<s>
is	O
an	O
open	B-Application
source	I-Application
VHDL	B-Language
compiler	O
that	O
can	O
execute	O
VHDL	B-Language
programs	O
.	O
</s>
<s>
by	O
Symphony	O
EDA	O
is	O
a	O
free	O
commercial	O
VHDL	B-Language
simulator	O
.	O
</s>
<s>
by	O
Edwin	O
Naroska	O
was	O
an	O
open	B-Application
source	I-Application
VHDL	B-Language
simulator	O
,	O
abandoned	O
since	O
2001	O
.	O
</s>
