<s>
VEGA	B-General_Concept
Microprocessors	I-General_Concept
are	O
a	O
portfolio	O
of	O
indigenous	O
processors	O
developed	O
by	O
C-DAC	O
.	O
</s>
<s>
The	O
portfolio	O
includes	O
several	O
32-bit/64	O
-bit	O
Single/Multi	O
-core	O
Superscalar	O
In-order/Out	O
-of-Order	O
high	O
performance	O
processors	O
based	O
on	O
the	O
RISC-V	B-Device
ISA	O
.	O
</s>
<s>
These	O
high-performance	O
processors	O
are	O
based	O
on	O
the	O
open-source	O
RISC-V	B-Device
Instruction	O
Set	O
Architecture	O
.	O
</s>
<s>
Vega	B-General_Concept
processors	I-General_Concept
are	O
used	O
in	O
“	O
Swadeshi	O
Microprocessor	O
Challenge	O
-	O
Innovate	O
Solutions	O
for	O
#Atmanirbhar	O
Bharat	O
”	O
.	O
</s>
<s>
There	O
are	O
many	O
variants	O
for	O
vega	B-General_Concept
microprocessors	I-General_Concept
,	O
including	O
:	O
</s>
<s>
VEGA	O
ET1031	O
is	O
a	O
compact	O
and	O
efficient	O
32-bit	O
,	O
3-stage	O
in-order	O
processor	O
based	O
on	O
RISC-V	B-Device
Instruction	O
Set	O
Architecture	O
.	O
</s>
<s>
It	O
is	O
based	O
on	O
RISC-V	B-Device
(	O
RV32IM	O
)	O
Instruction	O
Set	O
Architecture	O
and	O
contains	O
a	O
high-performance	O
multiply/divide	O
unit	O
,	O
configurable	O
AXI4	O
or	O
AHB	O
external	O
interface	O
,	O
optional	O
MPU	O
(	O
Memory	O
Protection	O
Unit	O
)	O
,	O
Platform	O
Level	O
Interrupt	O
Controller	O
and	O
advanced	O
Integrated	O
Debug	O
Controller	O
.	O
</s>
<s>
VEGA	O
AS1061	O
is	O
a	O
64-bit	O
,	O
6	O
stage	O
in-order	O
pipelined	O
processor	O
based	O
on	O
RISC-V	B-Device
64GC	O
(	O
RV64IMAFDC	O
)	O
Instruction	O
Set	O
Architecture	O
.	O
</s>
<s>
The	O
pipeline	O
is	O
highly	O
configurable	O
and	O
can	O
support	O
the	O
RISC-V	B-Device
RV64	O
IMAFDC	O
extensions	O
.	O
</s>
<s>
The	O
design	O
supports	O
RISC-V	B-Device
64G	O
(	O
RV64IMAFD	O
)	O
Instruction	O
Set	O
Architecture	O
in	O
a	O
13-16	O
stage	O
out-of-order	O
pipeline	O
implementation	O
.	O
</s>
<s>
The	O
design	O
supports	O
RISC-V	B-Device
64G	O
(	O
RV64IMAFD	O
)	O
Instruction	O
Set	O
Architecture	O
in	O
a	O
13-16	O
stage	O
out-of-order	O
pipeline	O
implementation	O
.	O
</s>
<s>
The	O
design	O
supports	O
RISC-V	B-Device
64G	O
(	O
RV64IMAFD	O
)	O
Instruction	O
Set	O
Architecture	O
in	O
a	O
13-16	O
stage	O
out-of-order	O
pipeline	O
implementation	O
along	O
with	O
advanced	O
branch	O
prediction	O
unit	O
,	O
L1	O
Caches	O
,	O
MMU	O
,	O
TLB	O
etc	O
.	O
</s>
<s>
THEJAS32	O
SoC	O
is	O
built	O
around	O
VEGA	O
ET1031	O
,	O
a	O
32-bit	O
high	O
performance	O
microcontroller	O
class	O
processor	O
consisting	O
of	O
a	O
3-stage	O
in-order	O
RISC-V	B-Device
based	O
core	O
.	O
</s>
<s>
The	O
complete	O
ecosystem	O
available	O
for	O
Embedded	O
Systems	O
design	O
with	O
the	O
VEGA	B-General_Concept
processors	I-General_Concept
consists	O
of	O
Board	O
Support	O
Packages	O
,	O
SDK	O
with	O
integrated	O
tool	O
chain	O
,	O
IDE	O
plug-ins	O
and	O
Debugger	O
for	O
the	O
development	O
,	O
testing	O
and	O
debugging	O
.	O
</s>
<s>
This	O
development	O
board	O
is	O
built	O
upon	O
a	O
RISC-V	B-Device
ISA	O
compliant	O
VEGA	B-General_Concept
Processor	I-General_Concept
with	O
easy-to-use	O
hardware	O
and	O
software	O
.	O
</s>
