<s>
The	O
V-11	B-Device
,	O
code-named	O
"	O
Scorpio	O
"	O
,	O
is	O
a	O
miniprocessor	O
chip	O
set	O
implementation	O
of	O
the	O
VAX	B-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
developed	O
and	O
fabricated	B-Architecture
by	O
Digital	O
Equipment	O
Corporation	O
(	O
DEC	O
)	O
.	O
</s>
<s>
The	O
V-11	B-Device
was	O
Digital	O
's	O
first	O
VAX	B-Device
microprocessor	O
design	O
,	O
but	O
was	O
the	O
second	O
to	O
ship	O
,	O
after	O
the	O
MicroVAX	B-Device
78032	I-Device
.	O
</s>
<s>
It	O
was	O
presented	O
at	O
the	O
39th	O
International	O
Solid	O
State	O
Circuits	O
Conference	O
held	O
in	O
1984	O
alongside	O
the	O
MicroVAX	B-Device
78032	I-Device
and	O
was	O
introduced	O
in	O
early	O
1986	O
in	O
systems	O
,	O
operating	O
at	O
5	O
MHz	O
(	O
200	O
ns	O
cycle	O
time	O
)	O
and	O
in	O
1987	O
at	O
6.25MHz	O
(	O
160	O
ns	O
cycle	O
time	O
)	O
.	O
</s>
<s>
The	O
V-11	B-Device
was	O
proprietary	O
to	O
DEC	O
and	O
was	O
only	O
used	O
in	O
their	O
VAX	B-Device
8200	O
,	O
VAX	B-Device
8250	O
,	O
VAX	B-Device
8300	O
and	O
VAX	B-Device
8350	O
minicomputers	B-Architecture
;	O
and	O
the	O
VAXstation	O
8000	O
workstation	B-Device
.	O
</s>
<s>
At	O
5	O
MHz	O
,	O
the	O
V-11	B-Device
performed	O
approximately	O
the	O
same	O
as	O
the	O
VAX-11/780	O
superminicomputer	B-Device
.	O
</s>
<s>
At	O
6.25MHz	O
,	O
it	O
performed	O
approximately	O
1.2	O
times	O
faster	O
than	O
the	O
VAX-11/780	O
.	O
</s>
<s>
The	O
V-11	B-Device
was	O
part	O
of	O
the	O
Scorpio	O
program	O
,	O
which	O
aimed	O
at	O
providing	O
DEC	O
with	O
the	O
ability	O
to	O
develop	O
and	O
fabricate	O
very-large-scale	O
integration	O
(	O
VLSI	O
)	O
integrated	O
circuits	O
(	O
ICs	O
)	O
.	O
</s>
<s>
Other	O
aspects	O
of	O
the	O
program	O
were	O
the	O
development	O
of	O
a	O
new	O
computer-aided	B-Application
design	I-Application
(	O
CAD	B-Application
)	O
suite	O
and	O
semiconductor	O
process	O
,	O
the	O
results	O
of	O
which	O
are	O
CHAS	O
and	O
ZMOS	B-Device
,	O
respectively	O
.	O
</s>
<s>
ZMOS	B-Device
was	O
the	O
first	O
semiconductor	O
process	O
to	O
be	O
developed	O
entirely	O
by	O
DEC	O
.	O
</s>
<s>
The	O
V-11	B-Device
was	O
a	O
multichip	O
design	O
,	O
mainly	O
consisting	O
of	O
an	O
I/E	O
chip	O
,	O
a	O
M	O
chip	O
,	O
a	O
F	O
chip	O
and	O
five	O
ROM/RAM	O
chips	O
.	O
</s>
<s>
Unlike	O
the	O
MicroVAX	B-Device
78032	I-Device
,	O
which	O
implemented	O
a	O
subset	O
of	O
VAX	B-Device
ISA	O
,	O
the	O
V-11	B-Device
was	O
a	O
complete	O
VAX	B-Device
implementation	O
,	O
supporting	O
all	O
of	O
the	O
304	O
instructions	O
and	O
17	O
data	O
types	O
(	O
byte	O
,	O
word	O
,	O
longword	O
,	O
quadword	O
,	O
octaword	O
,	O
F-floating	O
,	O
D-floating	O
,	O
G-floating	O
,	O
H-floating	O
,	O
bit	O
,	O
variable-length	O
bit	O
field	O
,	O
character	O
string	O
,	O
trailing	O
numeric	O
string	O
,	O
leading	O
separate	O
numeric	O
string	O
,	O
packed	O
decimal	O
string	O
,	O
absolute	O
queue	O
,	O
and	O
self-relative	O
queue	O
)	O
.	O
</s>
<s>
The	O
MIB	O
(	O
microinstruction	O
bus	O
)	O
carried	O
microinstructions	O
control	O
signals	O
and	O
addresses	O
from	O
the	O
control	B-General_Concept
store	I-General_Concept
to	O
the	O
I/E	O
and	O
F	O
chips	O
.	O
</s>
<s>
The	O
MIB	O
is	O
40	O
bits	O
wide	O
,	O
the	O
same	O
width	O
as	O
a	O
microword	O
and	O
is	O
parity	B-Error_Name
protected	O
.	O
</s>
<s>
The	O
DAL	O
is	O
a	O
32-bit	O
parity-protected	O
bus	O
that	O
carries	O
data	O
and	O
addresses	O
to	O
and	O
from	O
the	O
I/E	O
,	O
M	O
and	O
F	O
chips	O
,	O
cache	O
,	O
backup	O
translation	O
buffer	O
RAMs	B-Architecture
and	O
the	O
port	O
interface	O
.	O
</s>
<s>
The	O
ROM/RAM	O
chip	O
(	O
DC327	O
)	O
implemented	O
one-fifth	O
of	O
the	O
patchable	O
control	B-General_Concept
store	I-General_Concept
.	O
</s>
<s>
It	O
contained	O
a	O
16,384	O
by	O
8-bit	O
(	O
16	O
KB	O
)	O
read-only	B-Device
memory	I-Device
(	O
ROM	B-Device
)	O
,	O
a	O
1,024	O
by	O
8-bit	O
(	O
1	O
KB	O
)	O
random-access	B-Architecture
memory	I-Architecture
RAM	B-Architecture
and	O
a	O
32	O
by	O
14-bit	O
content-addressable	B-Data_Structure
memory	I-Data_Structure
(	O
CAM	B-Data_Structure
)	O
.	O
</s>
<s>
The	O
ROM	B-Device
contained	O
the	O
control	B-General_Concept
store	I-General_Concept
,	O
with	O
the	O
RAM	B-Architecture
used	O
to	O
hold	O
control	B-General_Concept
store	I-General_Concept
patches	O
.	O
</s>
<s>
The	O
ROM/RAM	O
consisted	O
of	O
208,000	O
transistors	O
on	O
a	O
die	O
measuring	O
344	O
mils	O
by	O
285	O
mils	O
(	O
8.74	O
mm	O
by	O
7.24	O
mm	O
)	O
for	O
an	O
area	O
of	O
98,040	O
mil2	O
(	O
63.25	O
mm2	O
)	O
.	O
</s>
<s>
The	O
I/E	O
chip	O
(	O
DC328	O
)	O
contained	O
an	O
instruction	O
buffer	O
,	O
a	O
microsequencer	B-General_Concept
,	O
an	O
execution	B-General_Concept
unit	I-General_Concept
and	O
a	O
mini-translation	O
buffer	O
(	O
MTB	O
)	O
.	O
</s>
<s>
The	O
execution	B-General_Concept
unit	I-General_Concept
consisted	O
of	O
sixteen	O
32-bit	O
general	O
purpose	O
registers	O
defined	O
by	O
the	O
VAX	B-Device
ISA	O
,	O
an	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
and	O
a	O
shifter	O
.	O
</s>
<s>
The	O
MTB	O
is	O
a	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
.	O
</s>
<s>
It	O
contained	O
five	O
page	B-General_Concept
table	I-General_Concept
entries	I-General_Concept
(	O
PTEs	O
)	O
,	O
one	O
for	O
instruction	O
and	O
four	O
for	O
data	O
.	O
</s>
<s>
The	O
M	O
chip	O
(	O
DC329	O
)	O
was	O
responsible	O
for	O
memory	B-General_Concept
management	I-General_Concept
and	O
interrupt	O
handling	O
.	O
</s>
<s>
It	O
contained	O
the	O
backup	O
translation	O
buffer	O
(	O
BTB	O
)	O
tags	O
,	O
cache	O
tags	O
and	O
internal	O
processor	B-General_Concept
registers	I-General_Concept
.	O
</s>
<s>
The	O
M	O
chip	O
also	O
contained	O
the	O
I/O	O
functionality	O
defined	O
by	O
the	O
VAX	B-Device
architecture	O
and	O
generated	O
the	O
clock	O
signal	O
for	O
the	O
chip	O
set	O
.	O
</s>
<s>
The	O
backup	O
translation	O
buffer	O
was	O
essentially	O
a	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
which	O
handled	O
a	O
miss	O
in	O
the	O
MTB	O
.	O
</s>
<s>
The	O
BTB	O
contained	O
512	O
page	B-General_Concept
table	I-General_Concept
entries	I-General_Concept
(	O
PTEs	O
)	O
,	O
of	O
which	O
256	O
were	O
for	O
system-space	O
pages	O
and	O
256	O
were	O
for	O
process-space	O
pages	O
.	O
</s>
<s>
The	O
BTB	O
was	O
implemented	O
with	O
external	O
RAMs	B-Architecture
.	O
</s>
<s>
There	O
are	O
26	O
internal	O
processor	B-General_Concept
registers	I-General_Concept
,	O
which	O
are	O
used	O
by	O
the	O
microcode	O
for	O
temporary	O
storage	O
when	O
executing	O
complex	O
instructions	O
requiring	O
multiple	O
cycles	O
.	O
</s>
<s>
The	O
F	O
chip	O
(	O
DC330	O
)	O
contained	O
a	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
.	O
</s>
<s>
It	O
supported	O
most	O
VAX	B-Device
floating-point	O
instructions	O
and	O
the	O
,	O
and	O
data	O
types	O
defined	O
in	O
the	O
VAX	B-Device
architecture	O
and	O
was	O
also	O
responsible	O
for	O
executing	O
integer	O
divide	O
and	O
multiply	O
instructions	O
.	O
</s>
<s>
The	O
F	O
chip	O
received	O
opcodes	B-Language
from	O
the	O
I/E	O
chip	O
and	O
microinstructions	O
from	O
the	O
control	B-General_Concept
store	I-General_Concept
over	O
the	O
MIB	O
bus	O
.	O
</s>
<s>
The	O
F	O
chip	O
was	O
a	O
derivative	O
of	O
the	O
FPA	O
,	O
which	O
belonged	O
to	O
the	O
J-11	B-Device
microprocessor	O
chip	O
set	O
,	O
an	O
implementation	O
of	O
the	O
PDP-11	B-Device
.	O
</s>
<s>
The	O
F	O
chip	O
was	O
supposed	O
to	O
be	O
a	O
completely	O
new	O
design	O
developed	O
for	O
the	O
V-11	B-Device
,	O
but	O
was	O
cancelled	O
in	O
favor	O
of	O
a	O
derivative	O
as	O
part	O
of	O
an	O
effort	O
to	O
simplify	O
the	O
V-11	B-Device
so	O
it	O
could	O
be	O
completed	O
quicker	O
as	O
development	O
of	O
the	O
MicroVAX	B-Device
78032	I-Device
had	O
begun	O
.	O
</s>
<s>
The	O
V-11	B-Device
has	O
an	O
external	O
8	O
KB	O
primary	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
cache	O
was	O
physically	O
addressed	O
and	O
has	O
a	O
64-byte	O
cache	B-General_Concept
block	I-General_Concept
.	O
</s>
<s>
The	O
V-11	B-Device
chip	O
set	O
contained	O
a	O
total	O
of	O
1,183,600	O
transistors	O
spread	O
over	O
nine	O
dies	O
fabricated	B-Architecture
in	O
Digital	O
's	O
ZMOS	B-Device
process	O
,	O
a	O
3.0	O
µm	O
NMOS	B-Algorithm
process	O
with	O
two	O
levels	O
of	O
interconnect	O
.	O
</s>
