<s>
The	O
Unibus	B-Device
was	O
the	O
earliest	O
of	O
several	O
computer	B-General_Concept
bus	I-General_Concept
and	O
backplane	B-Architecture
designs	O
used	O
with	O
PDP-11	B-Device
and	O
early	O
VAX	B-Device
systems	O
manufactured	O
by	O
the	O
Digital	O
Equipment	O
Corporation	O
(	O
DEC	O
)	O
of	O
Maynard	O
,	O
Massachusetts	O
.	O
</s>
<s>
The	O
Unibus	B-Device
was	O
developed	O
around	O
1969	O
by	O
Gordon	O
Bell	O
and	O
student	O
Harold	O
McFarland	O
while	O
at	O
Carnegie	O
Mellon	O
University	O
.	O
</s>
<s>
The	O
name	O
refers	O
to	O
the	O
unified	O
nature	O
of	O
the	O
bus	B-General_Concept
;	O
Unibus	B-Device
was	O
used	O
both	O
as	O
a	O
system	B-Architecture
bus	I-Architecture
allowing	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
to	O
communicate	O
with	O
main	O
memory	O
,	O
as	O
well	O
as	O
a	O
peripheral	B-Architecture
bus	I-Architecture
,	O
allowing	O
peripherals	O
to	O
send	O
and	O
receive	O
data	O
.	O
</s>
<s>
Unifying	O
these	O
formerly	O
separate	O
busses	O
allowed	O
external	O
devices	O
to	O
easily	O
perform	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	O
)	O
and	O
made	O
the	O
construction	O
of	O
device	B-Application
drivers	I-Application
easier	O
as	O
control	O
and	O
data	O
exchange	O
was	O
all	O
handled	O
through	O
memory-mapped	B-Architecture
I/O	I-Architecture
.	O
</s>
<s>
Unibus	B-Device
was	O
physically	O
large	O
,	O
which	O
led	O
to	O
the	O
introduction	O
of	O
Q-bus	B-Architecture
,	O
which	O
multiplexed	B-Architecture
some	O
signals	O
to	O
reduce	O
pin	O
count	O
.	O
</s>
<s>
The	O
system	O
was	O
later	O
supplanted	O
by	O
Massbus	B-Architecture
,	O
a	O
dedicated	O
I/O	B-General_Concept
bus	I-General_Concept
introduced	O
on	O
the	O
VAX	B-Device
and	O
late-model	O
PDP-11s	B-Device
.	O
</s>
<s>
The	O
Unibus	B-Device
consists	O
of	O
72	O
signals	O
,	O
usually	O
connected	O
via	O
two	O
36-way	O
edge	O
connectors	O
on	O
each	O
printed	O
circuit	O
board	O
.	O
</s>
<s>
When	O
not	O
counting	O
the	O
power	O
and	O
ground	O
lines	O
,	O
it	O
is	O
usually	O
referred	O
to	O
as	O
a	O
56-line	O
bus	B-General_Concept
.	O
</s>
<s>
It	O
can	O
exist	O
within	O
a	O
backplane	B-Architecture
or	O
on	O
a	O
cable	O
.	O
</s>
<s>
Up	O
to	O
20	O
nodes	O
(	O
devices	O
)	O
can	O
be	O
connected	O
to	O
a	O
single	O
Unibus	B-Device
segment	O
;	O
additional	O
segments	O
can	O
be	O
connected	O
via	O
a	O
bus	B-General_Concept
repeater	O
.	O
</s>
<s>
The	O
bus	B-General_Concept
is	O
completely	O
asynchronous	B-Application
,	O
allowing	O
a	O
mixture	O
of	O
fast	O
and	O
slow	O
devices	O
.	O
</s>
<s>
It	O
allows	O
the	O
overlapping	O
of	O
arbitration	O
(	O
selection	O
of	O
the	O
next	O
bus	B-General_Concept
master	O
)	O
while	O
the	O
current	O
bus	B-General_Concept
master	O
is	O
still	O
performing	O
data	O
transfers	O
.	O
</s>
<s>
Typically	O
,	O
the	O
top	O
is	O
reserved	O
for	O
the	O
registers	O
of	O
the	O
memory-mapped	B-Architecture
I/O	I-Architecture
devices	O
used	O
in	O
the	O
PDP-11	B-Device
architecture	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
system	O
always	O
contains	O
more	O
slave	O
devices	O
than	O
master	O
devices	O
so	O
most	O
of	O
the	O
complex	O
logic	O
required	O
to	O
implement	O
asynchronous	B-Application
data	O
transfers	O
is	O
forced	O
into	O
the	O
relatively	O
few	O
master	O
devices	O
.	O
</s>
<s>
Type	O
1	O
lines	O
are	O
a	O
normal	O
multi-sender	O
wired-OR	O
bus	B-General_Concept
with	O
pull-up	O
resistors	O
at	O
each	O
end	O
of	O
the	O
bus	B-General_Concept
,	O
typically	O
on	O
a	O
terminator	O
card	O
.	O
</s>
<s>
They	O
warn	O
the	O
devices	O
on	O
the	O
bus	B-General_Concept
when	O
the	O
power	O
is	O
about	O
to	O
fail	O
,	O
so	O
those	O
devices	O
can	O
execute	O
an	O
orderly	O
shutdown	O
,	O
and	O
disable	O
operations	O
to	O
prevent	O
spurious	O
writes	O
.	O
</s>
