<s>
UniDIMM	B-General_Concept
(	O
short	O
for	O
Universal	B-General_Concept
DIMM	I-General_Concept
)	O
is	O
a	O
specification	O
for	O
dual	B-General_Concept
in-line	I-General_Concept
memory	I-General_Concept
modules	I-General_Concept
(	O
DIMMs	B-General_Concept
)	O
,	O
which	O
are	O
printed	O
circuit	O
boards	O
(	O
PCBs	O
)	O
designed	O
to	O
carry	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
DRAM	O
)	O
chips	O
.	O
</s>
<s>
UniDIMMs	B-General_Concept
can	O
be	O
populated	O
with	O
either	O
DDR3	O
or	O
DDR4	O
chips	O
,	O
with	O
no	O
support	O
for	O
any	O
additional	O
memory	O
control	O
logic	O
;	O
as	O
a	O
result	O
,	O
the	O
computer	O
's	O
memory	B-General_Concept
controller	I-General_Concept
must	O
support	O
both	O
DDR3	O
and	O
DDR4	O
memory	O
standards	O
.	O
</s>
<s>
The	O
UniDIMM	B-General_Concept
specification	O
was	O
created	O
by	O
Intel	O
for	O
its	O
Skylake	B-Architecture
microarchitecture	I-Architecture
,	O
whose	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
(	O
IMC	O
)	O
supports	O
both	O
DDR3	O
(	O
more	O
specifically	O
,	O
the	O
DDR3L	O
low-voltage	O
variant	O
)	O
and	O
DDR4	O
memory	O
technologies	O
.	O
</s>
<s>
UniDIMM	B-General_Concept
is	O
a	O
SO-DIMM	O
form	O
factor	O
available	O
in	O
two	O
dimensions	O
:	O
for	O
the	O
standard	O
UniDIMM	B-General_Concept
version	O
(	O
the	O
same	O
size	O
as	O
DDR4	O
SO-DIMMs	O
)	O
,	O
and	O
for	O
the	O
low-profile	O
version	O
.	O
</s>
<s>
UniDIMMs	B-General_Concept
have	O
a	O
260-pin	O
edge	O
connector	O
,	O
which	O
has	O
the	O
same	O
pin	O
count	O
as	O
the	O
one	O
on	O
DDR4	O
SO-DIMMs	O
,	O
with	O
the	O
keying	O
notch	O
in	O
a	O
position	O
that	O
prevents	O
incompatible	O
installation	O
by	O
making	O
UniDIMMs	B-General_Concept
physically	O
incompatible	O
with	O
standard	O
DDR3	O
and	O
DDR4	O
SO-DIMM	O
sockets	O
.	O
</s>
<s>
Because	O
of	O
the	O
lower	O
operating	O
voltage	O
of	O
DDR4	O
chips	O
(	O
1.2V	O
)	O
compared	O
with	O
the	O
operating	O
voltage	O
of	O
DDR3	O
chips	O
(	O
1.5V	O
for	O
regular	O
DDR3	O
and	O
1.35V	O
for	O
low-voltage	O
DDR3L	O
)	O
,	O
UniDIMMs	B-General_Concept
are	O
designed	O
to	O
contain	O
additional	O
built-in	O
voltage	O
regulation	O
circuitry	O
.	O
</s>
<s>
The	O
UniDIMM	B-General_Concept
specification	O
was	O
created	O
to	O
ease	O
the	O
market	O
transition	O
from	O
DDR3	O
to	O
DDR4	O
SDRAM	O
.	O
</s>
<s>
In	O
previous	O
RAM	B-Architecture
standard	O
transitions	O
,	O
as	O
it	O
was	O
the	O
case	O
when	O
DDR2	O
was	O
phased	O
out	O
in	O
favor	O
of	O
DDR3	O
,	O
having	O
an	O
emerging	O
RAM	B-Architecture
standard	O
as	O
a	O
new	O
product	O
line	O
created	O
a	O
"	O
chicken-and-egg	O
"	O
problem	O
because	O
its	O
manufacturing	O
is	O
initially	O
more	O
expensive	O
,	O
yields	O
low	O
demand	O
,	O
and	O
results	O
in	O
low	O
production	O
rates	O
.	O
</s>
<s>
The	O
DDR2	O
to	O
DDR3	O
transition	O
issues	O
were	O
sometimes	O
handled	O
with	O
specific	O
motherboards	B-Device
that	O
provided	O
separate	O
slots	O
for	O
DDR2	O
and	O
DDR3	O
modules	O
,	O
out	O
of	O
which	O
only	O
one	O
kind	O
could	O
be	O
used	O
.	O
</s>
<s>
By	O
its	O
design	O
,	O
the	O
UniDIMM	B-General_Concept
specification	O
allows	O
either	O
DDR3	O
or	O
DDR4	O
memory	O
to	O
be	O
used	O
in	O
the	O
same	O
memory	O
module	O
slots	O
,	O
resulting	O
in	O
no	O
wasted	O
motherboard	B-Device
space	O
that	O
would	O
otherwise	O
be	O
occupied	O
by	O
unused	O
slots	O
.	O
</s>
<s>
,	O
UniDIMM	B-General_Concept
is	O
not	O
standardized	O
by	O
JEDEC	O
,	O
having	O
Kingston	O
and	O
Micron	O
as	O
its	O
main	O
supporters	O
.	O
</s>
<s>
Despite	O
the	O
availability	O
of	O
UniDIMM	B-General_Concept
specification	O
and	O
announced	O
manufacturer	O
support	O
,	O
there	O
are	O
no	O
commercial	O
UniDIMM	B-General_Concept
products	O
available	O
and	O
no	O
release	O
dates	O
have	O
been	O
set	O
by	O
the	O
manufacturers	O
.	O
</s>
<s>
As	O
DDR3	O
has	O
become	O
more	O
irrelevant	O
after	O
years	O
of	O
DDR4	O
availability	O
,	O
it	O
is	O
looking	O
increasingly	O
unlikely	O
that	O
manufacturers	O
will	O
ever	O
implement	O
UniDIMM	B-General_Concept
.	O
</s>
