<s>
"	O
Uncore	B-General_Concept
"	O
is	O
a	O
term	O
used	O
by	O
Intel	O
to	O
describe	O
the	O
functions	O
of	O
a	O
microprocessor	B-Architecture
that	O
are	O
not	O
in	O
the	O
core	O
,	O
but	O
which	O
must	O
be	O
closely	O
connected	O
to	O
the	O
core	O
to	O
achieve	O
high	O
performance	O
.	O
</s>
<s>
It	O
has	O
been	O
called	O
"	O
system	B-General_Concept
agent	I-General_Concept
"	O
since	O
the	O
release	O
of	O
the	O
Sandy	B-Device
Bridge	I-Device
microarchitecture	B-General_Concept
.	O
</s>
<s>
The	O
core	O
contains	O
the	O
components	O
of	O
the	O
processor	O
involved	O
in	O
executing	O
instructions	O
,	O
including	O
the	O
ALU	B-General_Concept
,	O
FPU	B-General_Concept
,	O
L1	O
and	O
L2	O
cache	O
.	O
</s>
<s>
Uncore	B-General_Concept
functions	O
include	O
QPI	B-Architecture
controllers	O
,	O
L3	O
cache	O
,	O
snoop	B-Operating_System
agent	I-Operating_System
pipeline	B-General_Concept
,	O
on-die	O
memory	B-General_Concept
controller	I-General_Concept
,	O
on-die	O
PCI	B-Architecture
Express	I-Architecture
Root	I-Architecture
Complex	I-Architecture
,	O
and	O
Thunderbolt	B-Protocol
controller	I-Protocol
.	O
</s>
<s>
Other	O
bus	O
controllers	O
such	O
as	O
SPI	B-Architecture
and	O
LPC	O
are	O
part	O
of	O
the	O
chipset	B-Device
.	O
</s>
<s>
The	O
Intel	O
uncore	B-General_Concept
design	O
stems	O
from	O
its	O
origin	O
as	O
the	O
northbridge	B-Device
.	O
</s>
<s>
The	O
design	O
of	O
the	O
Intel	O
uncore	B-General_Concept
reorganizes	O
the	O
functions	O
critical	O
to	O
the	O
core	O
,	O
making	O
them	O
physically	O
closer	O
to	O
the	O
core	O
on-die	O
,	O
thereby	O
reducing	O
their	O
access	O
latency	O
.	O
</s>
<s>
Specifically	O
,	O
the	O
microarchitecture	B-General_Concept
of	O
the	O
Intel	O
uncore	B-General_Concept
is	O
broken	O
down	O
into	O
a	O
number	O
of	O
modular	O
units	O
.	O
</s>
<s>
The	O
main	O
uncore	B-General_Concept
interface	O
to	O
the	O
core	O
is	O
the	O
so-called	O
cache	O
box	O
(	O
CBox	O
)	O
,	O
which	O
interfaces	O
with	O
the	O
last	O
level	O
cache	O
(	O
LLC	O
)	O
and	O
is	O
responsible	O
for	O
managing	O
cache	B-General_Concept
coherency	I-General_Concept
.	O
</s>
<s>
Multiple	O
internal	O
and	O
external	O
QPI	B-Architecture
links	O
are	O
managed	O
by	O
physical-layer	O
units	O
,	O
referred	O
to	O
as	O
PBox	O
.	O
</s>
<s>
Removal	O
of	O
serial	O
bus	O
controllers	O
from	O
the	O
Intel	O
uncore	B-General_Concept
further	O
enables	O
increased	O
performance	O
by	O
allowing	O
the	O
uncore	B-General_Concept
clock	O
(	O
UCLK	O
)	O
to	O
run	O
at	O
a	O
base	O
of	O
2.66GHz	O
,	O
with	O
overclocking	O
limits	O
in	O
excess	O
of	O
3.44GHz	O
.	O
</s>
<s>
This	O
increased	O
clock	O
rate	O
allows	O
the	O
core	O
to	O
access	O
critical	O
functions	O
(	O
such	O
as	O
the	O
iMC	B-General_Concept
)	O
with	O
significantly	O
less	O
latency	O
,	O
typically	O
reducing	O
core	O
access	O
times	O
to	O
DRAM	O
by	O
10ns	O
or	O
more	O
.	O
</s>
