<s>
The	O
SPARC	B-Architecture
T3	O
microprocessor	B-Architecture
(	O
previously	O
known	O
as	O
UltraSPARC	B-General_Concept
T3	I-General_Concept
,	O
codenamed	O
Rainbow	O
Falls	O
,	O
and	O
also	O
known	O
as	O
UltraSPARC	O
KT	O
or	O
Niagara-3	O
during	O
development	O
)	O
is	O
a	O
multithreading	B-General_Concept
,	O
multi-core	B-Architecture
CPU	I-Architecture
produced	O
by	O
Oracle	B-Application
Corporation	I-Application
(	O
previously	O
Sun	O
Microsystems	O
)	O
.	O
</s>
<s>
Officially	O
launched	O
on	O
20	O
September	O
2010	O
,	O
it	O
is	O
a	O
member	O
of	O
the	O
SPARC	B-Architecture
family	O
,	O
and	O
the	O
successor	O
to	O
the	O
UltraSPARC	B-Device
T2	I-Device
.	O
</s>
<s>
Overall	O
single	O
socket	O
and	O
multi-socket	O
throughput	O
increased	O
with	O
the	O
T3	O
processor	O
in	O
systems	O
,	O
providing	O
superior	O
throughput	O
with	O
half	O
the	O
CPU	B-General_Concept
socket	O
requirements	O
to	O
its	O
predecessor	O
.	O
</s>
<s>
Under	O
simulated	O
web	O
serving	O
workloads	O
,	O
dual-socket	O
based	O
SPARC	B-Architecture
T3	O
systems	O
benchmarked	O
better	O
performance	O
than	O
quad-socket	O
(	O
previous	O
generation	O
)	O
UltraSPARC	O
T2+	O
systems	O
(	O
as	O
well	O
as	O
competing	O
dual	O
and	O
quad	O
socket	O
contemporary	O
systems	O
)	O
.	O
</s>
<s>
Online	O
IT	O
publication	O
The	O
Register	O
incorrectly	O
reported	O
in	O
June	O
2008	O
that	O
the	O
microprocessor	B-Architecture
would	O
have	O
16	O
cores	O
,	O
each	O
with	O
16	O
threads	O
.	O
</s>
<s>
"	O
A	O
40nm	O
16-Core	O
128-Thread	O
CMT	O
SPARC	B-Architecture
SoC	O
Processor	O
"	O
.	O
</s>
<s>
Support	O
for	O
the	O
UltraSPARC	B-General_Concept
T3	I-General_Concept
was	O
confirmed	O
on	O
July	O
16	O
,	O
2010	O
when	O
the	O
ARCBot	O
under	O
Twitter	O
noted	O
unpublished	O
PSARC/2010/274	O
which	O
revealed	O
a	O
new	O
"	O
-xtarget	O
value	O
for	O
UltraSPARC	B-General_Concept
T3	I-General_Concept
"	O
being	O
included	O
in	O
OpenSolaris	B-Operating_System
.	O
</s>
<s>
During	O
Oracle	B-Application
OpenWorld	O
in	O
San	O
Francisco	O
on	O
September	O
20	O
,	O
2010	O
,	O
the	O
processor	O
was	O
officially	O
launched	O
as	O
the	O
"	O
SPARC	B-Architecture
T3	O
"	O
(	O
dropping	O
the	O
"	O
Ultra	O
"	O
prefix	O
in	O
its	O
name	O
)	O
,	O
accompanied	O
by	O
new	O
systems	O
and	O
new	O
reported	O
benchmarks	O
claiming	O
world-record	O
performance	O
.	O
</s>
<s>
Oracle	B-Application
disclosed	O
that	O
SPARC	B-Architecture
T3	O
was	O
built	O
with	O
a	O
40nm	O
process	O
.	O
</s>
<s>
SPARC	B-Architecture
T3	O
features	O
include	O
:	O
</s>
<s>
Security	B-General_Concept
co-processor	I-General_Concept
on	O
each	O
core	O
.	O
</s>
<s>
Supports	O
DES	B-Algorithm
,	O
3DES	B-Algorithm
,	O
AES	B-Algorithm
,	O
RC4	B-Algorithm
,	O
SHA-1	B-Algorithm
,	O
SHA-256/384/512	O
,	O
Kasumi	B-Algorithm
,	O
Galois	O
Field	O
,	O
MD5	B-Algorithm
,	O
RSA	B-Architecture
with	O
up	O
to	O
2048	O
key	O
,	O
ECC	O
,	O
CRC	O
.	O
</s>
<s>
With	O
the	O
release	O
of	O
the	O
SPARC	B-Architecture
T3	O
chip	O
,	O
the	O
new	O
brand	O
of	O
Oracle	B-Architecture
SPARC	I-Architecture
T-series	I-Architecture
servers	I-Architecture
was	O
introduced	O
to	O
the	O
market	O
,	O
effectively	O
replacing	O
CMT	O
(	O
UltraSPARC	B-Device
T2/T2	I-Device
Plus	I-Device
)	O
machines	O
from	O
the	O
previous	O
SPARC	B-Application
Enterprise	I-Application
product	O
line	O
.	O
</s>
<s>
The	O
T3	O
supports	O
up	O
to	O
128	O
Oracle	B-Application
VM	O
Server	O
for	O
SPARC	B-Architecture
domains	O
(	O
a	O
feature	O
formerly	O
known	O
as	O
Logical	O
Domains	O
)	O
.	O
</s>
<s>
The	O
SPARC	B-Architecture
T3	O
processor	O
is	O
effectively	O
two	O
T2+	O
processors	O
on	O
a	O
single	O
die	O
.	O
</s>
