<s>
Sun	O
Microsystems	O
 '	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
microprocessor	B-Architecture
,	O
known	O
until	O
its	O
14	O
November	O
2005	O
announcement	O
by	O
its	O
development	O
codename	O
"	O
Niagara	B-General_Concept
"	O
,	O
is	O
a	O
multithreading	B-Operating_System
,	O
multicore	B-Architecture
CPU	I-Architecture
.	O
</s>
<s>
Designed	O
to	O
lower	O
the	O
energy	O
consumption	O
of	O
server	O
computers	O
,	O
the	O
CPU	B-General_Concept
typically	O
uses	O
72	O
W	O
of	O
power	O
at	O
1.4GHz	O
.	O
</s>
<s>
Afara	O
Websystems	O
pioneered	O
a	O
radical	O
thread-heavy	O
SPARC	B-Architecture
design	O
.	O
</s>
<s>
The	O
T1	O
is	O
a	O
new-from-the-ground-up	O
SPARC	B-Architecture
microprocessor	B-Architecture
implementation	O
that	O
conforms	O
to	O
the	O
and	O
executes	O
the	O
full	O
SPARC	B-Architecture
V9	I-Architecture
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Sun	O
has	O
produced	O
two	O
previous	O
multicore	B-Architecture
processors	I-Architecture
(	O
UltraSPARC	B-General_Concept
IV	I-General_Concept
and	O
IV+	O
)	O
,	O
but	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
was	O
its	O
first	O
microprocessor	B-Architecture
that	O
is	O
both	O
multicore	B-Architecture
and	O
multithreaded	O
.	O
</s>
<s>
The	O
processor	O
is	O
available	O
with	O
four	O
,	O
six	O
or	O
eight	O
CPU	B-Architecture
cores	I-Architecture
,	O
each	O
core	O
able	O
to	O
handle	O
four	O
threads	B-Operating_System
concurrently	O
.	O
</s>
<s>
Thus	O
,	O
the	O
processor	O
is	O
capable	O
of	O
processing	O
up	O
to	O
32	O
threads	B-Operating_System
concurrently	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
can	O
be	O
partitioned	O
in	O
a	O
similar	O
way	O
to	O
high-end	O
Sun	O
SMP	B-Operating_System
systems	O
.	O
</s>
<s>
Thus	O
,	O
several	O
cores	O
can	O
be	O
partitioned	O
for	O
running	O
a	O
single	O
or	O
group	O
of	O
processes	O
and/or	O
threads	B-Operating_System
,	O
while	O
the	O
other	O
cores	O
deal	O
with	O
the	O
rest	O
of	O
the	O
processes	O
on	O
the	O
system	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
was	O
designed	O
from	O
scratch	O
as	O
a	O
multi-threaded	B-Operating_System
,	O
special-purpose	O
processor	O
,	O
and	O
thus	O
introduced	O
a	O
whole	O
new	O
architecture	O
for	O
obtaining	O
performance	O
.	O
</s>
<s>
Rather	O
than	O
try	O
to	O
make	O
each	O
core	O
as	O
intelligent	O
and	O
optimized	O
as	O
they	O
can	O
,	O
Sun	O
's	O
goal	O
was	O
to	O
run	O
as	O
many	O
concurrent	B-Operating_System
threads	B-Operating_System
as	O
possible	O
,	O
and	O
maximize	O
utilization	O
of	O
each	O
core	O
's	O
pipeline	B-General_Concept
.	O
</s>
<s>
The	O
cores	O
do	O
not	O
feature	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
or	O
a	O
sizable	O
amount	O
of	O
cache	B-General_Concept
.	O
</s>
<s>
Single-thread	B-Operating_System
processors	O
depend	O
heavily	O
on	O
large	O
caches	O
for	O
their	O
performance	O
because	O
cache	B-General_Concept
misses	O
result	O
in	O
a	O
wait	O
while	O
the	O
data	O
is	O
fetched	O
from	O
main	O
memory	O
.	O
</s>
<s>
By	O
making	O
the	O
cache	B-General_Concept
larger	O
,	O
the	O
probability	O
of	O
a	O
cache	B-General_Concept
miss	O
is	O
reduced	O
,	O
but	O
the	O
impact	O
of	O
a	O
miss	O
is	O
still	O
the	O
same	O
.	O
</s>
<s>
The	O
T1	O
cores	O
largely	O
side-step	O
the	O
issue	O
of	O
cache	B-General_Concept
misses	O
by	O
multithreading	B-Operating_System
.	O
</s>
<s>
Each	O
core	O
is	O
a	O
barrel	B-Operating_System
processor	I-Operating_System
,	O
meaning	O
it	O
switches	O
between	O
available	O
threads	B-Operating_System
each	O
cycle	O
.	O
</s>
<s>
When	O
a	O
long-latency	O
event	O
occurs	O
,	O
such	O
as	O
cache	B-General_Concept
miss	O
,	O
the	O
thread	B-Operating_System
is	O
taken	O
out	O
of	O
rotation	O
while	O
the	O
data	O
is	O
fetched	O
into	O
cache	B-General_Concept
in	O
the	O
background	O
.	O
</s>
<s>
Once	O
the	O
long-latency	O
event	O
completes	O
,	O
the	O
thread	B-Operating_System
is	O
made	O
available	O
for	O
execution	O
again	O
.	O
</s>
<s>
Sharing	O
of	O
the	O
pipeline	B-General_Concept
by	O
multiple	O
threads	B-Operating_System
may	O
make	O
each	O
thread	B-Operating_System
slower	O
,	O
but	O
the	O
overall	O
throughput	O
(	O
and	O
utilization	O
)	O
of	O
each	O
core	O
is	O
much	O
higher	O
.	O
</s>
<s>
It	O
also	O
means	O
that	O
the	O
impact	O
of	O
cache	B-General_Concept
misses	O
is	O
greatly	O
reduced	O
,	O
and	O
the	O
T1	O
can	O
maintain	O
high	O
throughput	O
with	O
a	O
smaller	O
amount	O
of	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
cache	B-General_Concept
no	O
longer	O
needs	O
to	O
be	O
large	O
enough	O
to	O
hold	O
all	O
or	O
most	O
of	O
the	O
"	O
working	O
set	O
"	O
,	O
just	O
the	O
recent	O
cache	B-General_Concept
misses	O
of	O
each	O
thread	B-Operating_System
.	O
</s>
<s>
Benchmarks	O
demonstrate	O
this	O
approach	O
has	O
worked	O
very	O
well	O
on	O
commercial	O
(	O
integer	O
)	O
,	O
multithreaded	O
workloads	O
such	O
as	O
Java	B-Language
application	O
servers	O
,	O
Enterprise	O
Resource	O
Planning	O
(	O
ERP	O
)	O
application	O
servers	O
,	O
email	O
(	O
such	O
as	O
Lotus	B-Operating_System
Domino	I-Operating_System
)	O
servers	O
,	O
and	O
web	B-Application
servers	I-Application
.	O
</s>
<s>
These	O
benchmarks	O
suggest	O
each	O
core	O
in	O
the	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
is	O
more	O
powerful	O
than	O
the	O
circa	O
2001	O
,	O
single-core	O
,	O
single-threaded	B-Operating_System
UltraSPARC	O
III	O
,	O
and	O
at	O
a	O
chip	O
to	O
chip	O
comparison	O
,	O
significantly	O
outperforms	O
other	O
processors	O
on	O
multithreaded	O
integer	O
workloads	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
contains	O
279	O
million	O
transistors	O
and	O
has	O
an	O
area	O
of	O
378mm2	O
.	O
</s>
<s>
Each	O
core	O
has	O
L1	O
16KB	O
instruction	O
cache	B-General_Concept
and	O
8KB	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
L2	O
cache	B-General_Concept
is	O
3MB	O
and	O
there	O
is	O
no	O
L3	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
microprocessor	B-Architecture
is	O
unique	O
in	O
its	O
strength	O
and	O
weaknesses	O
,	O
and	O
as	O
such	O
is	O
targeted	O
at	O
specific	O
markets	O
.	O
</s>
<s>
Rather	O
than	O
being	O
used	O
for	O
high-end	B-Architecture
number-crunching	I-Architecture
and	O
ultra-high	O
performance	O
applications	O
,	O
the	O
chip	O
is	O
targeted	O
at	O
network-facing	O
high-demand	O
servers	O
,	O
such	O
as	O
high-traffic	O
web	B-Application
servers	I-Application
,	O
and	O
mid-tier	O
Java	B-Language
,	O
ERP	O
,	O
and	O
CRM	O
application	O
servers	O
,	O
which	O
often	O
utilize	O
a	O
large	O
number	O
of	O
separate	O
threads	B-Operating_System
.	O
</s>
<s>
One	O
of	O
the	O
limitations	O
of	O
the	O
T1	O
design	O
is	O
that	O
a	O
single	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
is	O
shared	O
between	O
all	O
8	O
cores	O
,	O
making	O
the	O
T1	O
unsuitable	O
for	O
applications	O
performing	O
a	O
lot	O
of	O
floating	O
point	O
mathematics	O
.	O
</s>
<s>
Sun	O
provides	O
a	O
tool	O
for	O
analysing	O
an	O
application	O
's	O
level	O
of	O
parallelism	B-Operating_System
and	O
use	O
of	O
floating	O
point	O
instructions	O
to	O
determine	O
if	O
it	O
is	O
suitable	O
for	O
use	O
on	O
a	O
T1	O
or	O
T2	O
platform	O
.	O
</s>
<s>
In	O
addition	O
to	O
web	O
and	O
application	O
tier	O
processing	O
,	O
the	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
may	O
be	O
well	O
suited	O
for	O
smaller	O
database	O
applications	O
which	O
have	O
a	O
large	O
user	O
count	O
.	O
</s>
<s>
One	O
customer	O
has	O
published	O
results	O
showing	O
that	O
a	O
MySQL	B-Application
application	O
running	O
on	O
an	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
server	O
ran	O
13.5	O
times	O
faster	O
than	O
on	O
an	O
AMD	O
Opteron	O
server	O
.	O
</s>
<s>
T1	O
is	O
the	O
first	O
SPARC	B-Architecture
processor	O
that	O
supports	O
the	O
Hyper-Privileged	O
execution	O
mode	O
.	O
</s>
<s>
The	O
SPARC	B-Architecture
Hypervisor	O
runs	O
in	O
this	O
mode	O
,	O
and	O
it	O
can	O
partition	O
a	O
T1	O
system	O
into	O
32	O
Logical	O
Domains	O
,	O
each	O
of	O
which	O
can	O
run	O
an	O
operating	O
system	O
instance	O
.	O
</s>
<s>
Currently	O
,	O
Solaris	B-Application
,	O
Linux	B-Application
,	O
NetBSD	B-Device
and	O
OpenBSD	B-Operating_System
are	O
supported	O
.	O
</s>
<s>
Traditionally	O
,	O
commercial	O
software	O
suites	O
such	O
as	O
Oracle	B-General_Concept
Database	I-General_Concept
charge	O
their	O
customers	O
based	O
on	O
the	O
number	O
of	O
processors	O
the	O
software	O
runs	O
on	O
.	O
</s>
<s>
In	O
early	O
2006	O
,	O
Oracle	B-Application
changed	O
the	O
licensing	O
model	O
by	O
introducing	O
the	O
processor	O
factor	O
.	O
</s>
<s>
With	O
a	O
processor	O
factor	O
of	O
.25	O
for	O
the	O
T1	O
,	O
an	O
8-core	O
T2000	O
requires	O
only	O
a	O
2-CPU	O
license	O
.	O
</s>
<s>
The	O
"	O
Oracle	B-Application
Processor	O
Core	O
Factor	O
Table	O
"	O
has	O
since	O
been	O
updated	O
regularly	O
as	O
new	O
CPUs	O
came	O
to	O
market	O
.	O
</s>
<s>
The	O
T1	O
only	O
offered	O
a	O
single	O
floating-point	B-General_Concept
unit	I-General_Concept
to	O
be	O
shared	O
by	O
the	O
8	O
cores	O
,	O
limiting	O
usage	O
in	O
HPC	O
environments	O
.	O
</s>
<s>
This	O
weakness	O
was	O
mitigated	O
with	O
the	O
follow-on	O
UltraSPARC	B-Device
T2	I-Device
processor	O
,	O
which	O
included	O
8	O
floating	B-General_Concept
point	I-General_Concept
units	I-General_Concept
,	O
as	O
well	O
as	O
other	O
additional	O
features	O
.	O
</s>
<s>
This	O
weakness	O
was	O
mitigated	O
with	O
the	O
follow-on	O
UltraSPARC	B-Device
T2	I-Device
Plus	I-Device
,	O
as	O
well	O
as	O
the	O
next	O
generation	O
SPARC	B-Device
T3	I-Device
and	O
SPARC	B-Device
T4	I-Device
.	O
</s>
<s>
The	O
UltraSPARC	O
T2+	O
,	O
SPARC	B-Device
T3	I-Device
,	O
and	O
SPARC	B-Device
T4	I-Device
all	O
offer	O
single	O
,	O
dual	O
,	O
and	O
quad	O
socket	O
configurations	O
.	O
</s>
<s>
The	O
T1	O
had	O
outstanding	O
throughput	O
with	O
massive	O
numbers	O
of	O
threads	B-Operating_System
supported	O
by	O
the	O
processor	O
,	O
but	O
older	O
applications	O
burdened	O
with	O
single	B-Operating_System
thread	I-Operating_System
bottlenecks	O
occasionally	O
exhibited	O
poor	O
overall	O
performance	O
.	O
</s>
<s>
Single-threaded	B-Operating_System
application	O
weakness	O
was	O
mitigated	O
with	O
the	O
follow-on	O
SPARC	B-Device
T4	I-Device
processor	O
.	O
</s>
<s>
The	O
T4	O
core	O
count	O
was	O
reduced	O
to	O
8	O
(	O
from	O
16	O
on	O
the	O
T3	O
)	O
,	O
the	O
cores	O
were	O
made	O
more	O
complex	O
,	O
the	O
clock	O
rate	O
was	O
nearly	O
doubled	O
—	O
all	O
contributing	O
to	O
faster	O
single	B-Operating_System
thread	I-Operating_System
performance	O
(	O
from	O
between	O
300%	O
to	O
500%	O
increase	O
over	O
previous	O
generations	O
)	O
.	O
</s>
<s>
Additional	O
effort	O
was	O
made	O
to	O
add	O
the	O
"	O
critical	O
thread	B-Operating_System
API	O
"	O
,	O
where	O
the	O
operating	O
system	O
would	O
detect	O
a	O
bottleneck	O
and	O
would	O
temporarily	O
allocate	O
the	O
resources	O
of	O
an	O
entire	O
core	O
,	O
instead	O
of	O
1	O
(	O
of	O
8	O
)	O
threads	B-Operating_System
,	O
to	O
the	O
targeted	O
application	O
processes	O
exhibiting	O
single	B-Operating_System
threaded	I-Operating_System
CPU	B-General_Concept
bound	O
behavior	O
.	O
</s>
<s>
This	O
allowed	O
the	O
T4	O
to	O
uniquely	O
mitigate	O
single	B-Operating_System
threaded	I-Operating_System
bottlenecks	O
,	O
while	O
not	O
having	O
to	O
compromise	O
in	O
the	O
overall	O
architecture	O
to	O
achieve	O
massive	O
multi-threaded	B-Operating_System
throughput	O
.	O
</s>
<s>
The	O
"	O
Coolthreads(TM )	O
"	O
architecture	O
,	O
beginning	O
with	O
the	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
(	O
with	O
its	O
positive	O
and	O
negative	O
aspects	O
)	O
,	O
was	O
certainly	O
influential	O
in	O
the	O
concurrent	B-Operating_System
and	O
future	O
designs	O
of	O
SPARC	B-Architecture
processors	O
.	O
</s>
<s>
The	O
original	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
was	O
designed	O
for	O
single	O
CPU	B-General_Concept
systems	O
only	O
and	O
is	O
not	O
capable	O
of	O
SMP	B-Operating_System
.	O
</s>
<s>
It	O
was	O
seen	O
as	O
more	O
a	O
follow-on	O
to	O
Sun	O
's	O
SMP	B-Operating_System
processors	O
such	O
as	O
UltraSPARC	B-General_Concept
IV	I-General_Concept
,	O
rather	O
than	O
a	O
replacement	O
for	O
the	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
or	O
T2	O
,	O
but	O
was	O
canceled	O
in	O
the	O
timeframe	O
of	O
Oracle	B-Application
's	O
acquisition	O
of	O
Sun	O
.	O
</s>
<s>
Formerly	O
known	O
by	O
the	O
codename	O
Niagara	B-Device
2	I-Device
,	O
the	O
follow-on	O
to	O
the	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
,	O
the	O
T2	O
provides	O
eight	O
cores	O
.	O
</s>
<s>
Unlike	O
the	O
T1	O
,	O
each	O
core	O
supports	O
8	O
threads	B-Operating_System
per	O
core	O
,	O
one	O
FPU	O
per	O
core	O
,	O
one	O
enhanced	O
cryptographic	O
unit	O
per	O
core	O
,	O
and	O
CPU	B-General_Concept
embedded	O
10	O
Gigabit	O
Ethernet	O
network	O
controllers	O
.	O
</s>
<s>
In	O
February	O
2007	O
,	O
Sun	O
announced	O
at	O
its	O
annual	O
analyst	O
summit	O
that	O
its	O
third-generation	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
design	O
,	O
code-named	O
Victoria	O
Falls	O
,	O
was	O
taped	O
out	O
in	O
October	O
2006	O
.	O
</s>
<s>
A	O
two-socket	O
server	O
(	O
2	O
RU	O
)	O
will	O
have	O
128	O
threads	B-Operating_System
,	O
16	O
cores	O
,	O
and	O
a	O
65×	O
performance	O
improvement	O
over	O
UltraSPARC	O
III	O
.	O
</s>
<s>
Thus	O
,	O
a	O
single	O
4-way	O
SMP	B-Operating_System
server	O
will	O
support	O
256	O
concurrent	B-Operating_System
hardware	B-General_Concept
threads	I-General_Concept
.	O
</s>
<s>
In	O
April	O
2008	O
,	O
Sun	O
released	O
2-way	O
UltraSPARC	B-Device
T2	I-Device
Plus	I-Device
servers	O
,	O
the	O
SPARC	B-Application
Enterprise	I-Application
T5140	O
and	O
T5240	O
.	O
</s>
<s>
In	O
October	O
2008	O
,	O
Sun	O
released	O
4-way	O
UltraSPARC	B-Device
T2	I-Device
Plus	I-Device
SPARC	B-Application
Enterprise	I-Application
T5440	O
server	O
.	O
</s>
<s>
In	O
October	O
2006	O
,	O
Sun	O
disclosed	O
that	O
Niagara	B-General_Concept
3	O
will	O
be	O
built	O
with	O
a	O
45nm	O
process	O
.	O
</s>
<s>
The	O
Register	O
,	O
reported	O
in	O
June	O
2008	O
that	O
the	O
microprocessor	B-Architecture
will	O
have	O
16	O
cores	O
,	O
incorrectly	O
suggesting	O
each	O
core	O
would	O
have	O
16	O
threads	B-Operating_System
.	O
</s>
<s>
During	O
the	O
Hot	O
Chips	O
21	O
conference	O
Sun	O
revealed	O
the	O
chip	O
has	O
a	O
total	O
of	O
16	O
cores	O
and	O
128	O
threads	B-Operating_System
.	O
</s>
<s>
"	O
A	O
40nm	O
16-Core	O
128-Thread	O
CMT	O
SPARC	B-Architecture
SoC	O
Processor	O
"	O
.	O
</s>
<s>
The	O
T4	O
CPU	B-General_Concept
was	O
released	O
in	O
late	O
2011	O
.	O
</s>
<s>
The	O
new	O
T4	O
CPU	B-General_Concept
will	O
drop	O
from	O
16	O
cores	O
(	O
on	O
the	O
T3	O
)	O
back	O
to	O
8	O
cores	O
(	O
as	O
used	O
on	O
the	O
T1	O
,	O
T2	O
,	O
and	O
T2+	O
)	O
.	O
</s>
<s>
The	O
new	O
T4	O
core	O
design	O
(	O
named	O
"	O
S3	O
"	O
)	O
feature	O
improved	O
per-thread	O
performance	O
,	O
due	O
to	O
introduction	O
of	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
as	O
well	O
as	O
having	O
additional	O
improved	O
performance	O
for	O
single-threaded	B-Operating_System
programs	O
.	O
</s>
<s>
In	O
2010	O
,	O
Larry	O
Ellison	O
announced	O
that	O
Oracle	B-Application
will	O
offer	O
Oracle	B-Application
Linux	B-Application
on	O
the	O
UltraSPARC	O
platform	O
,	O
and	O
the	O
port	O
was	O
scheduled	O
to	O
be	O
available	O
in	O
the	O
T4	O
and	O
T5	O
timeframe	O
.	O
</s>
<s>
John	O
Fowler	O
,	O
Executive	O
Vice	O
President	O
Systems	O
Oracle	B-Application
,	O
in	O
Openworld	O
2014	O
said	O
Linux	B-Application
will	O
be	O
able	O
to	O
run	O
on	O
Sparc	B-Architecture
at	O
some	O
point	O
.	O
</s>
<s>
The	O
new	O
T5	O
CPU	B-General_Concept
features	O
128	O
threads	B-Operating_System
over	O
16	O
cores	O
and	O
is	O
manufactured	O
with	O
a	O
28	O
nanometer	O
technology	O
.	O
</s>
<s>
On	O
March	O
21	O
,	O
2006	O
,	O
Sun	O
made	O
the	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
processor	O
design	O
available	O
under	O
the	O
GNU	B-License
General	I-License
Public	I-License
License	I-License
via	O
the	O
OpenSPARC	B-Device
project	O
.	O
</s>
<s>
Verilog	B-Language
source	O
code	O
of	O
the	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
design	O
;	O
</s>
<s>
The	O
Solaris	B-Application
10	I-Application
OS	O
simulation	O
images	O
.	O
</s>
