<s>
The	O
UltraSPARC	O
IV	O
Jaguar	O
and	O
follow-up	O
UltraSPARC	B-General_Concept
IV+	I-General_Concept
Panther	O
are	O
microprocessors	B-Architecture
designed	O
by	O
Sun	O
Microsystems	O
and	O
manufactured	O
by	O
Texas	O
Instruments	O
.	O
</s>
<s>
They	O
are	O
the	O
fourth	O
generation	O
of	O
UltraSPARC	O
microprocessors	B-Architecture
,	O
and	O
implement	O
the	O
64-bit	O
SPARC	B-Architecture
V9	I-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
The	O
UltraSPARC	O
IV	O
was	O
originally	O
to	O
be	O
succeeded	O
by	O
the	O
UltraSPARC	O
V	O
Millennium	O
,	O
which	O
was	O
canceled	O
after	O
the	O
announcement	O
of	O
the	O
Niagara	B-General_Concept
,	O
now	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
microprocessor	B-Architecture
in	O
early	O
2004	O
.	O
</s>
<s>
It	O
was	O
instead	O
succeeded	O
by	O
the	O
Fujitsu-designed	O
SPARC64	B-Device
VI	I-Device
.	O
</s>
<s>
The	O
UltraSPARC	O
IV	O
was	O
developed	O
as	O
part	O
of	O
Sun	O
's	O
Throughput	O
Computing	O
initiative	O
,	O
which	O
included	O
the	O
UltraSPARC	O
V	O
Millennium	O
,	O
Gemini	O
and	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
Niagara	B-General_Concept
microprocessors	B-Architecture
.	O
</s>
<s>
Of	O
the	O
four	O
original	O
designs	O
in	O
the	O
initiative	O
,	O
two	O
reached	O
production	O
:	O
the	O
UltraSPARC	O
IV	O
and	O
the	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
.	O
</s>
<s>
Whereas	O
the	O
Millennium	O
and	O
Niagara	B-General_Concept
implemented	O
block	O
multithreading	O
-	O
also	O
known	O
as	O
coarse-grained	O
multithreading	O
,	O
the	O
UltraSPARC	O
IV	O
implemented	O
chip-multithreading	O
(	O
CMP	O
)	O
multiple	O
single-thread	O
cores	O
.	O
</s>
<s>
The	O
UltraSPARC	O
IV	O
was	O
the	O
first	O
multi-core	O
SPARC	B-Architecture
processor	O
,	O
released	O
in	O
March	O
,	O
2004	O
.	O
</s>
<s>
Internally	O
,	O
it	O
implements	O
two	O
modified	O
UltraSPARC	B-General_Concept
III	I-General_Concept
cores	O
,	O
and	O
its	O
physical	O
packaging	O
is	O
identical	O
to	O
the	O
UltraSPARC	B-General_Concept
III	I-General_Concept
with	O
the	O
exception	O
of	O
one	O
pin	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
III	I-General_Concept
cores	O
were	O
improved	O
in	O
a	O
variety	O
of	O
ways	O
.	O
</s>
<s>
The	O
floating-point	B-Algorithm
adder	O
implements	O
additional	O
hardware	O
to	O
handle	O
more	O
not	O
a	O
number	O
(	O
NaN	O
)	O
and	O
underflow	B-Algorithm
cases	O
to	O
avoid	O
exceptions	B-General_Concept
.	O
</s>
<s>
The	O
UltraSPARC	O
IV	O
contains	O
66	O
million	O
transistors	B-Application
and	O
measures	O
22.1mm	O
by	O
16.1mm	O
(	O
356mm2	O
)	O
.	O
</s>
<s>
It	O
was	O
fabricated	B-Architecture
by	O
Texas	O
Instruments	O
in	O
their	O
0.13μm	O
process	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
IV+	I-General_Concept
,	O
released	O
in	O
mid-2005	O
,	O
is	O
also	O
a	O
dual-core	O
design	O
,	O
featuring	O
enhanced	O
processor	O
cores	O
and	O
an	O
on-chip	O
L2	O
cache	O
.	O
</s>
<s>
It	O
is	O
fabricated	B-Architecture
on	O
a	O
90	O
nanometer	O
manufacturing	O
process	O
.	O
</s>
<s>
The	O
initial	O
speed	O
of	O
the	O
UltraSPARC	B-General_Concept
IV+	I-General_Concept
was	O
1.5GHz	O
,	O
0.3GHz	O
less	O
than	O
the	O
intended	O
1.8GHz	O
.	O
</s>
<s>
It	O
contains	O
295	O
million	O
transistors	B-Application
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
IV+	I-General_Concept
was	O
released	O
in	O
Sun	O
servers	O
in	O
September	O
2005	O
.	O
</s>
<s>
Sun	B-Architecture
Fire	I-Architecture
V490	O
,	O
V890	O
,	O
E2900	O
,	O
E4900	O
,	O
E6900	O
,	O
E20K	O
and	O
E25K	B-Device
systems	O
all	O
use	O
UltraSPARC	O
IV	O
and	O
IV+	O
processors	O
.	O
</s>
<s>
Servers	O
powered	O
by	O
the	O
UltraSPARC	B-General_Concept
IV+	I-General_Concept
processor	O
were	O
well	O
received	O
,	O
allowing	O
Sun	O
to	O
regain	O
revenue	O
lead	O
in	O
the	O
RISC/UNIX	O
server	O
market	O
in	O
2006	O
.	O
</s>
