<s>
The	O
UltraSPARC	B-General_Concept
III	I-General_Concept
,	O
code-named	O
"	O
Cheetah	O
"	O
,	O
is	O
a	O
microprocessor	O
that	O
implements	O
the	O
SPARC	B-Architecture
V9	I-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
developed	O
by	O
Sun	O
Microsystems	O
and	O
fabricated	O
by	O
Texas	O
Instruments	O
.	O
</s>
<s>
It	O
was	O
succeeded	O
by	O
the	O
UltraSPARC	B-General_Concept
IV	I-General_Concept
in	O
2004	O
.	O
</s>
<s>
When	O
presented	O
at	O
the	O
'	O
97	O
Microprocessor	O
Forum	O
,	O
the	O
probable	O
introduction	O
date	O
for	O
the	O
UltraSPARC	B-General_Concept
III	I-General_Concept
was	O
1999	O
,	O
and	O
it	O
would	O
have	O
competed	O
with	O
Digital	O
Equipment	O
Corporation	O
's	O
Alpha	B-General_Concept
21264	I-General_Concept
and	O
Intel	O
's	O
Itanium	B-General_Concept
(	O
Merced	O
)	O
.	O
</s>
<s>
Despite	O
being	O
late	O
,	O
it	O
was	O
awarded	O
the	O
Analysts	O
 '	O
Choice	O
Award	O
for	O
Best	O
Server/Workstation	O
Processor	O
of	O
2001	O
by	O
Microprocessor	O
Report	O
for	O
its	O
multiprocessing	B-Operating_System
features	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
III	I-General_Concept
is	O
an	O
in-order	B-General_Concept
superscalar	B-General_Concept
microprocessor	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
III	I-General_Concept
was	O
designed	O
for	O
shared	B-Operating_System
memory	I-Operating_System
multiprocessing	B-Operating_System
performance	O
,	O
and	O
it	O
has	O
several	O
features	O
that	O
aid	O
in	O
achieving	O
that	O
goal	O
:	O
an	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
and	O
a	O
dedicated	O
multiprocessing	B-Operating_System
bus	O
.	O
</s>
<s>
The	O
execution	O
resources	O
consisted	O
of	O
two	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
(	O
ALUs	O
)	O
,	O
a	O
load	O
and	O
store	O
unit	O
and	O
two	O
floating-point	O
units	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
III	I-General_Concept
has	O
split	O
primary	O
instruction	O
and	O
data	O
caches	O
.	O
</s>
<s>
Part	O
of	O
the	O
increased	O
bandwidth	O
to	O
the	O
cache	O
tags	O
is	O
used	O
by	O
cache	O
coherency	O
traffic	O
,	O
which	O
is	O
required	O
in	O
the	O
multiprocessor	B-Operating_System
systems	O
the	O
UltraSPARC	B-General_Concept
III	I-General_Concept
is	O
designed	O
to	O
be	O
used	O
in	O
.	O
</s>
<s>
The	O
external	O
interface	O
consists	O
of	O
a	O
128-bit	O
data	O
bus	O
and	O
a	O
43-bit	O
address	B-Architecture
bus	I-Architecture
operating	O
at	O
150MHz	O
.	O
</s>
<s>
The	O
UltraSPARC	O
has	O
an	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
and	O
implements	O
a	O
dedicated	O
128-bit	O
bus	O
operating	O
at	O
150MHz	O
to	O
access	O
up	O
to	O
4	O
GB	O
of	O
"	O
local	O
"	O
memory	O
.	O
</s>
<s>
The	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
is	O
used	O
to	O
reduce	O
latency	O
and	O
thus	O
improve	O
performance	O
,	O
unlike	O
some	O
other	O
UltraSPARC	O
microprocessors	O
that	O
use	O
the	O
feature	O
to	O
reduce	O
cost	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
III	I-General_Concept
consisted	O
of	O
16	O
million	O
transistors	O
,	O
of	O
which	O
75%	O
are	O
contained	O
in	O
the	O
caches	O
and	O
tags	O
.	O
</s>
<s>
It	O
was	O
packaged	O
in	O
a	O
1368-pad	O
land	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
LGA	O
)	O
package	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
III	I-General_Concept
Cu	O
,	O
code-named	O
"	O
Cheetah+	O
"	O
,	O
is	O
a	O
further	O
development	O
of	O
the	O
original	O
UltraSPARC	B-General_Concept
III	I-General_Concept
that	O
operated	O
at	O
higher	O
clock	O
frequencies	O
of	O
1002	O
to	O
1200MHz	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
IIIi	I-General_Concept
,	O
code	O
named	O
"	O
Jalapeño	O
"	O
,	O
is	O
a	O
derivative	O
of	O
the	O
UltraSPARC	B-General_Concept
III	I-General_Concept
for	O
workstations	O
and	O
low-end	O
(	O
one	O
to	O
four	O
processor	O
)	O
servers	O
introduced	O
in	O
2003	O
.	O
</s>
<s>
It	O
operates	O
at	O
1064	O
to	O
1593MHz	O
,	O
has	O
an	O
on-die	O
L2	O
cache	O
and	O
an	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
,	O
and	O
is	O
capable	O
of	O
four-way	O
multiprocessing	B-Operating_System
with	O
a	O
glue-less	O
system	O
bus	O
optimized	O
for	O
the	O
function	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
IIIi	I-General_Concept
has	O
a	O
unified	O
1MB	O
L2	O
cache	O
that	O
operates	O
at	O
half	O
of	O
the	O
microprocessor	O
's	O
clock	O
frequency	O
.	O
</s>
<s>
The	O
on-die	O
memory	B-General_Concept
controller	I-General_Concept
supports	O
256	O
MB	O
to	O
16GB	O
of	O
133MHz	O
DDR-I	O
SDRAM	O
.	O
</s>
<s>
The	O
microprocessor	O
was	O
designed	O
to	O
support	O
four-way	O
multiprocessing	B-Operating_System
.	O
</s>
<s>
The	O
UltraSPARC	O
IIIi+	O
,	O
code-named	O
"	O
Serrano	O
"	O
,	O
was	O
a	O
further	O
development	O
of	O
the	O
UltraSPARC	B-General_Concept
IIIi	I-General_Concept
.	O
</s>
<s>
It	O
was	O
scheduled	O
for	O
introduction	O
in	O
the	O
second	O
half	O
of	O
2005	O
,	O
but	O
was	O
cancelled	O
in	O
the	O
same	O
year	O
in	O
favor	O
of	O
the	O
UltraSPARC	B-General_Concept
IV+	I-General_Concept
,	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
and	O
UltraSPARC	B-Device
T2	I-Device
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
III	I-General_Concept
family	O
or	O
processors	O
was	O
succeeded	O
by	O
the	O
UltraSPARC	B-General_Concept
IV	I-General_Concept
series	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
IV	I-General_Concept
combined	O
two	O
UltraSPARC	B-General_Concept
III	I-General_Concept
cores	O
onto	O
a	O
single	O
piece	O
of	O
silicon	O
and	O
offered	O
increased	O
clock	O
rates	O
.	O
</s>
<s>
Some	O
systems	O
which	O
used	O
UltraSPARC	B-General_Concept
III	I-General_Concept
processors	O
could	O
accept	O
UltraSPARC	B-General_Concept
IV	I-General_Concept
CPU	O
board	O
upgrades	O
.	O
</s>
