<s>
The	O
UltraSPARC	B-General_Concept
II	I-General_Concept
,	O
code-named	O
"	O
Blackbird	O
"	O
,	O
is	O
a	O
microprocessor	B-Architecture
implementation	O
of	O
the	O
SPARC	B-Architecture
V9	I-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
developed	O
by	O
Sun	O
Microsystems	O
.	O
</s>
<s>
Introduced	O
in	O
1997	O
,	O
it	O
was	O
further	O
development	O
of	O
the	O
UltraSPARC	B-General_Concept
operating	O
at	O
higher	O
clock	O
frequencies	O
of	O
250MHz	O
,	O
eventually	O
reaching	O
650MHz	O
.	O
</s>
<s>
In	O
1999	O
,	O
the	O
UltraSPARC	B-General_Concept
II	I-General_Concept
was	O
ported	O
to	O
a	O
0.25μm	O
process	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
II	I-General_Concept
was	O
the	O
basis	O
for	O
four	O
derivatives	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
IIi	I-General_Concept
"	O
Sabre	O
"	O
featuring	O
on-chip	O
PCI	O
controller	O
was	O
a	O
low-cost	O
version	O
introduced	O
in	O
1997	O
that	O
operated	O
at	O
270	O
to	O
360MHz	O
.	O
</s>
<s>
In	O
1998	O
,	O
a	O
version	O
code-named	O
Sapphire-Red	O
,	O
was	O
fabricated	O
in	O
a	O
0.25μm	O
process	O
,	O
enabling	O
the	O
microprocessor	B-Architecture
to	O
operate	O
at	O
333	O
to	O
480MHz	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
IIe	I-General_Concept
"	O
Hummingbird	O
"	O
was	O
an	O
embedded	O
version	O
introduced	O
in	O
2000	O
that	O
operated	O
at	O
400	O
to	O
500MHz	O
,	O
fabricated	O
in	O
a	O
0.18μm	O
process	O
with	O
aluminium	O
interconnects	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
IIe+	I-General_Concept
or	O
IIi	O
was	O
introduced	O
in	O
2002	O
.	O
</s>
<s>
The	O
Gemini	O
was	O
the	O
first	O
attempt	O
by	O
Sun	O
to	O
produce	O
a	O
multithreaded	O
microprocessor	B-Architecture
.	O
</s>
<s>
It	O
had	O
taped	O
out	O
,	O
but	O
was	O
cancelled	O
before	O
it	O
was	O
introduced	O
after	O
the	O
announcement	O
of	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
Niagara	B-General_Concept
microprocessor	B-Architecture
in	O
early	O
2004	O
.	O
</s>
<s>
It	O
consisted	O
of	O
two	O
UltraSPARC	B-General_Concept
II	I-General_Concept
cores	O
and	O
an	O
on-die	O
L2	O
cache	O
on	O
a	O
single	O
chip	O
.	O
</s>
<s>
The	O
DAC	O
2004	O
abstracts	O
described	O
the	O
dual-core	O
UltraSPARC	B-General_Concept
II	I-General_Concept
processor	O
in	O
Session	O
40	O
.	O
</s>
<s>
The	O
"	O
Dual-Core	O
UltraSPARC	B-General_Concept
(	O
2003	O
)	O
"	O
was	O
based	O
upon	O
the	O
UltraSPARC	B-General_Concept
II	I-General_Concept
microarchitecture	O
and	O
featured	O
:	O
DDR-1	O
memory	O
controller	O
,	O
JBUS	O
interface	O
,	O
parity	O
protected	O
L1	O
cache	O
,	O
ECC	O
protected	O
dual	O
512KB	O
on-chip	O
L2	O
cache	O
,	O
1.2GHz	O
clock	O
frequency	O
,	O
80	O
million	O
transistors	O
,	O
206	O
mm	O
die	O
size	O
,	O
and	O
dissipated	O
23	O
watts	O
of	O
power	O
.	O
</s>
