<s>
The	O
UltraSPARC	B-General_Concept
is	O
a	O
microprocessor	B-Architecture
developed	O
by	O
Sun	O
Microsystems	O
and	O
fabricated	O
by	O
Texas	O
Instruments	O
,	O
introduced	O
in	O
mid-1995	O
.	O
</s>
<s>
It	O
is	O
the	O
first	O
microprocessor	B-Architecture
from	O
Sun	O
to	O
implement	O
the	O
64-bit	O
SPARC	B-Architecture
V9	I-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
is	O
a	O
four-issue	O
superscalar	B-General_Concept
microprocessor	B-Architecture
that	O
executes	O
instructions	O
in	O
in-order	O
.	O
</s>
<s>
It	O
has	O
a	O
nine-stage	O
integer	O
pipeline	B-General_Concept
.	O
</s>
<s>
The	O
execution	O
units	O
were	O
simplified	O
relative	O
to	O
the	O
SuperSPARC	B-Device
to	O
achieve	O
higher	O
clock	O
frequencies	O
-	O
an	O
example	O
of	O
a	O
simplification	O
is	O
that	O
the	O
ALUs	O
were	O
not	O
cascaded	O
,	O
unlike	O
the	O
SuperSPARC	B-Device
,	O
to	O
avoid	O
restricting	O
clock	O
frequency	O
.	O
</s>
<s>
The	O
integer	O
register	B-General_Concept
file	I-General_Concept
has	O
32	O
64-bit	O
entries	O
.	O
</s>
<s>
As	O
the	O
SPARC	B-Architecture
ISA	O
uses	O
register	B-General_Concept
windows	I-General_Concept
,	O
of	O
which	O
the	O
UltraSPARC	B-General_Concept
has	O
eight	O
,	O
the	O
actual	O
number	O
of	O
registers	O
is	O
144	O
.	O
</s>
<s>
The	O
register	B-General_Concept
file	I-General_Concept
has	O
seven	O
read	O
and	O
three	O
write	O
ports	O
.	O
</s>
<s>
The	O
integer	O
register	B-General_Concept
file	I-General_Concept
provides	O
registers	O
to	O
two	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
and	O
the	O
load/store	O
unit	O
.	O
</s>
<s>
Two	O
units	O
are	O
for	O
executing	O
SIMD	O
instructions	O
defined	O
by	O
the	O
Visual	B-General_Concept
Instruction	I-General_Concept
Set	I-General_Concept
(	O
VIS	O
)	O
.	O
</s>
<s>
The	O
floating-point	O
register	B-General_Concept
file	I-General_Concept
contains	O
thirty-two	O
64-bit	O
registers	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
has	O
two	O
levels	O
of	O
cache	O
,	O
primary	O
and	O
secondary	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
required	O
a	O
mandatory	O
external	O
secondary	O
cache	O
.	O
</s>
<s>
The	O
external	O
cache	O
is	O
implemented	O
with	O
synchronous	O
SRAMs	O
clocked	O
at	O
the	O
same	O
frequency	O
as	O
the	O
microprocessor	B-Architecture
,	O
as	O
ratios	O
were	O
not	O
supported	O
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
was	O
not	O
fabricated	O
in	O
a	O
BiCMOS	B-General_Concept
process	O
as	O
Texas	O
Instruments	O
claimed	O
it	O
did	O
not	O
scale	O
well	O
to	O
0.5	O
μm	O
processes	O
and	O
offered	O
little	O
performance	O
improvement	O
.	O
</s>
<s>
The	O
process	O
was	O
perfected	O
on	O
TI	O
's	O
MVP	O
digital	B-Architecture
signal	I-Architecture
processor	I-Architecture
(	O
DSP	O
)	O
with	O
some	O
features	O
missing	O
such	O
as	O
three	O
levels	O
of	O
metal	O
instead	O
of	O
four	O
and	O
a	O
0.55	O
feature	O
size	O
,	O
before	O
it	O
was	O
used	O
to	O
fabricate	O
the	O
UltraSPARC	B-General_Concept
to	O
avoid	O
a	O
repeat	O
of	O
the	O
fabrication	O
problems	O
encountered	O
with	O
SuperSPARC	B-Device
.	O
</s>
<s>
The	O
UltraSPARC	B-General_Concept
is	O
packaged	O
in	O
a	O
521-contact	O
plastic	B-Algorithm
ball	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
PBGA	B-Algorithm
)	O
.	O
</s>
