<s>
FIELDATA	B-Device
–	O
UNIVAC	O
6-bit	O
code	O
variant	O
(	O
no	O
lower	O
case	O
characters	O
)	O
six	O
characters	O
in	O
each	O
36-bit	O
word	O
.	O
</s>
<s>
(	O
FIELDATA	B-Device
was	O
originally	O
a	O
seven-bit	O
code	O
of	O
which	O
only	O
64	O
code	O
positions	O
(	O
occupying	O
six	O
bits	O
)	O
were	O
formally	O
defined	O
.	O
)	O
</s>
<s>
f	O
(	O
6	O
bits	O
)	O
-	O
function	O
designator	O
(	O
opcode	B-Language
)	O
,	O
</s>
<s>
j	O
(	O
4	O
bits	O
)	O
-	O
partial	O
word	O
designator	O
,	O
J-register	O
designator	O
,	O
or	O
minor	O
function	O
designator	O
,	O
</s>
<s>
a	O
(	O
4	O
bits	O
)	O
-	O
register	B-General_Concept
(	O
A	O
,	O
X	O
,	O
or	O
R	O
)	O
designator	O
or	O
I/O	B-General_Concept
designator	O
,	O
</s>
<s>
x	O
(	O
4	O
bits	O
)	O
-	O
index	B-General_Concept
register	I-General_Concept
(	O
X	O
)	O
designator	O
,	O
</s>
<s>
h	O
(	O
1	O
bit	O
)	O
-	O
index	B-General_Concept
register	I-General_Concept
increment	O
designator	O
,	O
</s>
<s>
Address	B-General_Concept
Register	I-General_Concept
Contents	O
000	O
Unused	O
Unused	O
001	O
X1	O
Increment	O
Modifier	O
...	O
...	O
Increment	O
Modifier	O
013	O
X11	O
Increment	O
Modifier	O
014	O
X12/A0	O
Overlap	O
(	O
X	O
or	O
A	O
)	O
...	O
...	O
</s>
<s>
The	O
128	O
registers	B-General_Concept
of	O
the	O
high-speed	O
"	O
general	O
register	B-General_Concept
stack	O
"	O
(	O
"	O
integrated	O
circuit	O
registers	B-General_Concept
"	O
on	O
the	O
UNIVAC	O
1108	O
and	O
UNIVAC	O
1106	O
models	O
)	O
,	O
map	O
to	O
the	O
current	O
data	O
space	O
in	O
main	O
storage	O
starting	O
at	O
memory	O
address	O
zero	O
.	O
</s>
<s>
These	O
registers	B-General_Concept
include	O
both	O
user	O
and	O
executive	O
copies	O
of	O
the	O
A	O
,	O
X	O
,	O
R	O
,	O
and	O
J	O
registers	B-General_Concept
and	O
many	O
special	O
function	O
executive	O
registers	B-General_Concept
.	O
</s>
<s>
The	O
table	O
on	O
the	O
right	O
shows	O
the	O
addresses	O
(	O
in	O
octal	O
)	O
of	O
the	O
user	O
registers	B-General_Concept
.	O
</s>
<s>
There	O
are	O
15	O
index	B-General_Concept
registers	I-General_Concept
(	O
X1	O
...	O
X15	O
)	O
,	O
16	O
accumulators	B-General_Concept
(	O
A0	O
...	O
A15	O
)	O
,	O
and	O
15	O
special	O
function	O
user	O
registers	B-General_Concept
(	O
R1	O
..	O
R15	O
)	O
.	O
</s>
<s>
The	O
4	O
J	O
registers	B-General_Concept
and	O
3	O
"	O
staging	O
registers	B-General_Concept
"	O
are	O
uses	O
of	O
some	O
of	O
the	O
special	O
function	O
R	O
registers	B-General_Concept
.	O
</s>
<s>
One	O
interesting	O
feature	O
is	O
that	O
the	O
last	O
four	O
index	B-General_Concept
registers	I-General_Concept
(	O
X12	O
...	O
X15	O
)	O
and	O
the	O
first	O
four	O
accumulators	B-General_Concept
(	O
A0	O
...	O
A3	O
)	O
overlap	O
,	O
allowing	O
data	O
to	O
be	O
interpreted	O
either	O
way	O
in	O
these	O
registers	B-General_Concept
.	O
</s>
<s>
This	O
also	O
results	O
in	O
four	O
unassigned	O
accumulators	B-General_Concept
(	O
A15+1	O
...	O
A15+4	O
)	O
that	O
can	O
only	O
be	O
accessed	O
by	O
their	O
memory	O
address	O
(	O
double	O
word	O
instructions	O
on	O
A15	O
do	O
operate	O
on	O
A15+1	O
)	O
.	O
</s>
<s>
They	O
all	O
used	O
vacuum	O
tubes	O
and	O
many	O
used	O
drum	B-General_Concept
memory	I-General_Concept
as	O
their	O
main	O
memory	O
.	O
</s>
<s>
The	O
UNIVAC	B-Device
1101	I-Device
,	O
or	O
ERA	B-Device
1101	I-Device
,	O
was	O
a	O
computer	O
system	O
designed	O
by	O
ERA	O
and	O
built	O
by	O
the	O
Remington	O
Rand	O
corporation	O
in	O
the	O
1950s	O
.	O
</s>
<s>
The	O
UNIVAC	B-Device
1102	I-Device
or	O
ERA	B-Device
1102	I-Device
was	O
designed	O
by	O
Engineering	O
Research	O
Associates	O
for	O
the	O
United	O
States	O
Air	O
Force	O
.	O
</s>
<s>
The	O
36-bit	O
UNIVAC	B-Device
1103	I-Device
was	O
introduced	O
in	O
1953	O
and	O
an	O
upgraded	O
version	O
(	O
UNIVAC	O
1103A	O
)	O
was	O
released	O
in	O
1956	O
.	O
</s>
<s>
This	O
was	O
the	O
first	O
commercial	O
computer	O
to	O
use	O
core	B-General_Concept
memory	I-General_Concept
instead	O
of	O
the	O
Williams	B-General_Concept
tube	I-General_Concept
.	O
</s>
<s>
The	O
UNIVAC	B-Device
1105	I-Device
was	O
the	O
successor	O
to	O
the	O
1103A	O
,	O
and	O
was	O
introduced	O
in	O
1958	O
.	O
</s>
<s>
However	O
,	O
by	O
the	O
time	O
the	O
BOMARC	O
was	O
deployed	O
in	O
the	O
1960s	O
,	O
a	O
more	O
modern	O
computer	O
(	O
a	O
version	O
of	O
the	O
AN/USQ	B-Device
-20	I-Device
,	O
designated	O
the	O
G-40	O
)	O
had	O
replaced	O
the	O
UNIVAC	O
1104	O
.	O
</s>
<s>
Early	O
machines	O
used	O
core	B-General_Concept
memory	I-General_Concept
(	O
the	O
1110	O
used	O
plated	B-General_Concept
wire	I-General_Concept
memory	I-General_Concept
)	O
until	O
that	O
was	O
replaced	O
with	O
semiconductor	B-Architecture
memory	I-Architecture
in	O
1975	O
.	O
</s>
<s>
It	O
was	O
also	O
known	O
as	O
the	O
Thin-Film	O
Computer	O
because	O
of	O
its	O
use	O
of	O
thin-film	B-General_Concept
memory	I-General_Concept
for	O
its	O
register	B-General_Concept
storage	I-General_Concept
.	O
</s>
<s>
It	O
represented	O
a	O
marked	O
change	O
of	O
architecture	O
:	O
unlike	O
previous	O
models	O
,	O
it	O
was	O
not	O
a	O
strict	O
two-address	O
machine	O
:	O
it	O
was	O
a	O
single-address	O
machine	O
with	O
up	O
to	O
65,536	O
words	O
of	O
36-bit	O
core	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
The	O
machine	O
's	O
registers	B-General_Concept
were	O
stored	O
in	O
128	O
words	O
of	O
thin-film	B-General_Concept
memory	I-General_Concept
,	O
a	O
faster	O
form	O
of	O
magnetic	O
storage	O
.	O
</s>
<s>
With	O
six	O
cycles	O
of	O
thin-film	B-General_Concept
memory	I-General_Concept
per	O
4	O
microsecond	O
main	O
memory	O
cycle	O
,	O
address	O
indexing	O
was	O
performed	O
without	O
a	O
cycle	O
time	O
penalty	O
.	O
</s>
<s>
The	O
core	B-General_Concept
memory	I-General_Concept
was	O
available	O
in	O
16,384	O
36-bit	O
words	O
in	O
a	O
single	O
bank	O
;	O
or	O
in	O
increments	O
of	O
16,384	O
words	O
to	O
a	O
maximum	O
of	O
65,536	O
words	O
in	O
two	O
separately	O
accessed	O
banks	O
.	O
</s>
<s>
The	O
128-word	O
thin-film	B-General_Concept
memory	I-General_Concept
general	O
register	B-General_Concept
stack	O
(	O
16	O
each	O
arithmetic	O
,	O
index	O
,	O
and	O
repeat	O
with	O
a	O
few	O
in	O
common	O
)	O
had	O
a	O
300-nanosecond	O
access	O
time	O
with	O
a	O
complete	O
cycle	O
time	O
of	O
600	O
nanoseconds	O
.	O
</s>
<s>
Six	O
cycles	O
of	O
thin-film	B-General_Concept
memory	I-General_Concept
per	O
core	B-General_Concept
memory	I-General_Concept
cycle	O
and	O
fast	O
adder	O
circuitry	O
permitted	O
memory	O
address	O
indexing	O
within	O
the	O
current	O
instruction	O
core	B-General_Concept
memory	I-General_Concept
cycle	O
and	O
also	O
modification	O
of	O
the	O
index	O
value	O
(	O
the	O
signed	O
upper	O
18	O
bits	O
were	O
added	O
to	O
the	O
lower	O
18	O
bits	O
)	O
in	O
the	O
specified	O
index	B-General_Concept
register	I-General_Concept
(	O
16	O
were	O
available	O
)	O
.	O
</s>
<s>
The	O
16	O
input/output	B-General_Concept
(	O
I/O	B-General_Concept
)	O
channels	O
also	O
used	O
thin-film	B-General_Concept
memory	I-General_Concept
locations	O
for	O
direct-to-memory	O
I/O	B-General_Concept
memory	O
location	O
registers	B-General_Concept
.	O
</s>
<s>
Programs	O
could	O
not	O
be	O
executed	O
from	O
unused	O
thin-film	B-General_Concept
memory	I-General_Concept
locations	O
.	O
</s>
<s>
The	O
FH880	O
drum	B-General_Concept
memory	I-General_Concept
unit	O
was	O
also	O
supported	O
as	O
a	O
spooling	O
and	O
file-storage	O
media	O
.	O
</s>
<s>
Univac	O
provided	O
a	O
batch	O
operating	O
system	O
,	O
EXEC	B-Application
I	I-Application
.	O
</s>
<s>
Computer	O
Sciences	O
Corporation	O
was	O
contracted	O
to	O
provide	O
a	O
powerful	O
optimizing	O
Fortran	B-Application
IV	O
compiler	B-Language
,	O
an	O
assembler	B-Application
named	O
SLEUTH	O
with	O
sophisticated	O
macro	O
capabilities	O
,	O
and	O
a	O
very	O
flexible	O
linking	B-Application
loader	I-Application
.	O
</s>
<s>
Integrated	O
circuits	O
replaced	O
the	O
thin-film	B-General_Concept
memory	I-General_Concept
that	O
the	O
UNIVAC	O
1107	O
used	O
for	O
register	B-General_Concept
storage	I-General_Concept
.	O
</s>
<s>
In	O
addition	O
to	O
faster	O
components	O
,	O
two	O
significant	O
design	O
improvements	O
were	O
incorporated	O
:	O
base	O
registers	B-General_Concept
and	O
additional	O
hardware	O
instructions	O
.	O
</s>
<s>
The	O
two	O
18-bit	O
base	O
registers	B-General_Concept
(	O
one	O
for	O
instruction	O
storage	O
and	O
one	O
for	O
data	O
storage	O
)	O
permitted	O
dynamic	O
relocation	O
:	O
as	O
a	O
program	O
got	O
swapped	O
in	O
and	O
out	O
of	O
main	O
memory	O
,	O
its	O
instructions	O
and	O
data	O
could	O
be	O
placed	O
anywhere	O
each	O
time	O
it	O
got	O
reloaded	O
.	O
</s>
<s>
To	O
support	O
multiprogramming	O
,	O
the	O
1108	O
had	O
memory	O
protection	O
using	O
two	O
base	O
and	O
limit	O
registers	B-General_Concept
,	O
with	O
512-word	O
resolution	O
.	O
</s>
<s>
The	O
1108	O
also	O
introduced	O
the	O
Processor	O
State	O
Register	B-General_Concept
,	O
or	O
PSR	O
.	O
</s>
<s>
In	O
addition	O
to	O
controlling	O
the	O
Base	O
Registers	B-General_Concept
,	O
it	O
included	O
various	O
control	O
"	O
bits	O
"	O
that	O
enabled	O
the	O
various	O
Storage	O
Protection	O
features	O
,	O
allowed	O
selection	O
of	O
either	O
the	O
User	O
or	O
Exec	O
set	O
of	O
A	O
,	O
X	O
&	O
R	O
registers	B-General_Concept
,	O
and	O
enabled	O
"	O
Guard	O
Mode	O
"	O
for	O
user	O
programs	O
.	O
</s>
<s>
The	O
processor	O
could	O
have	O
up	O
to	O
16	O
input/output	B-General_Concept
channels	O
for	O
peripherals	O
.	O
</s>
<s>
The	O
1108	O
CPU	O
was	O
,	O
with	O
the	O
exception	O
of	O
the	O
128-word	O
(	O
200	O
octal	O
)	O
ICR	O
(	O
Integrated	O
Control	O
Register	B-General_Concept
)	O
stack	O
,	O
entirely	O
implemented	O
via	O
discrete	O
component	O
logic	O
cards	O
,	O
each	O
with	O
a	O
55-pin	O
high	O
density	O
connector	O
,	O
which	O
interfaced	O
to	O
a	O
machine	O
wire	O
wrapped	O
backplane	O
.	O
</s>
<s>
Additional	O
hand	O
applied	O
twisted	O
pair	O
wiring	O
was	O
utilized	O
to	O
implement	O
backplane	O
connections	O
with	O
sensitive	O
timing	O
,	O
connections	O
between	O
machine	O
wire	O
wrapped	O
backplanes	O
,	O
and	O
connections	O
to	O
the	O
I/O	B-General_Concept
channel	O
connector	O
panel	O
in	O
the	O
lower	O
section	O
of	O
the	O
CPU	O
Cabinet	O
.	O
</s>
<s>
The	O
ICR	O
(	O
Integrated	O
Control	O
Register	B-General_Concept
)	O
stack	O
was	O
implemented	O
with	O
"	O
new	O
"	O
integrated	O
circuit	O
technology	O
,	O
replacing	O
the	O
thin	O
film	O
registers	B-General_Concept
on	O
the	O
1107	O
.	O
</s>
<s>
The	O
core	B-General_Concept
memory	I-General_Concept
was	O
contained	O
in	O
a	O
one	O
or	O
more	O
separate	O
cabinet(s )	O
,	O
and	O
consisted	O
of	O
two	O
separate	O
32K	O
modules	O
,	O
for	O
a	O
total	O
capacity	O
of	O
64K	O
38-bit	O
words	O
(	O
36-bits	O
data	O
and	O
a	O
Parity	O
Bit	O
for	O
each	O
18-bit	O
half-word	O
)	O
.	O
</s>
<s>
The	O
basic	O
cycle	O
time	O
of	O
the	O
core	B-General_Concept
memory	I-General_Concept
was	O
750	O
ns	O
,	O
and	O
the	O
supporting	O
circuitry	O
was	O
implemented	O
with	O
the	O
same	O
circuit	O
card/backplane	O
technology	O
as	O
the	O
1108	O
CPU	O
.	O
</s>
<s>
Just	O
as	O
the	O
first	O
UNIVAC	O
1108	O
systems	O
were	O
being	O
delivered	O
in	O
1965	O
,	O
Sperry	O
Rand	O
announced	O
the	O
UNIVAC	O
1108	O
II	O
(	O
also	O
known	O
as	O
the	O
UNIVAC	O
1108A	O
)	O
which	O
had	O
support	O
for	O
multiprocessing	O
:	O
up	O
to	O
three	O
CPUs	B-General_Concept
,	O
four	O
memory	O
banks	O
totaling	O
262,144	O
words	O
,	O
and	O
two	O
independent	O
programmable	O
input/output	B-General_Concept
controllers	O
(	O
IOCs	O
)	O
.	O
</s>
<s>
With	O
everything	O
busy	O
,	O
five	O
activities	O
could	O
be	O
going	O
on	O
at	O
the	O
same	O
moment	O
:	O
three	O
programs	O
running	O
in	O
the	O
CPUs	B-General_Concept
and	O
two	O
input/output	B-General_Concept
processes	O
in	O
the	O
IOCs	O
.	O
</s>
<s>
One	O
more	O
instruction	O
was	O
incorporated	O
:	O
test-and-set	B-Operating_System
,	O
to	O
provide	O
for	O
synchronization	O
between	O
the	O
CPUs	B-General_Concept
.	O
</s>
<s>
The	O
1108	O
II	O
,	O
or	O
1108A	O
,	O
was	O
the	O
first	O
multiprocessor	O
machine	O
in	O
the	O
series	O
,	O
capable	O
of	O
expansion	O
to	O
three	O
CPUs	B-General_Concept
and	O
two	O
IOCs	O
(	O
Input/Output	B-General_Concept
Control	O
Units	O
)	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
was	O
very	O
similar	O
to	O
that	O
of	O
the	O
1107	O
,	O
but	O
included	O
some	O
additional	O
instructions	O
,	O
including	O
the	O
"	O
Test	B-Operating_System
and	I-Operating_System
Set	I-Operating_System
"	O
instruction	O
for	O
multiprocessor	O
synchronization	O
.	O
</s>
<s>
Some	O
models	O
of	O
the	O
1108	O
implemented	O
the	O
ability	O
to	O
divide	O
words	O
into	O
four	O
nine-bit	O
bytes	O
,	O
allowing	O
use	O
of	O
ASCII	B-Protocol
characters	I-Protocol
.	O
</s>
<s>
Most	O
1108A	O
configurations	O
included	O
one	O
or	O
two	O
CPUs	B-General_Concept
,	O
each	O
with	O
eight	O
or	O
(	O
optionally	O
)	O
16	O
36-bit	O
parallel	O
I/O	B-General_Concept
channels	O
,	O
and	O
two	O
or	O
three	O
64K	O
core	B-General_Concept
memory	I-General_Concept
cabinets	O
.	O
</s>
<s>
Three	O
CPU	O
systems	O
,	O
with	O
four	O
core	B-General_Concept
memory	I-General_Concept
cabinets	O
were	O
the	O
exception	O
due	O
to	O
cost	O
considerations	O
.	O
</s>
<s>
The	O
IOC	O
was	O
a	O
separate	O
cabinet	O
that	O
contained	O
8	O
or	O
(	O
optionally	O
)	O
16	O
additional	O
I/O	B-General_Concept
channels	O
to	O
support	O
configurations	O
with	O
very	O
large	O
Mass	O
Storage	O
requirements	O
.	O
</s>
<s>
It	O
was	O
a	O
custom-built	O
,	O
stand-alone	O
math	B-General_Concept
coprocessor	I-General_Concept
to	O
the	O
1108A	O
system	O
.	O
</s>
<s>
It	O
was	O
capable	O
of	O
directly	O
addressing	O
and	O
interfacing	O
to	O
the	O
four	O
65K	O
core	B-General_Concept
memory	I-General_Concept
cabinets	O
of	O
two	O
independent	O
1108A	O
systems	O
.	O
</s>
<s>
At	O
a	O
simplified	O
level	O
,	O
one	O
of	O
the	O
1108A	O
CPUs	B-General_Concept
would	O
move	O
data	O
arrays	O
into	O
core	B-General_Concept
memory	I-General_Concept
,	O
and	O
send	O
the	O
UAP	O
an	O
instruction	B-Language
packet	I-Language
,	O
containing	O
the	O
function	O
to	O
be	O
executed	O
,	O
and	O
the	O
memory	O
address(es )	O
of	O
the	O
data	O
array(s )	O
,	O
across	O
a	O
standard	O
I/O	B-General_Concept
channel	O
.	O
</s>
<s>
The	O
UAP	O
would	O
then	O
perform	O
the	O
operation	O
,	O
totally	O
independent	O
of	O
the	O
CPU(s )	O
,	O
and	O
,	O
when	O
the	O
operation	O
was	O
complete	O
,	O
"	O
interrupt	O
"	O
the	O
originating	O
CPU	O
via	O
the	O
I/O	B-General_Concept
channel	O
.	O
</s>
<s>
When	O
Sperry	O
Rand	O
replaced	O
the	O
core	B-General_Concept
memory	I-General_Concept
with	O
semiconductor	B-Architecture
memory	I-Architecture
,	O
the	O
same	O
machine	O
was	O
released	O
as	O
the	O
UNIVAC	O
1100/20	O
.	O
</s>
<s>
In	O
this	O
new	O
naming	O
convention	O
,	O
the	O
final	O
digit	O
represented	O
the	O
number	O
of	O
CPUs	B-General_Concept
(	O
e.g.	O
,	O
1100/22	O
was	O
a	O
system	O
with	O
two	O
CPUs	B-General_Concept
)	O
in	O
the	O
system	O
.	O
</s>
<s>
The	O
operating	O
systems	O
were	O
batch	O
oriented	O
,	O
with	O
FORTRAN	B-Application
and	O
(	O
to	O
a	O
much	O
lesser	O
extent	O
)	O
ALGOL	B-Language
being	O
the	O
most	O
commonly	O
used	O
languages	O
.	O
</s>
<s>
As	O
the	O
market	O
for	O
commercial	O
computing	O
became	O
more	O
mature	O
,	O
these	O
operating	O
systems	O
were	O
no	O
longer	O
able	O
to	O
meet	O
the	O
growing	O
demand	O
for	O
business	O
computing	O
,	O
where	O
applications	O
were	O
commonly	O
written	O
in	O
COBOL	B-Application
.	O
</s>
<s>
utilizing	O
the	O
entire	O
CPU	O
and	O
core	B-General_Concept
memory	I-General_Concept
)	O
,	O
business	O
applications	O
,	O
typically	O
written	O
in	O
COBOL	B-Application
,	O
were	O
almost	O
always	O
"	O
I/O	B-General_Concept
bound	O
"	O
(	O
i.e.	O
</s>
<s>
waiting	O
for	O
I/O	B-General_Concept
operations	I-General_Concept
to	O
complete	O
)	O
.	O
</s>
<s>
Instrumentation	O
of	O
the	O
EXEC	O
8	O
operating	O
system	O
showed	O
that	O
,	O
in	O
a	O
1108A	O
multiprocessor	O
configuration	O
,	O
the	O
CPU(s )	O
were	O
often	O
in	O
the	O
"	O
idle	B-Algorithm
loop	I-Algorithm
"	O
as	O
much	O
as	O
50%	O
of	O
the	O
time	O
(	O
see	O
note	O
below	O
)	O
.	O
</s>
<s>
The	O
UNIVAC	O
1106	O
was	O
introduced	O
in	O
December	O
1969	O
and	O
was	O
absolutely	O
identical	O
to	O
the	O
UNIVAC	O
1108	O
,	O
both	O
physically	O
and	O
in	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Like	O
the	O
1108	O
,	O
it	O
was	O
multiprocessor	O
capable	O
,	O
though	O
it	O
appears	O
that	O
it	O
was	O
never	O
supplied	O
with	O
more	O
than	O
two	O
CPUs	B-General_Concept
,	O
and	O
did	O
not	O
support	O
IOCs	O
.	O
</s>
<s>
This	O
meant	O
that	O
only	O
three	O
I/O	B-General_Concept
channels	O
were	O
available	O
for	O
peripheral	O
subsystems	O
,	O
as	O
channel	O
15	O
(	O
the	O
highest-numbered	O
channel	O
)	O
was	O
always	O
,	O
in	O
both	O
1106	O
and	O
1108	O
systems	O
,	O
dedicated	O
to	O
the	O
operator	O
's	O
console	O
.	O
</s>
<s>
When	O
Sperry	O
Rand	O
replaced	O
the	O
core	B-General_Concept
memory	I-General_Concept
with	O
semiconductor	B-Architecture
memory	I-Architecture
,	O
the	O
same	O
machine	O
was	O
released	O
as	O
the	O
UNIVAC	O
1100/10	O
.	O
</s>
<s>
Note	O
:	O
EXEC	O
8	O
idle	B-Algorithm
loop	I-Algorithm
–	O
the	O
"	O
idle	B-Algorithm
loop	I-Algorithm
"	O
was	O
entered	O
when	O
a	O
CPU	O
had	O
no	O
available	O
task	O
to	O
execute	O
(	O
typically	O
when	O
waiting	O
for	O
an	O
I/O	B-General_Concept
operation	I-General_Concept
to	O
complete	O
)	O
.	O
</s>
<s>
A	O
simplified	O
description	O
is	O
that	O
the	O
CPU	O
executed	O
a	O
block	O
transfer	O
(	O
op	B-Language
code	I-Language
022	O
)	O
of	O
the	O
ICR	O
stack	O
(	O
the	O
first	O
0200	O
memory	O
addresses	O
)	O
back	O
to	O
the	O
same	O
addresses	O
.	O
</s>
<s>
Since	O
the	O
ICR	O
stack	O
was	O
contained	O
in	O
the	O
CPU	O
,	O
this	O
minimized	O
use	O
of	O
core	B-General_Concept
memory	I-General_Concept
cycles	O
,	O
freeing	O
them	O
up	O
for	O
active	O
CPUs	B-General_Concept
.	O
</s>
<s>
The	O
UNIVAC	O
1110	O
had	O
enhanced	O
multiprocessing	O
support	O
:	O
sixteen-way	O
memory	O
access	O
allowed	O
up	O
to	O
six	O
CAUs	O
(	O
Command	O
Arithmetic	O
Unit	O
,	O
the	O
new	O
name	O
for	O
CPU	O
and	O
so	O
called	O
because	O
the	O
CAU	O
no	O
longer	O
had	O
any	O
I/O	B-General_Concept
capability	O
)	O
and	O
four	O
IOAUs	O
(	O
Input	B-General_Concept
Output	I-General_Concept
Access	O
Units	O
,	O
the	O
name	O
for	O
separate	O
units	O
which	O
performed	O
the	O
I/O	B-General_Concept
channel	O
programs	O
)	O
.	O
</s>
<s>
The	O
core	B-General_Concept
memory	I-General_Concept
used	O
on	O
the	O
1108/1106	O
systems	O
was	O
replaced	O
with	O
faster	O
plated	B-General_Concept
wire	I-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
Each	O
memory	O
cabinet	O
contained	O
eight	O
independent	O
8K	O
plated	B-General_Concept
wire	I-General_Concept
memory	I-General_Concept
modules	O
,	O
or	O
64K	O
for	O
the	O
entire	O
cabinet	O
.	O
</s>
<s>
It	O
was	O
possible	O
to	O
utilize	O
the	O
1108	O
64K	O
core	B-General_Concept
memory	I-General_Concept
cabinets	O
as	O
Extended	O
Storage	O
,	O
but	O
in	O
most	O
systems	O
utilized	O
,	O
the	O
larger	O
,	O
less	O
expensive	O
131K	O
memory	O
cabinets	O
from	O
the	O
1106	O
system	O
.	O
</s>
<s>
The	O
1110	O
CAU	O
was	O
the	O
first	O
pipelined	B-General_Concept
processor	I-General_Concept
to	O
be	O
designed	O
by	O
UNIVAC	O
.	O
</s>
<s>
This	O
allowed	O
I/O	B-General_Concept
operations	I-General_Concept
to	O
be	O
independent	O
from	O
the	O
compute	O
operations	O
,	O
no	O
longer	O
"	O
stealing	O
"	O
memory	O
cycles	O
from	O
CAU(s )	O
.	O
</s>
<s>
The	O
IOAU	O
Maintenance	O
Panel	O
could	O
display	O
the	O
various	O
CAU	O
registers	B-General_Concept
from	O
one	O
or	O
two	O
associated	O
CAU(s )	O
.	O
</s>
<s>
The	O
1110	O
CAU	O
also	O
introduced	O
an	O
extension	O
to	O
the	O
instruction	B-General_Concept
set	I-General_Concept
of	O
'	O
Byte	O
Instructions	O
 '	O
.	O
</s>
<s>
The	O
discrete	O
component	O
logic	O
used	O
by	O
the	O
older	O
systems	O
was	O
replaced	O
by	O
transistor	B-General_Concept
–	I-General_Concept
transistor	I-General_Concept
logic	I-General_Concept
(	O
TTL	B-General_Concept
)	O
integrated	O
circuits	O
(	O
see	O
Note	O
,	O
below	O
)	O
.	O
</s>
<s>
When	O
Sperry	O
Rand	O
replaced	O
the	O
plated	B-General_Concept
wire	I-General_Concept
memory	I-General_Concept
with	O
semiconductor	B-Architecture
memory	I-Architecture
,	O
the	O
same	O
machine	O
was	O
released	O
as	O
the	O
UNIVAC	O
1100/40	O
.	O
</s>
<s>
In	O
this	O
new	O
naming	O
convention	O
,	O
the	O
final	O
digit	O
represented	O
the	O
number	O
of	O
CPUs	B-General_Concept
in	O
the	O
system	O
.	O
</s>
<s>
The	O
1100/40	O
utilized	O
a	O
new	O
Main	O
Memory	O
cabinet	O
,	O
replacing	O
the	O
8K	O
plated	B-General_Concept
wire	I-General_Concept
memory	I-General_Concept
modules	O
with	O
16K	O
static	B-Architecture
RAM	I-Architecture
modules	O
(	O
based	O
on	O
1024x1-bit	O
static	B-Architecture
RAM	I-Architecture
chips	O
)	O
,	O
for	O
a	O
total	O
of	O
131K	O
per	O
cabinet	O
.	O
</s>
<s>
As	O
with	O
the	O
1110	O
,	O
the	O
1100/40	O
CAU	O
had	O
four	O
base	O
and	O
limit	O
registers	B-General_Concept
,	O
so	O
a	O
program	O
could	O
access	O
four	O
64k	O
banks	O
.	O
</s>
<s>
Note	O
:	O
TTL	B-General_Concept
Integrated	O
circuits	O
used	O
in	O
1110	O
(	O
1100/40	O
)	O
CAU	O
,	O
IOAU	O
and	O
Main	O
Memory	O
cabinets	O
were	O
ceramic	O
14-pin	O
DIPs	B-Algorithm
,	O
where	O
pins	O
4	O
and	O
10	O
were	O
+5	O
volts	O
and	O
ground	O
respectively	O
:	O
state-of-the-art	O
in	O
1969	O
.	O
</s>
<s>
In	O
1975	O
,	O
Sperry	O
Univac	O
introduced	O
a	O
new	O
series	O
of	O
machines	O
with	O
semiconductor	B-Architecture
memory	I-Architecture
replacing	O
core	B-General_Concept
,	O
with	O
a	O
new	O
naming	O
convention	O
:	O
</s>
<s>
In	O
this	O
new	O
naming	O
convention	O
,	O
the	O
final	O
digit	O
represented	O
the	O
number	O
of	O
CPUs	B-General_Concept
or	O
CAUs	O
in	O
the	O
system	O
,	O
so	O
that	O
,	O
for	O
example	O
,	O
a	O
two-processor	O
1100/10	O
system	O
was	O
designated	O
an	O
1100/12	O
.	O
</s>
<s>
The	O
biggest	O
change	O
was	O
the	O
replacement	O
of	O
the	O
Type	O
7015	O
64K	O
Plated	B-General_Concept
Wire	I-General_Concept
Memory	I-General_Concept
cabinet	O
with	O
a	O
new	O
Type	O
7030	O
131K	O
solid	O
state	O
(	O
static	B-Architecture
RAM	I-Architecture
)	O
Memory	O
Cabinet	O
.	O
</s>
<s>
The	O
Type	O
7013	O
131K	O
Core	B-General_Concept
Memory	I-General_Concept
Cabinet	O
(	O
originally	O
used	O
on	O
the	O
later	O
1106	O
Systems	O
as	O
Main	O
Storage	O
)	O
was	O
also	O
replaced	O
with	O
a	O
Solid-State	O
Memory	O
Cabinet	O
,	O
based	O
on	O
Intel	B-General_Concept
1103A	I-General_Concept
DRAM	O
.	O
</s>
<s>
The	O
CAU	O
contained	O
the	O
same	O
basic	O
register	B-General_Concept
stack	O
,	O
in	O
the	O
first	O
128	O
words	O
of	O
addressable	O
memory	O
,	O
as	O
previous	O
generations	O
of	O
1100	O
Series	O
machines	O
,	O
but	O
since	O
these	O
registers	B-General_Concept
were	O
implemented	O
with	O
the	O
same	O
ECL	O
chips	O
as	O
the	O
rest	O
of	O
the	O
system	O
,	O
the	O
registers	B-General_Concept
did	O
not	O
require	O
parity	O
to	O
be	O
generated/checked	O
with	O
each	O
write/read	O
.	O
</s>
<s>
The	O
IOU	O
,	O
or	O
Input/Output	B-General_Concept
Unit	O
was	O
modular	O
in	O
design	O
and	O
could	O
be	O
configured	O
with	O
different	O
Channel	O
Modules	O
to	O
support	O
varying	O
I/O	B-General_Concept
requirements	O
.	O
</s>
<s>
The	O
CAU	O
,	O
IOU	O
,	O
and	O
SIU	O
units	O
were	O
implemented	O
using	O
emitter-coupled	B-General_Concept
logic	I-General_Concept
(	O
ECL	O
)	O
on	O
high	O
density	O
multi-layer	O
PC	O
boards	O
.	O
</s>
<s>
The	O
UNIVAC	B-Device
1100/60	I-Device
was	O
introduced	O
in	O
1979	O
.	O
</s>
<s>
Main	O
Storage	O
(	O
524K	O
to	O
1048K	O
)	O
words	O
per	O
CPU	O
,	O
optional	O
Semiconductor	O
Buffer	O
Storage	O
(	O
up	O
to	O
8K	O
words	O
per	O
CPU	O
)	O
,	O
and	O
the	O
Input/Output	B-General_Concept
Unit	O
(	O
IOU	O
)	O
were	O
contained	O
in	O
CPU	O
cabinet	O
.	O
</s>
<s>
An	O
1100/62	O
Model	O
E1	O
(	O
upgraded	O
version	O
)	O
–	O
Medium	O
Performance	O
Multiprocessor	O
Complex	O
–	O
two	O
CPUs	B-General_Concept
with	O
2K	O
Buffer	O
Storage	O
,	O
two	O
IOUs	O
with	O
one	O
Block	O
Mux	O
,	O
and	O
one	O
Word	O
Channel	O
module	O
(	O
four	O
channels	O
)	O
,	O
1048K	O
words	O
of	O
Main	O
Storage	O
,	O
two	O
System	O
Support	O
Processors	O
,	O
two	O
System	O
Consoles	O
,	O
and	O
a	O
Maintenance	O
Console	O
listed	O
for	O
$	O
889,340	O
.	O
</s>
<s>
The	O
UNIVAC	B-Device
1100/70	I-Device
was	O
introduced	O
in	O
1981	O
.	O
</s>
<s>
The	O
UNIVAC	B-Device
1100/90	I-Device
was	O
introduced	O
in	O
1982	O
.	O
</s>
<s>
As	O
with	O
the	O
1100/80	O
,	O
it	O
was	O
available	O
with	O
up	O
to	O
four	O
processors	O
,	O
and	O
four	O
I/O	B-General_Concept
units	O
.	O
</s>
<s>
The	O
ClearPath	O
machines	O
are	O
a	O
common	O
platform	O
that	O
implement	O
either	O
the	O
1100/2200	O
architecture	O
(	O
the	O
ClearPath	O
IX	O
series	O
)	O
or	O
the	O
Burroughs	B-Device
large	I-Device
systems	I-Device
architecture	O
(	O
the	O
ClearPath	O
NX	O
series	O
)	O
.	O
</s>
<s>
Everything	O
is	O
common	O
except	O
the	O
actual	O
CPUs	B-General_Concept
,	O
which	O
are	O
implemented	O
as	O
ASICs	O
.	O
</s>
<s>
In	O
addition	O
to	O
the	O
IX	O
(	O
1100/2200	O
)	O
CPUs	B-General_Concept
and	O
the	O
NX	O
(	O
Burroughs	B-Device
large	I-Device
systems	I-Device
)	O
CPU	O
,	O
the	O
architecture	O
had	O
Xeon	B-Device
(	O
and	O
briefly	O
Itanium	B-General_Concept
)	O
CPUs	B-General_Concept
.	O
</s>
