<s>
Universal	O
EXTension	O
(	O
UEXT	B-Protocol
)	O
is	O
a	O
connector	O
layout	O
which	O
includes	O
power	O
and	O
three	O
serial	O
buses	O
:	O
Asynchronous	O
,	O
I2C	O
,	O
and	O
SPI	B-Architecture
.	O
</s>
<s>
The	O
UEXT	B-Protocol
connector	O
consists	O
of	O
10	O
pins	O
,	O
in	O
a	O
two	O
row	O
by	O
five	O
male	O
pin	O
configuration	O
,	O
with	O
a	O
plastic	O
keyed-shroud	O
.	O
</s>
<s>
The	O
socket	O
is	O
mated	O
with	O
a	O
2x5	O
(	O
10-pin	O
)	O
IDC	B-Protocol
female	O
connector	O
,	O
and	O
typically	O
connected	O
to	O
a	O
Ribbon	O
cable	O
.	O
</s>
<s>
The	O
UEXT	B-Protocol
cable	O
assembly	O
is	O
referred	O
to	O
as	O
a	O
10-pin	O
IDC	B-Protocol
Connector	I-Protocol
Ribbon	O
Cable	O
.	O
</s>
<s>
The	O
UEXT	B-Protocol
connector	O
presents	O
power	O
and	O
three	O
serial	O
buses	O
:	O
Asynchronous	O
,	O
I2C	O
,	O
SPI	B-Architecture
.	O
</s>
<s>
If	O
a	O
microcontroller	O
pin	O
is	O
connected	O
to	O
the	O
UEXT	B-Protocol
connector	O
and	O
redefined	O
to	O
be	O
something	O
other	O
than	O
Asynchronous	O
Serial	O
Bus	O
/	O
I2C	O
Bus	O
/	O
SPI	B-Architecture
Bus	I-Architecture
,	O
then	O
some	O
thought	O
should	O
be	O
given	O
to	O
the	O
design	O
before	O
making	O
the	O
changes	O
.	O
</s>
<s>
To	O
minimize	O
the	O
chance	O
of	O
damaging	O
various	O
UEXT	B-Protocol
boards	O
or	O
the	O
microcontroller	O
,	O
redefined	O
pins	O
should	O
continue	O
to	O
adhere	O
to	O
the	O
direction	O
of	O
the	O
data	O
in	O
this	O
table	O
or	O
alternately	O
redefined	O
as	O
an	O
input	O
.	O
</s>
<s>
If	O
a	O
person	O
is	O
concerned	O
about	O
damaging	O
the	O
data	O
lines	O
of	O
the	O
microcontroller	O
,	O
additional	O
over-voltage	O
protection	O
diodes	O
and/or	O
separate	O
drivers	O
should	O
be	O
added	O
between	O
the	O
microcontroller	O
and	O
UEXT	B-Protocol
connector	O
.	O
</s>
<s>
Additionally	O
,	O
a	O
resettable	O
fuse	O
might	O
be	O
added	O
between	O
the	O
host	O
power	O
and	O
pin	B-Protocol
1	I-Protocol
to	O
protect	O
against	O
over-current	O
conditions	O
.	O
</s>
<s>
Open	O
source	O
UART	O
dongles	O
are	O
available	O
that	O
are	O
explicitly	O
designed	O
to	O
be	O
pin	O
compatible	O
with	O
UEXT	B-Protocol
,	O
and	O
may	O
be	O
used	O
to	O
interface	O
a	O
UEXT	B-Protocol
device	O
directly	O
with	O
a	O
computer	O
over	O
USB	O
.	O
</s>
<s>
Some	O
boards	O
might	O
provide	O
5V	O
output	O
on	O
UEXT	B-Protocol
pins	O
if	O
they	O
are	O
configured	O
for	O
operation	O
at	O
5V	O
.	O
</s>
<s>
If	O
the	O
3.3V/5V	O
jumper	O
is	O
set	O
to	O
5V	O
,	O
this	O
jumper	O
also	O
changes	O
the	O
voltage	O
available	O
at	O
pin	O
#1	O
of	O
UEXT	B-Protocol
as	O
well	O
as	O
the	O
voltage	O
levels	O
of	O
all	O
data	O
signals	O
available	O
there	O
(	O
UART	O
,	O
SPI	B-Architecture
,	O
I2C	O
)	O
.	O
</s>
<s>
As	O
the	O
UEXT	B-Protocol
standard	O
only	O
defines	O
3.3V	O
,	O
many	O
UEXT	B-Protocol
modules	O
may	O
not	O
be	O
5V	O
tolerant	O
,	O
and	O
thus	O
get	O
damaged	O
if	O
the	O
board	O
has	O
such	O
jumper	O
set	O
to	O
5V	O
.	O
</s>
<s>
Users	O
are	O
advised	O
to	O
verify	O
their	O
boards	O
are	O
configured	O
for	O
3.3V	O
before	O
connecting	O
UEXT	B-Protocol
hardware	O
to	O
prevent	O
damaging	O
said	O
hardware	O
.	O
</s>
<s>
It	O
is	O
possible	O
to	O
connect	O
multiple	O
UEXT	B-Protocol
devices	O
in	O
parallel	O
by	O
clamping	O
additional	O
IDC	B-Protocol
connectors	I-Protocol
onto	O
the	O
same	O
ribbon	O
cable	O
.	O
</s>
<s>
However	O
,	O
the	O
SPI	B-Architecture
bus	I-Architecture
will	O
not	O
work	O
since	O
all	O
the	O
SS	O
lines	O
are	O
tied	O
together	O
(	O
and	O
thus	O
all	O
slaves	O
addressed	O
simultaneously	O
,	O
scrambling	O
data	O
on	O
the	O
MISO	B-Architecture
line	O
)	O
,	O
and	O
neither	O
will	O
UART	O
work	O
since	O
multiple	O
devices	O
are	O
transmitting	O
and	O
receiving	O
on	O
the	O
same	O
lines	O
.	O
</s>
<s>
Series	O
resistors	O
are	O
necessary	O
on	O
conflicting	O
SPI	B-Architecture
and	O
UART	O
pins	O
to	O
limit	O
short	O
circuit	O
currents	O
due	O
to	O
conflicts	O
,	O
if	O
compatibility	O
with	O
other	O
UEXT	B-Protocol
devices	O
is	O
desired	O
.	O
</s>
<s>
Some	O
devices	O
use	O
a	O
layout	O
based	O
on	O
the	O
UEXT	B-Protocol
connector	O
but	O
have	O
chosen	O
not	O
to	O
implement	O
all	O
of	O
the	O
functionality	O
.	O
</s>
