<s>
The	O
TurboSPARC	B-Device
is	O
a	O
microprocessor	B-Architecture
that	O
implements	O
the	O
SPARC	B-Architecture
V8	I-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
developed	O
by	O
Fujitsu	O
Microelectronics	O
,	O
Inc	O
.	O
(	O
FMI	O
)	O
,	O
the	O
United	O
States	O
subsidiary	O
of	O
the	O
Japanese	O
multinational	O
information	O
technology	O
equipment	O
and	O
services	O
company	O
Fujitsu	O
Limited	O
located	O
in	O
San	O
Jose	O
,	O
California	O
.	O
</s>
<s>
It	O
was	O
a	O
low-end	O
microprocessor	B-Architecture
primarily	O
developed	O
as	O
an	O
upgrade	O
for	O
the	O
Sun	O
Microsystems	O
microSPARC-II-based	O
SPARCstation	B-Architecture
5	I-Architecture
workstation	B-Device
.	O
</s>
<s>
The	O
TurboSPARC	B-Device
was	O
mostly	O
succeeded	O
in	O
the	O
low-end	O
SPARC	B-Architecture
market	O
by	O
the	O
UltraSPARC	B-General_Concept
IIi	I-General_Concept
in	O
late	O
1997	O
,	O
but	O
remained	O
available	O
.	O
</s>
<s>
Users	O
of	O
the	O
TurboSPARC	B-Device
were	O
Force	O
Computers	O
,	O
Fujitsu	O
,	O
RDI	O
Computer	O
,	O
Opus	O
Systems	O
,	O
Tadpole	B-Architecture
Technologies	I-Architecture
,	O
Tatung	O
Science	O
and	O
Technology	O
and	O
Themis	O
Computers	O
.	O
</s>
<s>
Fujitsu	O
used	O
a	O
160MHz	O
version	O
in	O
a	O
SPARCstation	B-Architecture
5	I-Architecture
upgrade	O
kit	O
,	O
whereas	O
the	O
other	O
companies	O
used	O
the	O
170MHz	O
version	O
in	O
workstation	B-Device
,	O
notebook	O
and	O
embedded	O
computers	O
.	O
</s>
<s>
The	O
performance	O
of	O
the	O
170MHz	O
TurboSPARC	B-Device
was	O
similar	O
to	O
that	O
of	O
a	O
120MHz	O
Intel	B-General_Concept
Pentium	I-General_Concept
,	O
but	O
when	O
compared	O
to	O
a	O
110MHz	O
microSPARC-II	O
,	O
it	O
had	O
two	O
times	O
the	O
integer	O
performance	O
and	O
one	O
and	O
a	O
half	O
times	O
the	O
floating-point	O
performance	O
.	O
</s>
<s>
The	O
TurboSPARC	B-Device
was	O
a	O
simple	O
scalar	O
in-order	O
design	O
.	O
</s>
<s>
The	O
TurboSPARC	B-Device
had	O
an	O
integer	O
unit	O
and	O
a	O
floating-point	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
TurboSPARC	B-Device
has	O
a	O
16	O
KB	O
data	O
cache	O
.	O
</s>
<s>
The	O
TurboSPARC	B-Device
had	O
an	O
integrated	O
controllers	O
for	O
the	O
L2	O
cache	O
,	O
memory	O
,	O
AFX	O
interface	O
and	O
SBus	B-Architecture
interface	O
.	O
</s>
<s>
The	O
AFX	O
interface	O
enabled	O
AFX	O
graphics	B-Device
cards	I-Device
to	O
directly	O
access	O
the	O
memory	O
.	O
</s>
<s>
The	O
SBus	B-Architecture
controller	O
had	O
its	O
own	O
16-entry	O
input/output	O
translation	O
lookaside	O
buffer	O
.	O
</s>
<s>
TurboSPARC	B-Device
supported	O
SBus	B-Architecture
frequencies	O
of	O
16.67	O
to	O
25MHz	O
.	O
</s>
<s>
The	O
TurboSPARC	B-Device
was	O
not	O
multiprocessor-capable	O
.	O
</s>
<s>
The	O
TurboSPARC	B-Device
contained	O
3.0	O
million	O
transistors	O
and	O
measured	O
11.5	O
by	O
11.5mm	O
for	O
a	O
die	O
area	O
of	O
132.25mm2	O
.	O
</s>
<s>
The	O
TurboSPARC	B-Device
was	O
packaged	O
in	O
a	O
416-ball	O
plastic	B-Algorithm
ball	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
PBGA	B-Algorithm
)	O
.	O
</s>
