<s>
The	O
Itanium	B-General_Concept
9300	I-General_Concept
series	O
,	O
code-named	O
Tukwila	B-General_Concept
,	O
is	O
the	O
generation	O
of	O
Intel	O
's	O
Itanium	B-General_Concept
processor	I-General_Concept
family	I-General_Concept
following	O
Itanium	B-General_Concept
2	O
and	O
Montecito	B-Device
.	O
</s>
<s>
It	O
utilizes	O
both	O
multiple	O
processor	O
cores	O
(	O
multi-core	B-Architecture
)	O
and	O
SMT	B-Operating_System
techniques	O
.	O
</s>
<s>
The	O
engineers	O
said	O
to	O
be	O
working	O
on	O
this	O
project	O
were	O
from	O
the	O
DEC	B-Device
Alpha	I-Device
project	O
,	O
specifically	O
those	O
who	O
worked	O
on	O
the	O
Alpha	B-General_Concept
21464	I-General_Concept
(	O
EV8	O
)	O
,	O
which	O
was	O
focused	O
on	O
SMT	B-Operating_System
.	O
</s>
<s>
Named	O
for	O
the	O
city	O
of	O
Tukwila	B-General_Concept
,	O
Washington	O
,	O
Tukwila	B-General_Concept
was	O
previously	O
code-named	O
Tanglewood	B-Application
.	O
</s>
<s>
The	O
original	O
name	O
is	O
also	O
used	O
by	O
the	O
Tanglewood	B-Application
music	I-Application
festival	I-Application
,	O
and	O
Intel	O
renamed	O
the	O
project	O
in	O
late	O
2003	O
.	O
</s>
<s>
The	O
processor	O
has	O
two	O
to	O
four	O
cores	O
per	O
die	O
and	O
up	O
to	O
24	O
MB	O
L3	O
of	O
on-die	O
cache	B-General_Concept
.	O
</s>
<s>
They	O
are	O
the	O
first	O
batch	O
of	O
processors	O
to	O
contain	O
more	O
than	O
2	O
billion	O
transistors	B-Application
on	O
a	O
single	O
die	O
.	O
</s>
<s>
It	O
was	O
originally	O
stated	O
that	O
Tukwila	B-General_Concept
and	O
its	O
associated	O
chipset	O
would	O
bring	O
socket	O
compatibility	O
between	O
Intel	O
's	O
Xeon	B-Device
and	O
Itanium	B-General_Concept
processors	O
,	O
by	O
introducing	O
a	O
new	O
interconnect	O
called	O
Intel	B-Architecture
QuickPath	I-Architecture
Interconnect	I-Architecture
(	O
QuickPath	B-Architecture
,	O
previously	O
known	O
as	O
Common	B-Architecture
System	I-Architecture
Interface	I-Architecture
or	O
CSI	O
)	O
.	O
</s>
<s>
Tukwila	B-General_Concept
is	O
reported	O
to	O
have	O
four	O
"	O
full	O
"	O
QuickPath	B-Architecture
links	O
and	O
two	O
"	O
half	O
"	O
links	O
.	O
</s>
<s>
Whitefield	O
,	O
the	O
first	O
Xeon	B-Device
processor	O
to	O
feature	O
QuickPath	B-Architecture
,	O
suffered	O
significant	O
project	O
delays	O
and	O
was	O
cancelled	O
.	O
</s>
<s>
The	O
first	O
Xeon	B-Device
MP	I-Device
processor	O
to	O
feature	O
QuickPath	B-Architecture
is	O
Beckton	O
.	O
</s>
<s>
The	O
released	O
Itanium	O
9300-series	O
processors	O
are	O
using	O
a	O
separate	O
socket	O
,	O
LGA	B-Device
1248	I-Device
,	O
which	O
is	O
incompatible	O
with	O
Xeon	B-Device
processors	O
and	O
motherboards	O
.	O
</s>
<s>
In	O
2009	O
an	O
Intel	O
representative	O
stated	O
that	O
Intel	O
would	O
maintain	O
a	O
two-year	O
development	O
cycle	O
for	O
Itanium	B-General_Concept
,	O
implying	O
Poulson	O
would	O
be	O
released	O
in	O
Q1	O
2012	O
.	O
</s>
