<s>
The	O
Tseng	B-General_Concept
Labs	I-General_Concept
ET4000	I-General_Concept
was	O
a	O
line	O
of	O
SVGA	O
graphics	O
controller	O
chips	O
during	O
the	O
early	O
1990s	O
,	O
commonly	O
found	O
in	O
many	O
386/486	O
and	O
compatible	O
systems	O
,	O
with	O
some	O
models	O
,	O
notably	O
the	O
ET4000/W32	O
and	O
later	O
chips	O
,	O
offering	O
graphics	B-Architecture
acceleration	I-Architecture
.	O
</s>
<s>
Offering	O
above	O
average	O
host	O
interface	O
throughput	O
coupled	O
with	O
a	O
moderate	O
price	O
,	O
Tseng	O
Labs	O
 '	O
ET4000	B-General_Concept
chipset	O
family	O
were	O
well	O
regarded	O
for	O
their	O
performance	O
,	O
and	O
were	O
integrated	O
into	O
many	O
companies	O
 '	O
lineups	O
,	O
notably	O
with	O
Hercules	O
 '	O
Dynamite	O
series	O
,	O
the	O
Diamond	O
Stealth	O
32	O
and	O
several	O
Speedstar	O
cards	O
,	O
and	O
on	O
many	O
generic	O
boards	O
.	O
</s>
<s>
The	O
ET4000AX	O
was	O
a	O
major	O
advancement	O
over	O
Tseng	O
Labs	O
 '	O
earlier	O
ET3000	O
SVGA	O
chipset	O
,	O
featuring	O
a	O
new	O
16-bit	O
host	O
interface	O
controller	O
with	O
deep	O
FIFO	B-Operating_System
buffering	O
and	O
caching	O
capabilities	O
,	O
and	O
an	O
enhanced	O
,	O
variable-width	O
memory	O
interface	O
with	O
support	O
for	O
up	O
to	O
1MB	O
of	O
memory	O
with	O
a	O
~	O
16-bit	O
VRAM	O
or	O
~	O
32-bit	O
DRAM	O
memory	O
data	O
bus	O
width	O
.	O
</s>
<s>
The	O
FIFO	B-Operating_System
buffers	O
and	O
cache	O
functions	O
had	O
the	O
effect	O
of	O
greatly	O
improving	O
host	O
interface	O
throughput	O
,	O
and	O
therefore	O
offering	O
substantially	O
improved	O
redraw	O
performance	O
compared	O
to	O
the	O
ET3000	O
and	O
most	O
of	O
its	O
contemporaries	O
.	O
</s>
<s>
The	O
interface	O
controller	O
also	O
offered	O
support	O
for	O
IBM	O
's	O
MCA	B-Device
bus	I-Device
,	O
in	O
addition	O
to	O
an	O
8	O
or	O
16-bit	O
ISA	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
Neither	O
the	O
ET4000AX	O
or	O
its	O
succeeding	O
family	O
members	O
offered	O
an	O
integrated	O
RAMDAC	B-Device
,	O
which	O
hampered	O
the	O
line	O
's	O
cost/performance	O
competitiveness	O
later	O
on	O
.	O
</s>
<s>
Hardware	B-General_Concept
acceleration	I-General_Concept
via	O
dedicated	O
BitBLT	B-Algorithm
hardware	O
and	O
a	O
hardware	O
cursor	O
sprite	O
was	O
introduced	O
in	O
the	O
ET4000/W32	O
.	O
</s>
<s>
The	O
W32	O
offered	O
improved	O
local	O
bus	O
support	O
along	O
with	O
further	O
increased	O
host	O
interface	O
performance	O
,	O
but	O
by	O
the	O
time	O
PCI	B-Protocol
Windows	O
accelerators	O
became	O
commonplace	O
,	O
high	O
host	O
throughput	O
was	O
no	O
longer	O
a	O
distinguishing	O
feature	O
.	O
</s>
<s>
The	O
W32p	O
model	O
offered	O
support	O
for	O
the	O
PCI	B-Protocol
bus	I-Protocol
,	O
although	O
earlier	O
revisions	O
of	O
this	O
chip	O
(	O
prior	O
to	O
Revision	O
D	O
)	O
had	O
some	O
design	O
problems	O
that	O
caused	O
sub-optimal	O
or	O
problematic	O
operation	O
when	O
used	O
in	O
PCI	B-Protocol
implementations	O
,	O
although	O
VLB	O
implementations	O
were	O
unaffected	O
.	O
</s>
