<s>
The	O
transputer	B-General_Concept
is	O
a	O
series	O
of	O
pioneering	O
microprocessors	B-Architecture
from	O
the	O
1980s	O
,	O
intended	O
for	O
parallel	B-Operating_System
computing	I-Operating_System
.	O
</s>
<s>
To	O
support	O
this	O
,	O
each	O
transputer	B-General_Concept
had	O
its	O
own	O
integrated	O
memory	O
and	O
serial	B-Protocol
communication	I-Protocol
links	O
to	O
exchange	O
data	O
with	O
other	O
transputers	B-General_Concept
.	O
</s>
<s>
For	O
some	O
time	O
in	O
the	O
late	O
1980s	O
,	O
many	O
considered	O
the	O
transputer	B-General_Concept
to	O
be	O
the	O
next	O
great	O
design	O
for	O
the	O
future	O
of	O
computing	O
.	O
</s>
<s>
While	O
the	O
transputer	B-General_Concept
did	O
not	O
achieve	O
this	O
expectation	O
,	O
the	O
transputer	B-General_Concept
architecture	O
was	O
highly	O
influential	O
in	O
provoking	O
new	O
ideas	O
in	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
several	O
of	O
which	O
have	O
re-emerged	O
in	O
different	O
forms	O
in	O
modern	O
systems	O
.	O
</s>
<s>
In	O
the	O
early	O
1980s	O
,	O
conventional	O
central	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
(	O
CPUs	O
)	O
appeared	O
to	O
have	O
reached	O
a	O
performance	O
limit	O
.	O
</s>
<s>
Traditional	O
complex	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
CISC	B-Architecture
)	O
designs	O
were	O
reaching	O
a	O
performance	O
plateau	O
,	O
and	O
it	O
was	O
n't	O
clear	O
it	O
could	O
be	O
overcome	O
.	O
</s>
<s>
It	O
seemed	O
that	O
the	O
only	O
way	O
forward	O
was	O
to	O
increase	O
the	O
use	O
of	O
parallelism	B-Operating_System
,	O
the	O
use	O
of	O
several	O
CPUs	O
that	O
would	O
work	O
together	O
to	O
solve	O
several	O
tasks	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
This	O
depended	O
on	O
such	O
machines	O
being	O
able	O
to	O
run	O
several	O
tasks	O
at	O
once	O
,	O
a	O
process	O
termed	O
multitasking	B-Operating_System
.	O
</s>
<s>
This	O
had	O
generally	O
been	O
too	O
difficult	O
for	O
prior	O
microprocessor	B-Architecture
designs	O
to	O
handle	O
,	O
but	O
more	O
recent	O
designs	O
were	O
able	O
to	O
accomplish	O
it	O
effectively	O
.	O
</s>
<s>
It	O
was	O
clear	O
that	O
in	O
the	O
future	O
,	O
this	O
would	O
be	O
a	O
feature	O
of	O
all	O
operating	B-General_Concept
systems	I-General_Concept
(	O
OSs	O
)	O
.	O
</s>
<s>
A	O
side	O
effect	O
of	O
most	O
multitasking	B-Operating_System
design	O
is	O
that	O
it	O
often	O
also	O
allows	O
the	O
processes	O
to	O
be	O
run	O
on	O
physically	O
different	O
CPUs	O
,	O
in	O
which	O
case	O
it	O
is	O
termed	O
multiprocessing	B-Operating_System
.	O
</s>
<s>
A	O
low-cost	O
CPU	B-General_Concept
built	O
for	O
multiprocessing	B-Operating_System
could	O
allow	O
the	O
speed	O
of	O
a	O
machine	O
to	O
be	O
raised	O
by	O
adding	O
more	O
CPUs	O
,	O
potentially	O
far	O
more	O
cheaply	O
than	O
by	O
using	O
one	O
faster	O
CPU	B-General_Concept
design	O
.	O
</s>
<s>
The	O
first	O
transputer	B-General_Concept
designs	O
were	O
due	O
to	O
computer	O
scientist	O
David	O
May	O
and	O
telecommunications	O
consultant	O
Robert	O
Milne	O
.	O
</s>
<s>
Tony	O
Fuge	O
,	O
then	O
a	O
leading	O
engineer	O
at	O
Inmos	O
,	O
was	O
awarded	O
the	O
Prince	O
Philip	O
Designers	O
Prize	O
in	O
1987	O
for	O
his	O
work	O
on	O
the	O
T414	O
transputer	B-General_Concept
.	O
</s>
<s>
The	O
transputer	B-General_Concept
was	O
the	O
first	O
general	O
purpose	O
microprocessor	B-Architecture
designed	O
specifically	O
to	O
be	O
used	O
in	O
parallel	B-Operating_System
computing	I-Operating_System
systems	O
.	O
</s>
<s>
The	O
goal	O
was	O
to	O
produce	O
a	O
family	O
of	O
chips	O
ranging	O
in	O
power	O
and	O
cost	O
that	O
could	O
be	O
wired	O
together	O
to	O
form	O
a	O
complete	O
parallel	B-Operating_System
computer	I-Operating_System
.	O
</s>
<s>
The	O
name	O
,	O
from	O
"	O
transistor	B-Application
"	O
and	O
"	O
computer	O
"	O
)	O
,	O
was	O
selected	O
to	O
indicate	O
the	O
role	O
the	O
individual	O
transputers	B-General_Concept
would	O
play	O
:	O
numbers	O
of	O
them	O
would	O
be	O
used	O
as	O
basic	O
building	O
blocks	O
,	O
just	O
as	O
transistors	B-Application
had	O
earlier	O
.	O
</s>
<s>
Originally	O
the	O
plan	O
was	O
to	O
make	O
the	O
transputer	B-General_Concept
cost	O
only	O
a	O
few	O
dollars	O
per	O
unit	O
.	O
</s>
<s>
Inmos	O
saw	O
them	O
being	O
used	O
for	O
practically	O
everything	O
,	O
from	O
operating	O
as	O
the	O
main	O
CPU	B-General_Concept
for	O
a	O
computer	O
to	O
acting	O
as	O
a	O
channel	B-Device
controller	I-Device
for	O
disk	B-Device
drives	I-Device
in	O
the	O
same	O
machine	O
.	O
</s>
<s>
In	O
a	O
traditional	O
machine	O
,	O
the	O
processing	O
capability	O
of	O
a	O
disk	B-Device
controller	O
,	O
for	O
instance	O
,	O
would	O
be	O
idle	O
when	O
the	O
disk	B-Device
was	O
not	O
being	O
accessed	O
.	O
</s>
<s>
In	O
contrast	O
,	O
in	O
a	O
transputer	B-General_Concept
system	O
,	O
spare	O
cycles	O
on	O
any	O
of	O
these	O
transputers	B-General_Concept
could	O
be	O
used	O
for	O
other	O
tasks	O
,	O
greatly	O
increasing	O
the	O
overall	O
performance	O
of	O
the	O
machines	O
.	O
</s>
<s>
Even	O
one	O
transputer	B-General_Concept
would	O
have	O
all	O
the	O
circuitry	O
needed	O
to	O
work	O
by	O
itself	O
,	O
a	O
feature	O
more	O
commonly	O
associated	O
with	O
microcontrollers	B-Architecture
.	O
</s>
<s>
The	O
intent	O
was	O
to	O
allow	O
transputers	B-General_Concept
to	O
be	O
connected	O
together	O
as	O
easily	O
as	O
possible	O
,	O
with	O
no	O
need	O
for	O
a	O
complex	O
bus	B-General_Concept
,	O
or	O
motherboard	B-Device
.	O
</s>
<s>
Power	O
and	O
a	O
simple	O
clock	O
signal	O
had	O
to	O
be	O
supplied	O
,	O
but	O
little	O
else	O
:	O
random-access	B-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
,	O
a	O
RAM	B-Architecture
controller	O
,	O
bus	B-General_Concept
support	O
and	O
even	O
a	O
real-time	B-Operating_System
operating	I-Operating_System
system	I-Operating_System
(	O
RTOS	B-Operating_System
)	O
were	O
all	O
built	O
in	O
.	O
</s>
<s>
The	O
original	O
transputer	B-General_Concept
used	O
a	O
very	O
simple	O
and	O
rather	O
unusual	O
architecture	O
to	O
achieve	O
a	O
high	O
performance	O
in	O
a	O
small	O
area	O
.	O
</s>
<s>
It	O
used	O
microcode	B-Device
as	O
the	O
main	O
method	O
to	O
control	O
the	O
data	O
path	O
,	O
but	O
unlike	O
other	O
designs	O
of	O
the	O
time	O
,	O
many	O
instructions	O
took	O
only	O
one	O
cycle	O
to	O
execute	O
.	O
</s>
<s>
Instruction	B-Language
opcodes	I-Language
were	O
used	O
as	O
the	O
entry	O
points	O
to	O
the	O
microcode	B-Device
read-only	B-Device
memory	I-Device
(	O
ROM	B-Device
)	O
and	O
the	O
outputs	O
from	O
the	O
ROM	B-Device
were	O
fed	O
directly	O
to	O
the	O
data	O
path	O
.	O
</s>
<s>
For	O
multi-cycle	O
instructions	O
,	O
while	O
the	O
data	O
path	O
was	O
performing	O
the	O
first	O
cycle	O
,	O
the	O
microcode	B-Device
decoded	O
four	O
possible	O
options	O
for	O
the	O
second	O
cycle	O
.	O
</s>
<s>
The	O
internal	O
clock	O
actually	O
had	O
four	O
non-overlapping	O
phases	O
and	O
designers	O
were	O
free	O
to	O
use	O
whichever	O
combination	O
of	O
these	O
they	O
wanted	O
,	O
so	O
it	O
could	O
be	O
argued	O
that	O
the	O
transputer	B-General_Concept
actually	O
ran	O
at	O
80MHz	O
.	O
</s>
<s>
Dynamic	B-General_Concept
logic	I-General_Concept
was	O
used	O
in	O
many	O
parts	O
of	O
the	O
design	O
to	O
reduce	O
area	O
and	O
increase	O
speed	O
.	O
</s>
<s>
Prentice-Hall	O
published	O
a	O
book	O
on	O
the	O
general	O
principles	O
of	O
the	O
transputer	B-General_Concept
.	O
</s>
<s>
The	O
basic	O
design	O
of	O
the	O
transputer	B-General_Concept
included	O
serial	B-Protocol
links	I-Protocol
known	O
as	O
"	O
os-link	O
"	O
s	O
that	O
allowed	O
it	O
to	O
communicate	O
with	O
up	O
to	O
four	O
other	O
transputers	B-General_Concept
,	O
each	O
at	O
5	O
,	O
10	O
,	O
or	O
20Mbit/s	O
which	O
was	O
very	O
fast	O
for	O
the	O
1980s	O
.	O
</s>
<s>
Any	O
number	O
of	O
transputers	B-General_Concept
could	O
be	O
connected	O
together	O
over	O
links	O
(	O
which	O
could	O
run	O
tens	O
of	O
metres	O
)	O
to	O
form	O
one	O
computing	O
farm	O
.	O
</s>
<s>
A	O
hypothetical	O
desktop	O
machine	O
might	O
have	O
two	O
of	O
the	O
"	O
low	O
end	O
"	O
transputers	B-General_Concept
handling	O
input/output	B-General_Concept
(	O
I/O	B-General_Concept
)	O
tasks	O
on	O
some	O
of	O
their	O
serial	O
lines	O
(	O
hooked	O
up	O
to	O
appropriate	O
hardware	O
)	O
while	O
they	O
talked	O
to	O
one	O
of	O
their	O
larger	O
cousins	O
acting	O
as	O
a	O
CPU	B-General_Concept
on	O
another	O
.	O
</s>
<s>
Since	O
each	O
transputer	B-General_Concept
was	O
linked	O
to	O
another	O
in	O
a	O
fixed	O
point-to-point	O
layout	O
,	O
sending	O
messages	O
to	O
a	O
more	O
distant	O
transputer	B-General_Concept
required	O
that	O
messages	O
be	O
relayed	O
by	O
each	O
chip	O
in	O
the	O
line	O
.	O
</s>
<s>
To	O
solve	O
this	O
problem	O
Inmos	O
also	O
provided	O
a	O
zero-delay	O
switch	O
that	O
connected	O
up	O
to	O
32	O
transputers	B-General_Concept
(	O
or	O
switches	O
)	O
into	O
even	O
larger	O
networks	O
.	O
</s>
<s>
Transputers	B-General_Concept
could	O
boot	O
from	O
memory	O
,	O
as	O
is	O
the	O
case	O
for	O
most	O
computers	O
,	O
but	O
could	O
also	O
be	O
booted	O
over	B-Device
its	I-Device
network	I-Device
links	I-Device
.	O
</s>
<s>
The	O
general	O
concept	O
for	O
the	O
system	O
was	O
to	O
have	O
one	O
transputer	B-General_Concept
act	O
as	O
the	O
central	O
authority	O
for	O
booting	O
a	O
system	O
containing	O
a	O
number	O
of	O
connected	O
transputers	B-General_Concept
.	O
</s>
<s>
The	O
selected	O
transputer	B-General_Concept
would	O
have	O
the	O
BootFromROM	O
permanently	O
asserted	O
,	O
which	O
would	O
cause	O
it	O
to	O
begin	O
running	O
a	O
booter	O
process	O
from	O
ROM	B-Device
on	O
startup	O
.	O
</s>
<s>
The	O
other	O
transputers	B-General_Concept
would	O
have	O
the	O
BootFromROM	O
tied	O
low	O
,	O
and	O
would	O
simply	O
wait	O
.	O
</s>
<s>
The	O
loader	O
would	O
boot	O
the	O
central	O
transputer	B-General_Concept
,	O
which	O
would	O
then	O
begin	O
sending	O
boot	O
code	O
to	O
the	O
other	O
transputers	B-General_Concept
in	O
the	O
network	O
,	O
and	O
could	O
customize	O
the	O
code	O
sent	O
to	O
each	O
one	O
,	O
for	O
instance	O
,	O
sending	O
a	O
device	B-Application
driver	I-Application
to	O
the	O
transputer	B-General_Concept
connected	O
to	O
the	O
hard	O
drives	O
.	O
</s>
<s>
The	O
system	O
also	O
included	O
the	O
'	O
special	O
 '	O
code	O
lengths	O
of	O
0	O
and	O
1	O
which	O
were	O
reserved	O
for	O
PEEK	B-Language
and	I-Language
POKE	I-Language
.	O
</s>
<s>
This	O
allowed	O
inspection	O
and	O
changing	O
of	O
RAM	B-Architecture
in	O
an	O
unbooted	O
transputer	B-General_Concept
.	O
</s>
<s>
After	O
a	O
peek	O
,	O
followed	O
by	O
a	O
memory	O
address	O
,	O
or	O
a	O
poke	O
,	O
with	O
an	O
address	O
and	O
single	O
word	O
of	O
data	O
,	O
the	O
transputer	B-General_Concept
would	O
return	O
to	O
waiting	O
for	O
a	O
bootstrap	O
.	O
</s>
<s>
Other	O
processes	O
running	O
on	O
the	O
transputer	B-General_Concept
would	O
then	O
be	O
given	O
that	O
processing	O
time	O
.	O
</s>
<s>
It	O
included	O
two	O
priority	O
levels	O
to	O
improve	O
real-time	B-General_Concept
and	O
multiprocessor	B-Operating_System
operation	O
.	O
</s>
<s>
The	O
same	O
logical	O
system	O
was	O
used	O
to	O
communicate	O
between	O
programs	O
running	O
on	O
one	O
transputer	B-General_Concept
,	O
implemented	O
as	O
virtual	O
network	O
links	O
in	O
memory	O
.	O
</s>
<s>
So	O
programs	O
asking	O
for	O
any	O
input	O
or	O
output	O
automatically	O
paused	O
while	O
the	O
operation	O
completed	O
,	O
a	O
task	O
that	O
normally	O
required	O
an	O
operating	B-General_Concept
system	I-General_Concept
to	O
handle	O
as	O
the	O
arbiter	O
of	O
hardware	O
.	O
</s>
<s>
Operating	B-General_Concept
systems	I-General_Concept
on	O
the	O
transputer	B-General_Concept
did	O
not	O
need	O
to	O
handle	O
scheduling	O
;	O
the	O
chip	O
could	O
be	O
considered	O
to	O
have	O
an	O
OS	O
inside	O
it	O
.	O
</s>
<s>
To	O
include	O
all	O
this	O
function	O
on	O
one	O
chip	O
,	O
the	O
transputer	B-General_Concept
's	O
core	O
logic	O
was	O
simpler	O
than	O
most	O
CPUs	O
.	O
</s>
<s>
While	O
some	O
have	O
called	O
it	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
due	O
to	O
its	O
rather	O
sparse	O
nature	O
,	O
and	O
because	O
that	O
was	O
then	O
a	O
desirable	O
marketing	O
buzzword	O
,	O
it	O
was	O
heavily	O
microcoded	B-Device
,	O
had	O
a	O
limited	O
register	O
set	O
,	O
and	O
complex	O
memory-to-memory	O
instructions	O
,	O
all	O
of	O
which	O
place	O
it	O
firmly	O
in	O
the	O
CISC	B-Architecture
camp	O
.	O
</s>
<s>
Unlike	O
register-heavy	O
load/store	B-Architecture
RISC	I-Architecture
CPUs	O
,	O
the	O
transputer	B-General_Concept
had	O
only	O
three	O
data	O
registers	O
,	O
which	O
behaved	O
as	O
a	O
stack	O
.	O
</s>
<s>
This	O
allowed	O
for	O
very	O
fast	O
context	B-Operating_System
switching	I-Operating_System
by	O
simply	O
changing	O
the	O
workspace	O
pointer	O
to	O
the	O
memory	O
used	O
by	O
another	O
process	O
(	O
a	O
method	O
used	O
in	O
a	O
number	O
of	O
contemporary	O
designs	O
,	O
such	O
as	O
the	O
TMS9900	B-General_Concept
)	O
.	O
</s>
<s>
The	O
three	O
register	O
stack	O
contents	O
were	O
not	O
preserved	O
past	O
certain	O
instructions	O
,	O
like	O
Jump	O
,	O
when	O
the	O
transputer	B-General_Concept
could	O
do	O
a	O
context	B-Operating_System
switch	I-Operating_System
.	O
</s>
<s>
The	O
transputer	B-General_Concept
instruction	O
set	O
consisted	O
of	O
8-bit	O
instructions	O
assembled	O
from	O
opcode	B-Language
and	O
operand	O
nibbles	O
.	O
</s>
<s>
The	O
upper	O
nibble	O
contained	O
the	O
16	O
possible	O
primary	O
instruction	B-Language
codes	I-Language
,	O
making	O
it	O
one	O
of	O
the	O
very	O
few	O
commercialized	O
minimal	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
computers	I-General_Concept
.	O
</s>
<s>
Further	O
instructions	O
were	O
supported	O
via	O
the	O
instruction	B-Language
code	I-Language
Operate	O
(	O
Opr	O
)	O
,	O
which	O
decoded	O
the	O
constant	O
operand	O
as	O
an	O
extended	O
zero-operand	O
opcode	B-Language
,	O
providing	O
for	O
almost	O
endless	O
and	O
easy	O
instruction	O
set	O
expansion	O
as	O
newer	O
implementations	O
of	O
the	O
transputer	B-General_Concept
were	O
introduced	O
.	O
</s>
<s>
To	O
provide	O
an	O
easy	O
means	O
of	O
prototyping	O
,	O
constructing	O
and	O
configuring	O
multiple-transputer	O
systems	O
,	O
Inmos	O
introduced	O
the	O
TRAM	O
(	O
TRAnsputer	B-General_Concept
Module	O
)	O
standard	O
in	O
1987	O
.	O
</s>
<s>
A	O
TRAM	O
was	O
essentially	O
a	O
building	O
block	O
daughterboard	O
comprising	O
a	O
transputer	B-General_Concept
and	O
,	O
optionally	O
,	O
external	O
memory	O
and/or	O
peripheral	O
devices	O
,	O
with	O
simple	O
standardised	O
connectors	O
providing	O
power	O
,	O
transputer	B-General_Concept
links	O
,	O
clock	O
and	O
system	O
signals	O
.	O
</s>
<s>
Inmos	O
produced	O
a	O
range	O
of	O
TRAM	O
motherboards	B-Device
for	O
various	O
host	O
buses	O
such	O
as	O
Industry	B-Architecture
Standard	I-Architecture
Architecture	I-Architecture
(	O
ISA	O
)	O
,	O
MicroChannel	B-Device
,	O
or	O
VMEbus	B-Architecture
.	O
</s>
<s>
Transputers	B-General_Concept
were	O
intended	O
to	O
be	O
programmed	O
using	O
the	O
programming	O
language	O
occam	B-Language
,	O
based	O
on	O
the	O
communicating	O
sequential	O
processes	O
(	O
CSP	O
)	O
process	O
calculus	O
.	O
</s>
<s>
The	O
transputer	B-General_Concept
was	O
built	O
to	O
run	O
Occam	B-Language
specifically	O
,	O
more	O
than	O
contemporary	O
CISC	B-Architecture
designs	O
were	O
built	O
to	O
run	O
languages	O
like	O
Pascal	B-Application
or	O
C	B-Language
.	O
Occam	B-Language
supported	O
concurrency	B-Operating_System
and	O
channel-based	O
inter-process	O
or	O
inter-processor	O
communication	O
as	O
a	O
fundamental	O
part	O
of	O
the	O
language	O
.	O
</s>
<s>
With	O
the	O
parallelism	B-Operating_System
and	O
communications	O
built	O
into	O
the	O
chip	O
and	O
the	O
language	O
interacting	O
with	O
it	O
directly	O
,	O
writing	O
code	O
for	O
things	O
like	O
device	O
controllers	O
became	O
a	O
triviality	O
;	O
even	O
the	O
most	O
basic	O
code	O
could	O
watch	O
the	O
serial	O
ports	O
for	O
I/O	B-General_Concept
,	O
and	O
would	O
automatically	O
sleep	O
when	O
there	O
was	O
no	O
data	O
.	O
</s>
<s>
The	O
initial	O
Occam	B-Language
development	O
environment	O
for	O
the	O
transputer	B-General_Concept
was	O
the	O
Inmos	O
D700	O
Transputer	B-General_Concept
Development	O
System	O
(	O
TDS	O
)	O
.	O
</s>
<s>
The	O
TDS	O
was	O
a	O
transputer	B-General_Concept
application	O
written	O
in	O
Occam	B-Language
.	O
</s>
<s>
Unfortunately	O
,	O
the	O
combination	O
of	O
an	O
unfamiliar	O
programming	O
language	O
and	O
equally	O
unfamiliar	O
development	O
environment	O
did	O
nothing	O
for	O
the	O
early	O
popularity	O
of	O
the	O
transputer	B-General_Concept
.	O
</s>
<s>
Later	O
,	O
Inmos	O
would	O
release	O
more	O
conventional	O
Occam	B-Language
cross-compilers	O
,	O
the	O
Occam	B-Language
2	I-Language
Toolsets	O
.	O
</s>
<s>
Implementations	O
of	O
more	O
mainstream	O
programming	O
languages	O
,	O
such	O
as	O
C	B-Language
,	O
FORTRAN	B-Application
,	O
Ada	B-Language
,	O
Forth	B-Application
,	O
and	O
Pascal	B-Application
were	O
also	O
later	O
released	O
by	O
both	O
Inmos	O
and	O
third-party	O
vendors	O
.	O
</s>
<s>
These	O
usually	O
included	O
language	O
extensions	O
or	O
libraries	O
providing	O
,	O
in	O
a	O
less	O
elegant	O
way	O
,	O
Occam-like	O
concurrency	B-Operating_System
and	O
channel-based	O
communication	O
.	O
</s>
<s>
The	O
transputer	B-General_Concept
's	O
lack	O
of	O
support	O
for	O
virtual	B-Architecture
memory	I-Architecture
inhibited	O
the	O
porting	O
of	O
mainstream	O
variants	O
of	O
the	O
Unix	B-Application
operating	I-Application
system	I-Application
,	O
though	O
ports	O
of	O
Unix-like	B-Operating_System
operating	I-Operating_System
systems	I-Operating_System
(	O
such	O
as	O
Minix	B-Operating_System
and	O
Idris	B-Operating_System
from	O
Whitesmiths	O
)	O
were	O
produced	O
.	O
</s>
<s>
An	O
advanced	O
Unix-like	B-Operating_System
distributed	B-Operating_System
operating	I-Operating_System
system	I-Operating_System
,	O
HeliOS	B-Operating_System
,	O
was	O
also	O
designed	O
specifically	O
for	O
multi-transputer	O
systems	O
by	O
Perihelion	O
Software	O
.	O
</s>
<s>
The	O
first	O
transputers	B-General_Concept
were	O
announced	O
in	O
1983	O
and	O
released	O
in	O
1984	O
.	O
</s>
<s>
In	O
keeping	O
with	O
their	O
role	O
as	O
microcontroller-like	O
devices	O
,	O
they	O
included	O
on-board	O
RAM	B-Architecture
and	O
a	O
built-in	O
RAM	B-Architecture
controller	O
which	O
enabled	O
more	O
memory	O
to	O
be	O
added	O
with	O
no	O
added	O
hardware	O
.	O
</s>
<s>
Unlike	O
other	O
designs	O
,	O
transputers	B-General_Concept
did	O
not	O
include	O
I/O	B-General_Concept
lines	O
:	O
these	O
were	O
to	O
be	O
added	O
with	O
hardware	O
attached	O
to	O
the	O
existing	O
serial	B-Protocol
links	I-Protocol
.	O
</s>
<s>
All	O
transputers	B-General_Concept
ran	O
from	O
an	O
external	O
5MHz	O
clock	O
input	O
;	O
this	O
was	O
multiplied	O
to	O
provide	O
the	O
processor	O
clock	O
.	O
</s>
<s>
The	O
transputer	B-General_Concept
did	O
not	O
include	O
a	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
or	O
a	O
virtual	B-Architecture
memory	I-Architecture
system	O
.	O
</s>
<s>
Transputer	B-General_Concept
variants	O
(	O
except	O
the	O
cancelled	O
T9000	O
)	O
can	O
be	O
categorised	O
into	O
three	O
groups	O
:	O
the	O
16-bit	B-Device
T2	O
series	O
,	O
the	O
32-bit	O
T4	O
series	O
,	O
and	O
the	O
32-bit	O
T8	O
series	O
with	O
64-bit	O
IEEE	O
754	O
floating-point	B-Algorithm
support	O
.	O
</s>
<s>
The	O
prototype	O
16-bit	B-Device
transputer	B-General_Concept
was	O
the	O
S43	O
,	O
which	O
lacked	O
the	O
scheduler	O
and	O
DMA-controlled	O
block	O
transfer	O
on	O
the	O
links	O
.	O
</s>
<s>
At	O
launch	O
,	O
the	O
T212	O
and	O
M212	O
(	O
the	O
latter	O
with	O
an	O
on-board	O
disk	B-Device
controller	O
)	O
were	O
the	O
16-bit	B-Device
offerings	O
.	O
</s>
<s>
The	O
T212	O
was	O
superseded	O
by	O
the	O
T222	O
,	O
with	O
on-chip	O
RAM	B-Architecture
expanded	O
from	O
2KB	O
to	O
4KB	O
,	O
and	O
,	O
later	O
,	O
the	O
T225	O
.	O
</s>
<s>
Launched	O
in	O
October	O
1985	O
,	O
the	O
T414	O
employed	O
the	O
equivalent	O
of	O
900,000	O
transistors	B-Application
and	O
was	O
fabricated	O
with	O
a	O
feature	O
size	O
.	O
</s>
<s>
Originally	O
,	O
the	O
first	O
32-bit	O
variant	O
was	O
to	O
be	O
the	O
T424	O
,	O
but	O
fabrication	O
difficulties	O
meant	O
that	O
this	O
was	O
redesigned	O
as	O
the	O
T414	O
with	O
2KB	O
on-board	O
RAM	B-Architecture
instead	O
of	O
the	O
intended	O
4KB	O
.	O
</s>
<s>
The	O
RAM	B-Architecture
was	O
later	O
reinstated	O
to	O
4KB	O
on	O
the	O
T425	O
(	O
in	O
20	O
,	O
25	O
,	O
and	O
30MHz	O
varieties	O
)	O
,	O
which	O
also	O
added	O
the	O
J	O
0	O
breakpoint	O
support	O
and	O
extra	O
T800	O
instructions	O
.	O
</s>
<s>
The	O
T400	O
,	O
released	O
in	O
September	O
1989	O
,	O
was	O
a	O
low-cost	O
20MHz	O
T425	O
derivative	O
with	O
2KB	O
and	O
two	O
instead	O
of	O
four	O
links	O
,	O
intended	O
for	O
the	O
embedded	B-Architecture
systems	I-Architecture
market	O
.	O
</s>
<s>
The	O
second-generation	O
T800	O
transputer	B-General_Concept
,	O
introduced	O
in	O
1987	O
,	O
had	O
an	O
extended	O
instruction	O
set	O
.	O
</s>
<s>
The	O
most	O
important	O
addition	O
was	O
a	O
64-bit	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
and	O
three	O
added	O
registers	O
for	O
floating	B-Algorithm
point	I-Algorithm
,	O
implementing	O
the	O
IEEE	O
754-1985	O
floating	B-Algorithm
point	I-Algorithm
standard	O
.	O
</s>
<s>
It	O
also	O
had	O
4KB	O
of	O
on-board	O
RAM	B-Architecture
and	O
was	O
available	O
in	O
20	O
or	O
25MHz	O
versions	O
.	O
</s>
<s>
Breakpoint	O
support	O
was	O
added	O
in	O
the	O
later	O
T801	O
and	O
T805	O
,	O
the	O
former	O
featuring	O
separate	O
address	O
and	O
data	B-General_Concept
buses	I-General_Concept
to	O
improve	O
performance	O
.	O
</s>
<s>
An	O
enhanced	O
T810	O
was	O
planned	O
,	O
which	O
would	O
have	O
had	O
more	O
RAM	B-Architecture
,	O
more	O
and	O
faster	O
links	O
,	O
extra	O
instructions	O
,	O
and	O
improved	O
microcode	B-Device
,	O
but	O
this	O
was	O
cancelled	O
around	O
1990	O
.	O
</s>
<s>
Inmos	O
also	O
produced	O
a	O
variety	O
of	O
support	O
chips	O
for	O
the	O
transputer	B-General_Concept
processors	O
,	O
such	O
as	O
the	O
C004	O
32-way	O
link	O
switch	O
and	O
the	O
C011	O
and	O
C012	O
"	O
link	O
adapters	O
"	O
which	O
allowed	O
transputer	B-General_Concept
links	O
to	O
be	O
interfaced	O
to	O
an	O
8-bit	O
data	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
Although	O
a	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoC	O
)	O
as	O
they	O
are	O
commonly	O
termed	O
,	O
are	O
ubiquitous	O
now	O
,	O
the	O
concept	O
was	O
almost	O
unheard	O
of	O
back	O
in	O
the	O
early	O
1980s	O
.	O
</s>
<s>
The	O
M212	O
was	O
based	O
on	O
a	O
standard	O
T212	O
core	O
with	O
the	O
addition	O
of	O
a	O
disk	B-Device
controller	O
for	O
the	O
ST	O
506	O
and	O
ST	O
412	O
Shugart	O
standards	O
.	O
</s>
<s>
TV-toy	O
was	O
to	O
be	O
the	O
basis	O
for	O
a	O
video	B-Device
game	I-Device
console	I-Device
and	O
was	O
joint	O
project	O
between	O
Inmos	O
and	O
Sinclair	O
Research	O
.	O
</s>
<s>
The	O
links	O
in	O
the	O
T212	O
and	O
T414/T424	O
transputers	B-General_Concept
had	O
hardware	O
DMA	O
engines	O
so	O
that	O
transfers	O
could	O
happen	O
in	O
parallel	O
with	O
execution	O
of	O
other	O
processes	O
.	O
</s>
<s>
A	O
variant	O
of	O
the	O
design	O
,	O
termed	O
the	O
T400	O
,	O
not	O
to	O
be	O
confused	O
with	O
a	O
later	O
transputer	B-General_Concept
of	O
the	O
same	O
name	O
,	O
was	O
designed	O
where	O
the	O
CPU	B-General_Concept
handled	O
these	O
transfers	O
.	O
</s>
<s>
This	O
reduced	O
the	O
size	O
of	O
the	O
device	O
considerably	O
since	O
4	O
link	O
engines	O
were	O
approximately	O
the	O
same	O
size	O
as	O
the	O
whole	O
CPU	B-General_Concept
.	O
</s>
<s>
The	O
T400	O
was	O
intended	O
to	O
be	O
used	O
as	O
a	O
core	O
in	O
what	O
were	O
then	O
called	O
systems	O
on	O
silicon	O
(	O
SOS	O
)	O
devices	O
,	O
now	O
termed	O
and	O
better	O
known	O
as	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoC	O
)	O
.	O
</s>
<s>
Although	O
the	O
prior	O
SoC	O
projects	O
had	O
had	O
only	O
limited	O
success	O
(	O
the	O
M212	O
was	O
sold	O
for	O
a	O
time	O
)	O
,	O
many	O
designers	O
still	O
firmly	O
believed	O
in	O
the	O
concept	O
and	O
in	O
1987	O
,	O
a	O
new	O
project	O
,	O
the	O
T100	O
was	O
started	O
which	O
combined	O
an	O
8-bit	O
version	O
of	O
the	O
transputer	B-General_Concept
CPU	B-General_Concept
with	O
configurable	O
logic	O
based	O
on	O
state	O
machines	O
.	O
</s>
<s>
The	O
transputer	B-General_Concept
instruction	O
set	O
is	O
based	O
on	O
8-bit	O
instructions	O
and	O
can	O
easily	O
be	O
used	O
with	O
any	O
word	O
size	O
which	O
is	O
a	O
multiple	O
of	O
8	O
bits	O
.	O
</s>
<s>
The	O
target	O
market	O
for	O
the	O
T100	O
was	O
to	O
be	O
bus	B-General_Concept
controllers	O
such	O
as	O
Futurebus	O
,	O
and	O
an	O
upgrade	O
for	O
the	O
standard	O
link	O
adapters	O
(	O
C011	O
etc	O
.	O
)	O
.	O
</s>
<s>
TPCORE	O
is	O
an	O
implementation	O
of	O
the	O
transputer	B-General_Concept
,	O
including	O
the	O
os-links	O
,	O
that	O
runs	O
in	O
a	O
FPGA	O
.	O
</s>
<s>
Inmos	O
improved	O
on	O
the	O
performance	O
of	O
the	O
T8	O
series	O
transputers	B-General_Concept
with	O
the	O
introduction	O
of	O
the	O
T9000	O
(	O
code-named	O
H1	O
during	O
development	O
)	O
.	O
</s>
<s>
The	O
T9000	O
shared	O
most	O
features	O
with	O
the	O
T800	O
,	O
but	O
moved	O
several	O
pieces	O
of	O
the	O
design	O
into	O
hardware	O
and	O
added	O
several	O
features	O
for	O
superscalar	B-General_Concept
support	O
.	O
</s>
<s>
Unlike	O
the	O
earlier	O
models	O
,	O
the	O
T9000	O
had	O
a	O
true	O
16KB	O
high-speed	O
cache	B-General_Concept
(	O
using	O
random	O
replacement	O
)	O
instead	O
of	O
RAM	B-Architecture
,	O
but	O
also	O
allowed	O
it	O
to	O
be	O
used	O
as	O
memory	O
and	O
included	O
MMU-like	O
functionality	O
to	O
handle	O
all	O
of	O
this	O
(	O
termed	O
the	O
PMI	O
)	O
.	O
</s>
<s>
An	O
interesting	O
addition	O
was	O
the	O
grouper	O
which	O
would	O
collect	O
instructions	O
out	O
of	O
the	O
cache	B-General_Concept
and	O
group	O
them	O
into	O
larger	O
packages	O
of	O
up	O
to	O
8	O
bytes	O
to	O
feed	O
the	O
pipeline	O
faster	O
.	O
</s>
<s>
Groups	O
then	O
completed	O
in	O
one	O
cycle	O
,	O
as	O
if	O
they	O
were	O
single	O
larger	O
instructions	O
working	O
on	O
a	O
faster	O
CPU	B-General_Concept
.	O
</s>
<s>
This	O
new	O
packet-based	O
link	O
protocol	O
was	O
called	O
DS-Link	O
,	O
and	O
later	O
formed	O
the	O
basis	O
of	O
the	O
IEEE	O
1355	O
serial	O
interconnect	B-General_Concept
standard	O
.	O
</s>
<s>
By	O
this	O
time	O
,	O
the	O
company	O
had	O
been	O
sold	O
to	O
SGS-Thomson	O
(	O
now	O
STMicroelectronics	O
)	O
,	O
whose	O
focus	O
was	O
the	O
embedded	B-Architecture
systems	I-Architecture
market	O
,	O
and	O
eventually	O
the	O
T9000	O
project	O
was	O
abandoned	O
.	O
</s>
<s>
However	O
,	O
a	O
comprehensively	O
redesigned	O
32-bit	O
transputer	B-General_Concept
intended	O
for	O
embedded	O
applications	O
,	O
the	O
ST20	O
series	O
,	O
was	O
later	O
produced	O
,	O
using	O
some	O
technology	O
developed	O
for	O
the	O
T9000	O
.	O
</s>
<s>
Although	O
not	O
strictly	O
a	O
transputer	B-General_Concept
,	O
the	O
ST20	O
was	O
heavily	O
influenced	O
by	O
the	O
T4	O
and	O
T9	O
and	O
formed	O
the	O
basis	O
of	O
the	O
T450	O
,	O
which	O
was	O
arguably	O
the	O
last	O
of	O
the	O
transputers	B-General_Concept
.	O
</s>
<s>
The	O
architecture	O
was	O
loosely	O
based	O
on	O
the	O
original	O
T4	O
architecture	O
with	O
a	O
microcode-controlled	O
data	O
path	O
.	O
</s>
<s>
However	O
,	O
it	O
was	O
a	O
full	O
redesign	O
,	O
using	O
VHDL	B-Language
as	O
the	O
design	O
language	O
and	O
with	O
an	O
optimized	O
(	O
and	O
rewritten	O
)	O
microcode	B-Device
compiler	O
.	O
</s>
<s>
Several	O
trial	O
designs	O
were	O
done	O
,	O
ranging	O
from	O
a	O
very	O
simple	O
RISC-style	O
CPU	B-General_Concept
with	O
complex	O
instructions	O
implemented	O
in	O
software	O
via	O
traps	O
to	O
a	O
rather	O
complex	O
superscalar	B-General_Concept
design	O
similar	O
in	O
concept	O
to	O
the	O
Tomasulo	B-General_Concept
algorithm	I-General_Concept
.	O
</s>
<s>
The	O
final	O
design	O
looked	O
very	O
similar	O
to	O
the	O
original	O
T4	O
core	O
although	O
some	O
simple	O
instruction	O
grouping	O
and	O
a	O
workspace	O
cache	B-General_Concept
were	O
added	O
to	O
help	O
with	O
performance	O
.	O
</s>
<s>
While	O
the	O
transputer	B-General_Concept
was	O
simple	O
but	O
powerful	O
compared	O
to	O
many	O
contemporary	O
designs	O
,	O
it	O
never	O
came	O
close	O
to	O
meeting	O
its	O
goal	O
of	O
being	O
used	O
universally	O
in	O
both	O
CPU	B-General_Concept
and	O
microcontroller	B-Architecture
roles	O
.	O
</s>
<s>
In	O
the	O
microcontroller	B-Architecture
market	O
,	O
the	O
market	O
was	O
dominated	O
by	O
8-bit	O
machines	O
where	O
cost	O
was	O
the	O
most	O
serious	O
consideration	O
.	O
</s>
<s>
In	O
the	O
computer	O
desktop	O
and	O
workstation	B-Device
field	O
,	O
the	O
transputer	B-General_Concept
was	O
fairly	O
fast	O
(	O
operating	O
at	O
about	O
10	O
million	O
instructions	O
per	O
second	O
(	O
MIPS	O
)	O
at	O
20MHz	O
)	O
.	O
</s>
<s>
This	O
was	O
excellent	O
performance	O
for	O
the	O
early	O
1980s	O
,	O
but	O
by	O
the	O
time	O
the	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
equipped	O
T800	O
was	O
shipping	O
,	O
other	O
RISC	B-Architecture
designs	O
had	O
surpassed	O
it	O
.	O
</s>
<s>
This	O
could	O
have	O
been	O
mitigated	O
to	O
a	O
large	O
extent	O
if	O
machines	O
had	O
used	O
multiple	O
transputers	B-General_Concept
as	O
planned	O
,	O
but	O
T800s	O
cost	O
about	O
$400	O
each	O
when	O
introduced	O
,	O
which	O
meant	O
a	O
poor	O
price/performance	O
ratio	O
.	O
</s>
<s>
Few	O
transputer-based	O
workstation	B-Device
systems	O
were	O
designed	O
;	O
the	O
most	O
notable	O
likely	O
being	O
the	O
Atari	B-Device
Transputer	I-Device
Workstation	I-Device
.	O
</s>
<s>
The	O
transputer	B-General_Concept
was	O
more	O
successful	O
in	O
the	O
field	O
of	O
massively	B-Operating_System
parallel	I-Operating_System
computing	I-Operating_System
,	O
where	O
several	O
vendors	O
produced	O
transputer-based	O
systems	O
in	O
the	O
late	O
1980s	O
.	O
</s>
<s>
These	O
included	O
Meiko	B-Device
Scientific	I-Device
(	O
founded	O
by	O
ex-Inmos	O
employees	O
)	O
,	O
Floating	B-Algorithm
Point	I-Algorithm
Systems	O
,	O
Parsytec	B-Device
,	O
and	O
Parsys	O
.	O
</s>
<s>
Several	O
British	O
academic	O
institutions	O
founded	O
research	O
activities	O
in	O
the	O
application	O
of	O
transputer-based	O
parallel	O
systems	O
,	O
including	O
Bristol	O
Polytechnic	O
's	O
Bristol	O
Transputer	B-General_Concept
Centre	O
and	O
the	O
University	O
of	O
Edinburgh	O
's	O
Edinburgh	B-Device
Concurrent	I-Device
Supercomputer	I-Device
Project	I-Device
.	O
</s>
<s>
Also	O
,	O
the	O
Data	B-Algorithm
Acquisition	I-Algorithm
and	O
Second	O
Level	O
Trigger	O
systems	O
of	O
the	O
High	O
Energy	O
Physics	O
ZEUS	O
Experiment	O
for	O
the	O
Hadron	O
Elektron	O
Ring	O
Anlage	O
(	O
HERA	O
)	O
collider	O
at	O
DESY	O
was	O
based	O
on	O
a	O
network	O
of	O
over	O
300	O
synchronously	O
clocked	O
transputers	B-General_Concept
divided	O
into	O
several	O
subsystems	O
.	O
</s>
<s>
The	O
parallel	B-Operating_System
processing	I-Operating_System
abilities	O
of	O
the	O
transputer	B-General_Concept
were	O
put	O
to	O
use	O
commercially	O
for	O
image	B-Algorithm
processing	I-Algorithm
by	O
the	O
world	O
's	O
largest	O
printing	O
company	O
,	O
RR	O
Donnelley	O
&	O
Sons	O
,	O
in	O
the	O
early	O
1990s	O
.	O
</s>
<s>
Within	O
a	O
few	O
years	O
,	O
the	O
processing	O
ability	O
of	O
even	O
desktop	O
computers	O
ended	O
the	O
need	O
for	O
custom	O
multi-processing	B-Operating_System
systems	O
for	O
the	O
firm	O
.	O
</s>
<s>
The	O
German	O
company	O
Jäger	O
Messtechnik	O
used	O
transputers	B-General_Concept
for	O
their	O
early	O
ADwin	O
real-time	B-General_Concept
data	B-Algorithm
acquisition	I-Algorithm
and	O
control	O
products	O
.	O
</s>
<s>
A	O
French	O
company	O
built	O
the	O
Archipel	O
Volvox	O
Supercomputer	B-Architecture
with	O
up	O
to	O
144	O
T800	O
and	O
T400	O
Transputers	B-General_Concept
.	O
</s>
<s>
It	O
was	O
controlled	O
by	O
a	O
Silicon	O
Graphics	O
Indigo2	O
running	O
UNIX	B-Application
and	O
a	O
special	O
card	O
that	O
interfaced	O
to	O
the	O
Volvox	O
backplanes	O
.	O
</s>
<s>
Transputers	B-General_Concept
also	O
found	O
use	O
in	O
protocol	O
analysers	O
such	O
as	O
the	O
Siemens/Tektronix	O
K1103	O
and	O
in	O
military	O
applications	O
where	O
the	O
array	O
architecture	O
suited	O
applications	O
such	O
as	O
radar	O
and	O
the	O
serial	B-Protocol
links	I-Protocol
(	O
that	O
were	O
high	O
speed	O
in	O
the	O
1980s	O
)	O
served	O
well	O
to	O
save	O
cost	O
and	O
weight	O
in	O
sub-system	O
communications	O
.	O
</s>
<s>
The	O
transputer	B-General_Concept
also	O
appeared	O
in	O
products	O
related	O
to	O
virtual	B-Application
reality	I-Application
such	O
as	O
the	O
ProVision	O
100	O
system	O
made	O
by	O
Division	O
Limited	O
of	O
Bristol	O
,	O
featuring	O
a	O
combination	O
of	O
Intel	B-General_Concept
i860	I-General_Concept
,	O
80486/33	O
and	O
Toshiba	O
HSP	O
processors	O
,	O
together	O
with	O
T805	O
or	O
T425	O
transputers	B-General_Concept
,	O
implementing	O
a	O
rendering	O
engine	O
that	O
could	O
then	O
be	O
accessed	O
as	O
a	O
server	B-Application
by	O
PC	B-Device
,	O
Sun	B-Device
SPARCstation	I-Device
or	O
VAX	B-Device
systems	O
.	O
</s>
<s>
The	O
field	O
of	O
asynchronous	O
algorithms	O
,	O
and	O
the	O
asynchronous	O
implementation	O
of	O
current	O
algorithms	O
,	O
is	O
likely	O
to	O
play	O
a	O
key	O
role	O
in	O
the	O
move	O
to	O
exascale	B-General_Concept
computing	I-General_Concept
.	O
</s>
<s>
The	O
High	O
Energy	O
Transient	O
Explorer	O
2	O
(	O
HETE-2	O
)	O
spacecraft	O
used	O
4×	O
T805	O
transputers	B-General_Concept
and	O
8×	O
DSP56001	O
yielding	O
about	O
100	O
million	O
instructions	O
per	O
second	O
(	O
MIPS	O
)	O
of	O
performance	O
.	O
</s>
<s>
Growing	O
internal	O
parallelism	B-Operating_System
has	O
been	O
one	O
driving	O
force	O
behind	O
improvements	O
in	O
conventional	O
CPU	B-General_Concept
designs	O
.	O
</s>
<s>
Instead	O
of	O
explicit	O
thread-level	O
parallelism	B-Operating_System
(	O
as	O
is	O
used	O
in	O
the	O
transputer	B-General_Concept
)	O
,	O
CPU	B-General_Concept
designs	O
exploited	O
implicit	O
parallelism	B-Operating_System
at	O
the	O
instruction-level	O
,	O
inspecting	O
code	O
sequences	O
for	O
data	O
dependencies	O
and	O
issuing	O
multiple	O
independent	O
instructions	O
to	O
different	O
execution	O
units	O
.	O
</s>
<s>
This	O
is	O
termed	O
superscalar	B-General_Concept
processing	O
.	O
</s>
<s>
Superscalar	B-General_Concept
processors	I-General_Concept
are	O
suited	O
for	O
optimising	O
the	O
execution	O
of	O
sequentially	O
constructed	O
fragments	O
of	O
code	O
.	O
</s>
<s>
The	O
combination	O
of	O
superscalar	B-General_Concept
processing	O
and	O
speculative	B-General_Concept
execution	I-General_Concept
delivered	O
a	O
tangible	O
performance	O
increase	O
on	O
existing	O
bodies	O
of	O
code	O
–	O
which	O
were	O
mostly	O
written	O
in	O
Pascal	B-Application
,	O
Fortran	B-Application
,	O
C	B-Language
and	O
C++	O
.	O
</s>
<s>
Given	O
these	O
substantial	O
and	O
regular	O
performance	O
improvements	O
to	O
existing	O
code	O
there	O
was	O
little	O
incentive	O
to	O
rewrite	O
software	O
in	O
languages	O
or	O
coding	O
styles	O
which	O
expose	O
more	O
task-level	O
parallelism	B-Operating_System
.	O
</s>
<s>
Nevertheless	O
,	O
the	O
model	O
of	O
cooperating	O
concurrent	B-Operating_System
processors	O
can	O
still	O
be	O
found	O
in	O
cluster	B-Architecture
computing	I-Architecture
systems	O
that	O
dominate	O
supercomputer	B-Architecture
design	O
in	O
the	O
21st	O
century	O
.	O
</s>
<s>
Unlike	O
the	O
transputer	B-General_Concept
architecture	O
,	O
the	O
processing	O
units	O
in	O
these	O
systems	O
typically	O
use	O
superscalar	B-General_Concept
CPUs	O
with	O
access	O
to	O
substantial	O
amounts	O
of	O
memory	O
and	O
disk	B-Device
storage	I-Device
,	O
running	O
conventional	O
operating	B-General_Concept
systems	I-General_Concept
and	O
network	O
interfaces	O
.	O
</s>
<s>
Resulting	O
from	O
the	O
more	O
complex	O
nodes	O
,	O
the	O
software	O
architecture	O
used	O
for	O
coordinating	O
the	O
parallelism	B-Operating_System
in	O
such	O
systems	O
is	O
typically	O
far	O
more	O
heavyweight	O
than	O
in	O
the	O
transputer	B-General_Concept
architecture	O
.	O
</s>
<s>
The	O
fundamental	O
transputer	B-General_Concept
motive	O
remains	O
,	O
yet	O
was	O
masked	O
for	O
over	O
20	O
years	O
by	O
the	O
repeated	O
doubling	O
of	O
transistor	B-Application
counts	O
.	O
</s>
<s>
Inevitably	O
,	O
microprocessor	B-Architecture
designers	O
finally	O
ran	O
out	O
of	O
uses	O
for	O
the	O
greater	O
physical	O
resources	O
,	O
almost	O
at	O
the	O
same	O
time	O
when	O
technology	O
scaling	O
began	O
to	O
hit	O
its	O
limits	O
.	O
</s>
<s>
The	O
most	O
powerful	O
supercomputers	B-Architecture
in	O
the	O
world	O
,	O
based	O
on	O
designs	O
from	O
Columbia	O
University	O
and	O
built	O
as	O
IBM	B-Operating_System
Blue	I-Operating_System
Gene	I-Operating_System
,	O
are	O
real-world	O
incarnations	O
of	O
the	O
transputer	B-General_Concept
dream	O
.	O
</s>
<s>
Recent	O
trends	O
have	O
also	O
tried	O
to	O
solve	O
the	O
transistor	B-Application
dilemma	O
in	O
ways	O
that	O
would	O
have	O
been	O
too	O
futuristic	O
even	O
for	O
Inmos	O
.	O
</s>
<s>
On	O
top	O
of	O
adding	O
components	O
to	O
the	O
CPU	B-General_Concept
die	O
and	O
placing	O
multiple	O
dies	O
in	O
one	O
system	O
,	O
modern	O
processors	O
increasingly	O
place	O
multiple	O
cores	O
in	O
one	O
die	O
.	O
</s>
<s>
The	O
transputer	B-General_Concept
designers	O
struggled	O
to	O
fit	O
even	O
one	O
core	O
into	O
its	O
transistor	B-Application
budget	O
.	O
</s>
<s>
Today	O
designers	O
,	O
working	O
with	O
a	O
1000-fold	O
increase	O
in	O
transistor	B-Application
densities	O
,	O
can	O
now	O
typically	O
place	O
many	O
.	O
</s>
<s>
One	O
of	O
the	O
most	O
recent	O
commercial	O
developments	O
has	O
emerged	O
from	O
the	O
firm	O
XMOS	O
,	O
which	O
has	O
developed	O
a	O
family	O
of	O
embedded	O
multi-core	O
multi-threaded	O
processors	O
which	O
resonate	O
strongly	O
with	O
the	O
transputer	B-General_Concept
and	O
Inmos	O
.	O
</s>
<s>
There	O
is	O
an	O
emerging	O
class	O
of	O
multicore/manycore	O
processors	O
taking	O
the	O
approach	O
of	O
a	O
network	O
on	O
a	O
chip	O
(	O
NoC	O
)	O
,	O
such	O
as	O
the	O
Cell	B-General_Concept
processor	I-General_Concept
,	O
Adapteva	B-Application
Epiphany	I-Application
architecture	O
,	O
Tilera	O
,	O
etc	O
.	O
</s>
<s>
The	O
transputer	B-General_Concept
and	O
Inmos	O
helped	O
establish	O
Bristol	O
,	O
UK	O
,	O
as	O
a	O
hub	O
for	O
microelectronic	O
design	O
and	O
innovation	O
.	O
</s>
