<s>
In	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
a	O
transport	B-General_Concept
triggered	I-General_Concept
architecture	I-General_Concept
(	O
TTA	O
)	O
is	O
a	O
kind	O
of	O
processor	O
design	O
in	O
which	O
programs	O
directly	O
control	O
the	O
internal	O
transport	B-General_Concept
buses	I-General_Concept
of	O
a	O
processor	O
.	O
</s>
<s>
Computation	O
happens	O
as	O
a	O
side	O
effect	O
of	O
data	O
transports	O
:	O
writing	O
data	O
into	O
a	O
triggering	O
port	O
of	O
a	O
functional	B-General_Concept
unit	I-General_Concept
triggers	O
the	O
functional	B-General_Concept
unit	I-General_Concept
to	O
start	O
a	O
computation	O
.	O
</s>
<s>
This	O
is	O
similar	O
to	O
what	O
happens	O
in	O
a	O
systolic	B-Architecture
array	I-Architecture
.	O
</s>
<s>
Due	O
to	O
its	O
modular	O
structure	O
,	O
TTA	O
is	O
an	O
ideal	O
processor	O
template	O
for	O
application-specific	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
processors	I-General_Concept
(	O
ASIP	O
)	O
with	O
customized	O
datapath	O
but	O
without	O
the	O
inflexibility	O
and	O
design	O
cost	O
of	O
fixed	O
function	O
hardware	O
accelerators	O
.	O
</s>
<s>
Typically	O
a	O
transport	O
triggered	O
processor	O
has	O
multiple	O
transport	B-General_Concept
buses	I-General_Concept
and	O
multiple	O
functional	B-General_Concept
units	I-General_Concept
connected	O
to	O
the	O
buses	B-General_Concept
,	O
which	O
provides	O
opportunities	O
for	O
instruction	B-Operating_System
level	I-Operating_System
parallelism	I-Operating_System
.	O
</s>
<s>
In	O
this	O
respect	O
(	O
and	O
obviously	O
due	O
to	O
the	O
large	O
instruction	O
word	O
width	O
)	O
,	O
the	O
TTA	O
architecture	O
resembles	O
the	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
architecture	O
.	O
</s>
<s>
For	O
example	O
,	O
software	O
can	O
transfer	O
data	O
directly	O
between	O
functional	B-General_Concept
units	I-General_Concept
without	O
using	O
registers	O
.	O
</s>
<s>
Transport	O
triggering	O
exposes	O
some	O
microarchitectural	B-General_Concept
details	O
that	O
are	O
normally	O
hidden	O
from	O
programmers	O
.	O
</s>
<s>
This	O
greatly	O
simplifies	O
the	O
control	O
logic	O
of	O
a	O
processor	O
,	O
because	O
many	O
decisions	O
normally	O
done	O
at	O
run	B-Library
time	I-Library
are	O
fixed	O
at	O
compile	B-Application
time	I-Application
.	O
</s>
<s>
The	O
binary	O
incompatibility	O
problem	O
,	O
in	O
addition	O
to	O
the	O
complexity	O
of	O
implementing	O
a	O
full	O
context	O
switch	O
,	O
makes	O
TTAs	O
more	O
suitable	O
for	O
embedded	B-Architecture
systems	I-Architecture
than	O
for	O
general	O
purpose	O
computing	O
.	O
</s>
<s>
Of	O
all	O
the	O
one-instruction	B-Application
set	I-Application
computer	I-Application
architectures	O
,	O
the	O
TTA	O
architecture	O
is	O
one	O
of	O
the	O
few	O
that	O
has	O
had	O
processors	O
based	O
on	O
it	O
built	O
,	O
and	O
the	O
only	O
one	O
that	O
has	O
processors	O
based	O
on	O
it	O
sold	O
commercially	O
.	O
</s>
<s>
TTAs	O
can	O
be	O
seen	O
as	O
"	O
exposed	O
datapath	O
"	O
VLIW	B-General_Concept
architectures	O
.	O
</s>
<s>
While	O
VLIW	B-General_Concept
is	O
programmed	O
using	O
operations	O
,	O
TTA	O
splits	O
the	O
operation	O
execution	O
to	O
multiple	O
move	O
operations	O
.	O
</s>
<s>
low	O
level	O
programming	O
model	O
enables	O
several	O
benefits	O
in	O
comparison	O
to	O
the	O
standard	O
VLIW	B-General_Concept
.	O
</s>
<s>
For	O
example	O
,	O
a	O
TTA	O
architecture	O
can	O
provide	O
more	O
parallelism	O
with	O
simpler	O
register	B-General_Concept
files	I-General_Concept
than	O
with	O
VLIW	B-General_Concept
.	O
</s>
<s>
As	O
the	O
programmer	O
is	O
in	O
control	O
of	O
the	O
timing	O
of	O
the	O
operand	O
and	O
result	O
data	O
transports	O
,	O
the	O
complexity	O
(	O
the	O
number	O
of	O
input	O
and	O
output	O
ports	O
)	O
of	O
the	O
register	B-General_Concept
file	I-General_Concept
(	O
RF	O
)	O
need	O
not	O
be	O
scaled	O
according	O
to	O
the	O
worst	O
case	O
issue/completion	O
scenario	O
of	O
the	O
multiple	O
parallel	O
instructions	O
.	O
</s>
<s>
In	O
case	O
of	O
software	O
bypassing	O
,	O
the	O
programmer	O
bypasses	O
the	O
register	B-General_Concept
file	I-General_Concept
write	O
back	O
by	O
moving	O
data	O
directly	O
to	O
the	O
next	O
functional	B-General_Concept
unit	I-General_Concept
's	O
operand	O
ports	O
.	O
</s>
<s>
When	O
this	O
optimization	O
is	O
applied	O
aggressively	O
,	O
the	O
original	O
move	O
that	O
transports	O
the	O
result	O
to	O
the	O
register	B-General_Concept
file	I-General_Concept
can	O
be	O
eliminated	O
completely	O
,	O
thus	O
reducing	O
both	O
the	O
register	B-General_Concept
file	I-General_Concept
port	O
pressure	O
and	O
freeing	O
a	O
general	O
purpose	O
register	O
for	O
other	O
temporary	O
variables	O
.	O
</s>
<s>
The	O
reduced	O
register	O
pressure	O
,	O
in	O
addition	O
to	O
simplifying	O
the	O
required	O
complexity	O
of	O
the	O
RF	O
hardware	O
,	O
can	O
lead	O
to	O
significant	O
CPU	O
energy	O
savings	O
,	O
an	O
important	O
benefit	O
especially	O
in	O
mobile	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
TTA	O
processors	O
are	O
built	O
of	O
independent	O
function	O
units	O
and	O
register	B-General_Concept
files	I-General_Concept
,	O
which	O
are	O
connected	O
with	O
transport	B-General_Concept
buses	I-General_Concept
and	O
sockets	O
.	O
</s>
<s>
Each	O
function	O
unit	O
may	O
have	O
an	O
independent	O
pipeline	B-General_Concept
.	O
</s>
<s>
In	O
case	O
a	O
function	O
unit	O
is	O
fully	B-General_Concept
pipelined	I-General_Concept
,	O
a	O
new	O
operation	O
that	O
takes	O
multiple	O
clock	O
cycles	O
to	O
finish	O
can	O
be	O
started	O
in	O
every	O
clock	O
cycle	O
.	O
</s>
<s>
On	O
the	O
other	O
hand	O
,	O
a	O
pipeline	B-General_Concept
can	O
be	O
such	O
that	O
it	O
does	O
not	O
always	O
accept	O
new	O
operation	O
start	O
requests	O
while	O
an	O
old	O
one	O
is	O
still	O
executing	O
.	O
</s>
<s>
Data	B-General_Concept
memory	I-General_Concept
access	O
and	O
communication	O
to	O
outside	O
of	O
the	O
processor	O
is	O
handled	O
by	O
using	O
special	O
function	O
units	O
.	O
</s>
<s>
Function	O
units	O
that	O
implement	O
memory	O
accessing	O
operations	O
and	O
connect	O
to	O
a	O
memory	O
module	O
are	O
often	O
called	O
load/store	B-Architecture
units	I-Architecture
.	O
</s>
<s>
A	O
control	O
unit	O
usually	O
has	O
an	O
instruction	B-General_Concept
pipeline	I-General_Concept
,	O
which	O
consists	O
of	O
stages	O
for	O
fetching	O
,	O
decoding	O
and	O
executing	O
program	O
instructions	O
.	O
</s>
<s>
Register	B-General_Concept
files	I-General_Concept
contain	O
general	O
purpose	O
registers	O
,	O
which	O
are	O
used	O
to	O
store	O
variables	O
in	O
programs	O
.	O
</s>
<s>
Like	O
function	O
units	O
,	O
also	O
register	B-General_Concept
files	I-General_Concept
have	O
input	O
and	O
output	O
ports	O
.	O
</s>
<s>
The	O
number	O
of	O
read	O
and	O
write	O
ports	O
,	O
that	O
is	O
,	O
the	O
capability	O
of	O
being	O
able	O
to	O
read	O
and	O
write	O
multiple	O
registers	O
in	O
a	O
same	O
clock	O
cycle	O
,	O
can	O
vary	O
in	O
each	O
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
Interconnect	B-General_Concept
architecture	O
consists	O
of	O
transport	B-General_Concept
buses	I-General_Concept
which	O
are	O
connected	O
to	O
function	O
unit	O
ports	O
by	O
means	O
of	O
sockets	O
.	O
</s>
<s>
Due	O
to	O
expense	O
of	O
connectivity	O
,	O
it	O
is	O
usual	O
to	O
reduce	O
the	O
number	O
of	O
connections	O
between	O
units	O
(	O
function	O
units	O
and	O
register	B-General_Concept
files	I-General_Concept
)	O
.	O
</s>
<s>
Some	O
TTA	O
implementations	O
support	O
conditional	B-Language
execution	O
.	O
</s>
<s>
Conditional	B-Language
execution	O
is	O
implemented	O
with	O
the	O
aid	O
of	O
guards	O
.	O
</s>
<s>
Each	O
data	O
transport	O
can	O
be	O
conditionalized	O
by	O
a	O
guard	O
,	O
which	O
is	O
connected	O
to	O
a	O
register	O
(	O
often	O
a	O
1-bit	O
conditional	B-General_Concept
register	I-General_Concept
)	O
and	O
to	O
a	O
bus	O
.	O
</s>
<s>
All	O
processors	O
,	O
including	O
TTA	O
processors	O
,	O
include	O
control	O
flow	O
instructions	O
that	O
alter	O
the	O
program	B-General_Concept
counter	I-General_Concept
,	O
which	O
are	O
used	O
to	O
implement	O
subroutines	O
,	O
if-then-else	B-Language
,	O
for-loop	B-Language
,	O
etc	O
.	O
</s>
<s>
The	O
assembly	O
language	O
for	O
TTA	O
processors	O
typically	O
includes	O
control	O
flow	O
instructions	O
such	O
as	O
unconditional	O
branches	O
(	O
JUMP	O
)	O
,	O
conditional	B-Language
relative	O
branches	O
(	O
BNZ	O
)	O
,	O
subroutine	O
call	O
(	O
CALL	O
)	O
,	O
conditional	B-Language
return	O
(	O
RETNZ	O
)	O
,	O
etc	O
.	O
</s>
<s>
TTA	O
implementations	O
that	O
support	O
conditional	B-Language
execution	O
,	O
such	O
as	O
the	O
sTTAck	O
and	O
the	O
first	O
MOVE	O
prototype	O
,	O
can	O
implement	O
most	O
of	O
these	O
control	O
flow	O
instructions	O
as	O
a	O
conditional	B-Language
move	O
to	O
the	O
program	B-General_Concept
counter	I-General_Concept
.	O
</s>
<s>
TTA	O
implementations	O
that	O
only	O
support	O
unconditional	O
data	O
transports	O
,	O
such	O
as	O
the	O
Maxim	O
Integrated	O
MAXQ	O
,	O
typically	O
have	O
a	O
special	O
function	O
unit	O
tightly	O
connected	O
to	O
the	O
program	B-General_Concept
counter	I-General_Concept
that	O
responds	O
to	O
a	O
variety	O
of	O
destination	O
addresses	O
.	O
</s>
<s>
Each	O
such	O
address	O
,	O
when	O
used	O
as	O
the	O
destination	O
of	O
a	O
"	O
move	O
"	O
,	O
has	O
a	O
different	O
effect	O
on	O
the	O
program	B-General_Concept
counter	I-General_Concept
—	O
each	O
"	O
relative	O
branch	O
condition	O
"	O
instruction	O
has	O
a	O
different	O
destination	O
address	O
for	O
each	O
condition	O
;	O
and	O
other	O
destination	O
addresses	O
are	O
used	O
CALL	O
,	O
RETNZ	O
,	O
etc	O
.	O
</s>
<s>
a	O
data	O
transport	O
from	O
function	O
unit	O
F	O
,	O
port	O
1	O
,	O
to	O
register	B-General_Concept
file	I-General_Concept
R	O
,	O
register	O
index	O
2	O
,	O
should	O
take	O
place	O
in	O
bus	O
B1	O
.	O
</s>
<s>
are	O
multiple	O
buses	B-General_Concept
in	O
the	O
target	O
processor	O
,	O
each	O
bus	O
can	O
be	O
utilized	O
in	O
parallel	O
in	O
the	O
same	O
clock	O
cycle	O
.	O
</s>
<s>
The	O
ports	O
associated	O
with	O
the	O
ALU	O
may	O
act	O
as	O
an	O
accumulator	B-General_Concept
,	O
allowing	O
creation	O
of	O
macro	O
instructions	O
that	O
abstract	B-Application
away	I-Application
the	O
underlying	O
TTA	O
:	O
</s>
<s>
One	O
of	O
them	O
is	O
delay	B-General_Concept
slots	I-General_Concept
,	O
the	O
programmer	O
visible	O
operation	O
latency	O
of	O
the	O
function	O
units	O
.	O
</s>
<s>
When	O
triggering	O
the	O
add	O
operation	O
,	O
it	O
is	O
possible	O
to	O
read	O
the	O
result	O
in	O
the	O
next	B-General_Concept
instruction	I-General_Concept
(	O
next	O
clock	O
cycle	O
)	O
,	O
but	O
in	O
case	O
of	O
mul	O
,	O
one	O
has	O
to	O
wait	O
for	O
two	O
instructions	O
before	O
the	O
result	O
can	O
be	O
read	O
.	O
</s>
<s>
Due	O
to	O
the	O
abundance	O
of	O
programmer-visible	O
processor	O
context	O
which	O
practically	O
includes	O
,	O
in	O
addition	O
to	O
register	B-General_Concept
file	I-General_Concept
contents	O
,	O
also	O
function	O
unit	O
pipeline	B-General_Concept
register	O
contents	O
and/or	O
function	O
unit	O
input	O
and	O
output	O
ports	O
,	O
context	O
saves	O
required	O
for	O
external	O
interrupt	O
support	O
can	O
become	O
complex	O
and	O
expensive	O
to	O
implement	O
in	O
a	O
TTA	O
processor	O
.	O
</s>
<s>
MAXQ	O
from	O
Maxim	O
Integrated	O
,	O
the	O
only	O
commercially	O
available	O
microcontroller	O
built	O
upon	O
transport	B-General_Concept
triggered	I-General_Concept
architecture	I-General_Concept
,	O
is	O
an	O
OISC	O
or	O
"	O
one-instruction	B-Application
set	I-Application
computer	I-Application
"	O
.	O
</s>
<s>
It	O
offers	O
a	O
single	O
though	O
flexible	O
MOVE	O
instruction	O
,	O
which	O
can	O
then	O
function	O
as	O
various	O
virtual	O
instructions	O
by	O
moving	O
values	O
directly	O
to	O
the	O
program	B-General_Concept
counter	I-General_Concept
.	O
</s>
<s>
The	O
architecture	O
of	O
the	O
Amiga	O
Copper	O
has	O
all	O
the	O
basic	O
features	O
of	O
a	O
transport	B-General_Concept
triggered	I-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
Mali	B-General_Concept
(	O
200/400	O
)	O
vertex	O
processor	O
,	O
uses	O
a	O
128-bit	O
instruction	O
word	O
single	O
precision	O
floating-point	O
scalar	O
TTA	O
.	O
</s>
