<s>
The	O
Efficeon	B-General_Concept
processor	O
is	O
Transmeta	O
's	O
second-generation	O
256-bit	O
VLIW	B-General_Concept
design	O
released	O
in	O
2004	O
which	O
employs	O
a	O
software	O
engine	O
Code	B-Application
Morphing	I-Application
Software	I-Application
(	O
CMS	O
)	O
to	O
convert	O
code	O
written	O
for	O
x86	B-Operating_System
processors	O
to	O
the	O
native	O
instruction	B-General_Concept
set	I-General_Concept
of	O
the	O
chip	O
.	O
</s>
<s>
Like	O
its	O
predecessor	O
,	O
the	O
Transmeta	B-General_Concept
Crusoe	I-General_Concept
(	O
a	O
128-bit	O
VLIW	B-General_Concept
architecture	O
)	O
,	O
Efficeon	B-General_Concept
stresses	O
computational	O
efficiency	O
,	O
low	O
power	O
consumption	O
,	O
and	O
a	O
low	O
thermal	O
footprint	O
.	O
</s>
<s>
Efficeon	B-General_Concept
most	O
closely	O
mirrors	O
the	O
feature	O
set	O
of	O
Intel	B-General_Concept
Pentium	I-General_Concept
4	I-General_Concept
processors	O
,	O
although	O
,	O
like	O
AMD	B-General_Concept
Opteron	I-General_Concept
processors	O
,	O
it	O
supports	O
a	O
fully	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
,	O
a	O
HyperTransport	B-Device
IO	O
bus	O
,	O
and	O
the	O
NX	B-General_Concept
bit	I-General_Concept
,	O
or	O
no-execute	O
x86	B-Operating_System
extension	O
to	O
PAE	B-General_Concept
mode	I-General_Concept
.	O
</s>
<s>
NX	B-General_Concept
bit	I-General_Concept
support	O
is	O
available	O
starting	O
with	O
CMS	O
version	O
6.0.4	O
.	O
</s>
<s>
Efficeon	B-General_Concept
's	O
computational	O
performance	O
relative	O
to	O
mobile	O
CPUs	O
like	O
the	O
Intel	B-Architecture
Pentium	I-Architecture
M	I-Architecture
is	O
thought	O
to	O
be	O
lower	O
,	O
although	O
little	O
appears	O
to	O
be	O
published	O
about	O
the	O
relative	O
performance	O
of	O
these	O
competing	O
processors	O
.	O
</s>
<s>
Efficeon	B-General_Concept
came	O
in	O
two	O
package	B-Algorithm
types	O
:	O
a	O
783	O
-	O
and	O
a	O
592-contact	O
ball	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
BGA	O
)	O
.	O
</s>
<s>
Internally	O
,	O
the	O
Efficeon	B-General_Concept
has	O
two	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
,	O
two	O
load/store/add	O
units	O
,	O
two	O
execute	O
units	O
,	O
two	O
floating-point/MMX/SSE/SSE2	O
units	O
,	O
one	O
branch	B-General_Concept
prediction	I-General_Concept
unit	I-General_Concept
,	O
one	O
alias	O
unit	O
,	O
and	O
one	O
control	O
unit	O
.	O
</s>
<s>
The	O
VLIW	B-General_Concept
core	O
can	O
execute	O
a	O
256-bit	O
VLIW	B-General_Concept
instruction	O
per	O
cycle	O
,	O
which	O
is	O
called	O
a	O
molecule	O
and	O
has	O
room	O
to	O
store	O
eight	O
32-bit	O
instructions	O
(	O
called	O
atoms	O
)	O
per	O
cycle	O
.	O
</s>
<s>
The	O
Efficeon	B-General_Concept
has	O
a	O
128	O
KB	O
L1	O
instruction	O
cache	O
,	O
a	O
64	O
KB	O
L1	O
data	O
cache	O
and	O
a	O
1	O
MB	O
L2	O
cache	O
.	O
</s>
<s>
Additionally	O
the	O
Efficeon	B-General_Concept
CMS	O
(	O
code	B-Application
morphing	I-Application
software	I-Application
)	O
reserves	O
a	O
small	O
portion	O
of	O
main	O
memory	O
(	O
typically	O
32	O
MB	O
)	O
for	O
its	O
translation	O
cache	O
of	O
dynamically	O
translated	O
x86	B-Operating_System
instructions	O
.	O
</s>
