<s>
A	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
is	O
a	O
memory	O
cache	B-General_Concept
that	O
stores	O
the	O
recent	O
translations	O
of	O
virtual	B-Architecture
memory	I-Architecture
to	O
physical	O
memory	O
.	O
</s>
<s>
It	O
can	O
be	O
called	O
an	O
address-translation	O
cache	B-General_Concept
.	O
</s>
<s>
It	O
is	O
a	O
part	O
of	O
the	O
chip	O
's	O
memory-management	B-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
.	O
</s>
<s>
A	O
TLB	O
may	O
reside	O
between	O
the	O
CPU	B-General_Concept
and	O
the	O
CPU	B-General_Concept
cache	I-General_Concept
,	O
between	O
CPU	B-General_Concept
cache	I-General_Concept
and	O
the	O
main	O
memory	O
or	O
between	O
the	O
different	O
levels	O
of	O
the	O
multi-level	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
majority	O
of	O
desktop	O
,	O
laptop	O
,	O
and	O
server	O
processors	O
include	O
one	O
or	O
more	O
TLBs	O
in	O
the	O
memory-management	O
hardware	O
,	O
and	O
it	O
is	O
nearly	O
always	O
present	O
in	O
any	O
processor	O
that	O
utilizes	O
paged	B-Architecture
or	O
segmented	B-General_Concept
virtual	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
The	O
TLB	O
is	O
sometimes	O
implemented	O
as	O
content-addressable	B-Data_Structure
memory	I-Data_Structure
(	O
CAM	B-Data_Structure
)	O
.	O
</s>
<s>
The	O
CAM	B-Data_Structure
search	O
key	O
is	O
the	O
virtual	B-General_Concept
address	I-General_Concept
,	O
and	O
the	O
search	O
result	O
is	O
a	O
physical	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
If	O
the	O
requested	O
address	O
is	O
present	O
in	O
the	O
TLB	O
,	O
the	O
CAM	B-Data_Structure
search	O
yields	O
a	O
match	O
quickly	O
and	O
the	O
retrieved	O
physical	B-General_Concept
address	I-General_Concept
can	O
be	O
used	O
to	O
access	O
memory	O
.	O
</s>
<s>
If	O
the	O
requested	O
address	O
is	O
not	O
in	O
the	O
TLB	O
,	O
it	O
is	O
a	O
miss	O
,	O
and	O
the	O
translation	O
proceeds	O
by	O
looking	O
up	O
the	O
page	B-General_Concept
table	I-General_Concept
in	O
a	O
process	O
called	O
a	O
page	O
walk	O
.	O
</s>
<s>
The	O
page	O
walk	O
is	O
time-consuming	O
when	O
compared	O
to	O
the	O
processor	O
speed	O
,	O
as	O
it	O
involves	O
reading	O
the	O
contents	O
of	O
multiple	O
memory	O
locations	O
and	O
using	O
them	O
to	O
compute	O
the	O
physical	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
After	O
the	O
physical	B-General_Concept
address	I-General_Concept
is	O
determined	O
by	O
the	O
page	O
walk	O
,	O
the	O
virtual	B-General_Concept
address	I-General_Concept
to	O
physical	B-General_Concept
address	I-General_Concept
mapping	O
is	O
entered	O
into	O
the	O
TLB	O
.	O
</s>
<s>
A	O
TLB	O
has	O
a	O
fixed	O
number	O
of	O
slots	O
containing	O
page-table	B-General_Concept
entries	O
and	O
segment-table	O
entries	O
;	O
page-table	B-General_Concept
entries	O
map	O
virtual	O
addresses	O
to	O
physical	O
addresses	O
and	O
intermediate-table	O
addresses	O
,	O
while	O
segment-table	O
entries	O
map	O
virtual	O
addresses	O
to	O
segment	O
addresses	O
,	O
intermediate-table	O
addresses	O
and	O
page-table	B-General_Concept
addresses	O
.	O
</s>
<s>
The	O
virtual	B-Architecture
memory	I-Architecture
is	O
the	O
memory	O
space	O
as	O
seen	O
from	O
a	O
process	O
;	O
this	O
space	O
is	O
often	O
split	O
into	O
pages	B-General_Concept
of	O
a	O
fixed	O
size	O
(	O
in	O
paged	B-Architecture
memory	I-Architecture
)	O
,	O
or	O
less	O
commonly	O
into	O
segments	B-General_Concept
of	O
variable	O
sizes	O
(	O
in	O
segmented	B-General_Concept
memory	I-General_Concept
)	O
.	O
</s>
<s>
The	O
page	B-General_Concept
table	I-General_Concept
,	O
generally	O
stored	O
in	O
main	O
memory	O
,	O
keeps	O
track	O
of	O
where	O
the	O
virtual	B-General_Concept
pages	I-General_Concept
are	O
stored	O
in	O
the	O
physical	O
memory	O
.	O
</s>
<s>
This	O
method	O
uses	O
two	O
memory	O
accesses	O
(	O
one	O
for	O
the	O
page-table	B-General_Concept
entry	O
,	O
one	O
for	O
the	O
byte	O
)	O
to	O
access	O
a	O
byte	O
.	O
</s>
<s>
First	O
,	O
the	O
page	B-General_Concept
table	I-General_Concept
is	O
looked	O
up	O
for	O
the	O
frame	O
number	O
.	O
</s>
<s>
Thus	O
any	O
straightforward	O
virtual	B-Architecture
memory	I-Architecture
scheme	O
would	O
have	O
the	O
effect	O
of	O
doubling	O
the	O
memory	O
access	O
time	O
.	O
</s>
<s>
Hence	O
,	O
the	O
TLB	O
is	O
used	O
to	O
reduce	O
the	O
time	O
taken	O
to	O
access	O
the	O
memory	O
locations	O
in	O
the	O
page-table	B-General_Concept
method	O
.	O
</s>
<s>
The	O
TLB	O
is	O
a	O
cache	B-General_Concept
of	O
the	O
page	B-General_Concept
table	I-General_Concept
,	O
representing	O
only	O
a	O
subset	O
of	O
the	O
page-table	B-General_Concept
contents	O
.	O
</s>
<s>
Referencing	O
the	O
physical	O
memory	O
addresses	O
,	O
a	O
TLB	O
may	O
reside	O
between	O
the	O
CPU	B-General_Concept
and	O
the	O
CPU	B-General_Concept
cache	I-General_Concept
,	O
between	O
the	O
CPU	B-General_Concept
cache	I-General_Concept
and	O
primary	O
storage	O
memory	O
,	O
or	O
between	O
levels	O
of	O
a	O
multi-level	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
placement	O
determines	O
whether	O
the	O
cache	B-General_Concept
uses	O
physical	O
or	O
virtual	B-General_Concept
addressing	I-General_Concept
.	O
</s>
<s>
If	O
the	O
cache	B-General_Concept
is	O
virtually	O
addressed	O
,	O
requests	O
are	O
sent	O
directly	O
from	O
the	O
CPU	B-General_Concept
to	O
the	O
cache	B-General_Concept
,	O
and	O
the	O
TLB	O
is	O
accessed	O
only	O
on	O
a	O
cache	B-General_Concept
miss	O
.	O
</s>
<s>
If	O
the	O
cache	B-General_Concept
is	O
physically	O
addressed	O
,	O
the	O
CPU	B-General_Concept
does	O
a	O
TLB	O
lookup	O
on	O
every	O
memory	O
operation	O
,	O
and	O
the	O
resulting	O
physical	B-General_Concept
address	I-General_Concept
is	O
sent	O
to	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
In	O
a	O
Harvard	B-Architecture
architecture	I-Architecture
or	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
,	O
a	O
separate	O
virtual	B-General_Concept
address	I-General_Concept
space	I-General_Concept
or	O
memory-access	O
hardware	O
may	O
exist	O
for	O
instructions	O
and	O
data	O
.	O
</s>
<s>
This	O
can	O
lead	O
to	O
distinct	O
TLBs	O
for	O
each	O
access	O
type	O
,	O
an	O
instruction	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
ITLB	B-Architecture
)	O
and	O
a	O
data	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
DTLB	B-Architecture
)	O
.	O
</s>
<s>
The	O
TLB	O
can	O
be	O
used	O
as	O
a	O
fast	O
lookup	O
hardware	O
cache	B-General_Concept
.	O
</s>
<s>
If	O
the	O
tag	O
of	O
the	O
incoming	O
virtual	B-General_Concept
address	I-General_Concept
matches	O
the	O
tag	O
in	O
the	O
TLB	O
,	O
the	O
corresponding	O
value	O
is	O
returned	O
.	O
</s>
<s>
A	O
common	O
optimization	O
for	O
physically	O
addressed	O
caches	O
is	O
to	O
perform	O
the	O
TLB	O
lookup	O
in	O
parallel	O
with	O
the	O
cache	B-General_Concept
access	O
.	O
</s>
<s>
If	O
the	O
page	O
number	O
is	O
not	O
in	O
the	O
TLB	O
,	O
the	O
page	B-General_Concept
table	I-General_Concept
must	O
be	O
checked	O
.	O
</s>
<s>
Depending	O
on	O
the	O
CPU	B-General_Concept
,	O
this	O
can	O
be	O
done	O
automatically	O
using	O
a	O
hardware	O
or	O
using	O
an	O
interrupt	O
to	O
the	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
;	O
see	O
the	O
address	O
translation	O
section	O
in	O
the	O
cache	B-General_Concept
article	O
for	O
more	O
details	O
about	O
virtual	B-General_Concept
addressing	I-General_Concept
as	O
it	O
pertains	O
to	O
caches	O
and	O
TLBs	O
.	O
</s>
<s>
The	O
CPU	B-General_Concept
has	O
to	O
access	O
main	O
memory	O
for	O
an	O
instruction-cache	O
miss	O
,	O
data-cache	O
miss	O
,	O
or	O
TLB	O
miss	O
.	O
</s>
<s>
The	O
third	O
case	O
(	O
the	O
simplest	O
one	O
)	O
is	O
where	O
the	O
desired	O
information	O
itself	O
actually	O
is	O
in	O
a	O
cache	B-General_Concept
,	O
but	O
the	O
information	O
for	O
virtual-to-physical	O
translation	O
is	O
not	O
in	O
a	O
TLB	O
.	O
</s>
<s>
Indeed	O
,	O
a	O
TLB	O
miss	O
can	O
be	O
more	O
expensive	O
than	O
an	O
instruction	O
or	O
data	B-General_Concept
cache	I-General_Concept
miss	O
,	O
due	O
to	O
the	O
need	O
for	O
not	O
just	O
a	O
load	O
from	O
main	O
memory	O
,	O
but	O
a	O
page	O
walk	O
,	O
requiring	O
several	O
memory	O
accesses	O
.	O
</s>
<s>
If	O
it	O
is	O
a	O
TLB	O
miss	O
,	O
then	O
the	O
CPU	B-General_Concept
checks	O
the	O
page	B-General_Concept
table	I-General_Concept
for	O
the	O
page	B-General_Concept
table	I-General_Concept
entry	O
.	O
</s>
<s>
If	O
the	O
present	O
bit	O
is	O
set	O
,	O
then	O
the	O
page	O
is	O
in	O
main	O
memory	O
,	O
and	O
the	O
processor	O
can	O
retrieve	O
the	O
frame	O
number	O
from	O
the	O
page-table	B-General_Concept
entry	O
to	O
form	O
the	O
physical	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
The	O
processor	O
also	O
updates	O
the	O
TLB	O
to	O
include	O
the	O
new	O
page-table	B-General_Concept
entry	O
.	O
</s>
<s>
Finally	O
,	O
if	O
the	O
present	O
bit	O
is	O
not	O
set	O
,	O
then	O
the	O
desired	O
page	O
is	O
not	O
in	O
the	O
main	O
memory	O
,	O
and	O
a	O
page	B-General_Concept
fault	I-General_Concept
is	O
issued	O
.	O
</s>
<s>
If	O
the	O
page	O
working	B-General_Concept
set	I-General_Concept
does	O
not	O
fit	O
into	O
the	O
TLB	O
,	O
then	O
TLB	O
thrashing	B-General_Concept
occurs	O
,	O
where	O
frequent	O
TLB	O
misses	O
occur	O
,	O
with	O
each	O
newly	O
cached	O
page	O
displacing	O
one	O
that	O
will	O
soon	O
be	O
used	O
again	O
,	O
degrading	O
performance	O
in	O
exactly	O
the	O
same	O
way	O
as	O
thrashing	B-General_Concept
of	O
the	O
instruction	O
or	O
data	B-General_Concept
cache	I-General_Concept
does	O
.	O
</s>
<s>
TLB	O
thrashing	B-General_Concept
can	O
occur	O
even	O
if	O
instruction-cache	O
or	O
data-cache	O
thrashing	B-General_Concept
are	O
not	O
occurring	O
,	O
because	O
these	O
are	O
cached	O
in	O
different-size	O
units	O
.	O
</s>
<s>
Instructions	O
and	O
data	O
are	O
cached	O
in	O
small	O
blocks	O
(	O
cache	B-General_Concept
lines	I-General_Concept
)	O
,	O
not	O
entire	O
pages	B-General_Concept
,	O
but	O
address	O
lookup	O
is	O
done	O
at	O
the	O
page	O
level	O
.	O
</s>
<s>
Thus	O
even	O
if	O
the	O
code	O
and	O
data	O
working	B-General_Concept
sets	I-General_Concept
fit	O
into	O
cache	B-General_Concept
,	O
if	O
the	O
working	B-General_Concept
sets	I-General_Concept
are	O
fragmented	O
across	O
many	O
pages	B-General_Concept
,	O
the	O
virtual-address	O
working	B-General_Concept
set	I-General_Concept
may	O
not	O
fit	O
into	O
TLB	O
,	O
causing	O
TLB	O
thrashing	B-General_Concept
.	O
</s>
<s>
Appropriate	O
sizing	O
of	O
the	O
TLB	O
thus	O
requires	O
considering	O
not	O
only	O
the	O
size	O
of	O
the	O
corresponding	O
instruction	O
and	O
data	B-General_Concept
caches	I-General_Concept
,	O
but	O
also	O
how	O
these	O
are	O
fragmented	O
across	O
multiple	O
pages	B-General_Concept
.	O
</s>
<s>
When	O
instruction-TLB	O
(	O
ITLB	B-Architecture
)	O
and	O
data-TLB	O
(	O
DTLB	B-Architecture
)	O
are	O
used	O
,	O
a	O
CPU	B-General_Concept
can	O
have	O
three	O
(	O
ITLB1	O
,	O
DTLB1	O
,	O
TLB2	O
)	O
or	O
four	O
TLBs	O
.	O
</s>
<s>
For	O
instance	O
,	O
Intel	O
's	O
Nehalem	B-Device
microarchitecture	I-Device
has	O
a	O
four-way	O
set	O
associative	O
L1	O
DTLB	B-Architecture
with	O
64	O
entries	O
for	O
4KiB	O
pages	B-General_Concept
and	O
32	O
entries	O
for	O
2/4MiB	O
pages	B-General_Concept
,	O
an	O
L1	O
ITLB	B-Architecture
with	O
128	O
entries	O
for	O
4KiB	O
pages	B-General_Concept
using	O
four-way	O
associativity	O
and	O
14	O
fully	O
associative	O
entries	O
for	O
2/4MiB	O
pages	B-General_Concept
(	O
both	O
parts	O
of	O
the	O
ITLB	B-Architecture
divided	O
statically	O
between	O
two	O
threads	O
)	O
and	O
a	O
unified	O
512-entry	O
L2	O
TLB	O
for	O
4KiB	O
pages	B-General_Concept
,	O
both	O
4-way	O
associative	O
.	O
</s>
<s>
Some	O
TLBs	O
may	O
have	O
separate	O
sections	O
for	O
small	O
pages	B-General_Concept
and	O
huge	O
pages	B-General_Concept
.	O
</s>
<s>
For	O
example	O
,	O
Intel	B-Architecture
Skylake	I-Architecture
microarchitecture	O
separates	O
the	O
TLB	O
entries	O
for	O
1GiB	O
pages	B-General_Concept
from	O
those	O
for	O
4KiB/2MiB	O
pages	B-General_Concept
.	O
</s>
<s>
With	O
hardware	O
TLB	O
management	O
,	O
the	O
CPU	B-General_Concept
automatically	O
walks	O
the	O
page	B-General_Concept
tables	I-General_Concept
(	O
using	O
the	O
CR3	O
register	O
on	O
x86	B-Operating_System
,	O
for	O
instance	O
)	O
to	O
see	O
whether	O
there	O
is	O
a	O
valid	O
page-table	B-General_Concept
entry	O
for	O
the	O
specified	O
virtual	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
If	O
the	O
CPU	B-General_Concept
finds	O
no	O
valid	O
entry	O
for	O
the	O
virtual	B-General_Concept
address	I-General_Concept
in	O
the	O
page	B-General_Concept
tables	I-General_Concept
,	O
it	O
raises	O
a	O
page	B-General_Concept
fault	I-General_Concept
exception	B-General_Concept
,	O
which	O
the	O
operating	B-General_Concept
system	I-General_Concept
must	O
handle	O
.	O
</s>
<s>
Handling	O
page	B-General_Concept
faults	I-General_Concept
usually	O
involves	O
bringing	O
the	O
requested	O
data	O
into	O
physical	O
memory	O
,	O
setting	O
up	O
a	O
page	B-General_Concept
table	I-General_Concept
entry	O
to	O
map	O
the	O
faulting	O
virtual	B-General_Concept
address	I-General_Concept
to	O
the	O
correct	O
physical	B-General_Concept
address	I-General_Concept
,	O
and	O
resuming	O
the	O
program	O
.	O
</s>
<s>
With	O
a	O
hardware-managed	O
TLB	O
,	O
the	O
format	O
of	O
the	O
TLB	O
entries	O
is	O
not	O
visible	O
to	O
software	O
and	O
can	O
change	O
from	O
CPU	B-General_Concept
to	O
CPU	B-General_Concept
without	O
causing	O
loss	O
of	O
compatibility	O
for	O
the	O
programs	O
.	O
</s>
<s>
With	O
software-managed	O
TLBs	O
,	O
a	O
TLB	O
miss	O
generates	O
a	O
TLB	O
miss	O
exception	B-General_Concept
,	O
and	O
operating	B-General_Concept
system	I-General_Concept
code	O
is	O
responsible	O
for	O
walking	O
the	O
page	B-General_Concept
tables	I-General_Concept
and	O
performing	O
the	O
translation	O
in	O
software	O
.	O
</s>
<s>
The	O
operating	B-General_Concept
system	I-General_Concept
then	O
loads	O
the	O
translation	O
into	O
the	O
TLB	O
and	O
restarts	O
the	O
program	O
from	O
the	O
instruction	O
that	O
caused	O
the	O
TLB	O
miss	O
.	O
</s>
<s>
As	O
with	O
hardware	O
TLB	O
management	O
,	O
if	O
the	O
OS	O
finds	O
no	O
valid	O
translation	O
in	O
the	O
page	B-General_Concept
tables	I-General_Concept
,	O
a	O
page	B-General_Concept
fault	I-General_Concept
has	O
occurred	O
,	O
and	O
the	O
OS	O
must	O
handle	O
it	O
accordingly	O
.	O
</s>
<s>
Instruction	B-General_Concept
sets	I-General_Concept
of	O
CPUs	O
that	O
have	O
software-managed	O
TLBs	O
have	O
instructions	O
that	O
allow	O
loading	O
entries	O
into	O
any	O
slot	O
in	O
the	O
TLB	O
.	O
</s>
<s>
The	O
format	O
of	O
the	O
TLB	O
entry	O
is	O
defined	O
as	O
a	O
part	O
of	O
the	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
The	O
MIPS	B-Device
architecture	I-Device
specifies	O
a	O
software-managed	O
TLB	O
.	O
</s>
<s>
The	O
SPARC	B-Architecture
V9	I-Architecture
architecture	O
allows	O
an	O
implementation	O
of	O
SPARC	B-Architecture
V9	I-Architecture
to	O
have	O
no	O
MMU	O
,	O
an	O
MMU	O
with	O
a	O
software-managed	O
TLB	O
,	O
or	O
an	O
MMU	O
with	O
a	O
hardware-managed	O
TLB	O
,	O
and	O
the	O
UltraSPARC	O
Architecture	O
2005	O
specifies	O
a	O
software-managed	O
TLB	O
.	O
</s>
<s>
The	O
Itanium	B-General_Concept
architecture	O
provides	O
an	O
option	O
of	O
using	O
either	O
software	O
-	O
or	O
hardware-managed	O
TLBs	O
.	O
</s>
<s>
The	O
Alpha	B-Device
architecture	O
's	O
TLB	O
is	O
managed	O
in	O
PALcode	B-General_Concept
,	O
rather	O
than	O
in	O
the	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
As	O
the	O
PALcode	B-General_Concept
for	O
a	O
processor	O
can	O
be	O
processor-specific	O
and	O
operating-system-specific	O
,	O
this	O
allows	O
different	O
versions	O
of	O
PALcode	B-General_Concept
to	O
implement	O
different	O
page-table	B-General_Concept
formats	O
for	O
different	O
operating	B-General_Concept
systems	I-General_Concept
,	O
without	O
requiring	O
that	O
the	O
TLB	O
format	O
,	O
and	O
the	O
instructions	O
to	O
control	O
the	O
TLB	O
,	O
to	O
be	O
specified	O
by	O
the	O
architecture	O
.	O
</s>
<s>
On	O
an	O
address-space	B-Operating_System
switch	I-Operating_System
,	O
as	O
occurs	O
when	O
context	B-Operating_System
switching	I-Operating_System
between	O
processes	O
(	O
but	O
not	O
between	O
threads	O
)	O
,	O
some	O
TLB	O
entries	O
can	O
become	O
invalid	O
,	O
since	O
the	O
virtual-to-physical	O
mapping	O
is	O
different	O
.	O
</s>
<s>
Other	O
strategies	O
avoid	O
flushing	O
the	O
TLB	O
on	O
a	O
context	B-Operating_System
switch	I-Operating_System
:	O
</s>
<s>
(	O
a	O
)	O
A	O
single	B-Operating_System
address	I-Operating_System
space	I-Operating_System
operating	I-Operating_System
system	I-Operating_System
uses	O
the	O
same	O
virtual-to-physical	O
mapping	O
for	O
all	O
processes	O
.	O
</s>
<s>
For	O
example	O
,	O
in	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
,	O
each	O
TLB	O
entry	O
is	O
tagged	O
with	O
an	O
address	O
space	O
number	O
(	O
ASN	O
)	O
,	O
and	O
only	O
TLB	O
entries	O
with	O
an	O
ASN	O
matching	O
the	O
current	O
task	O
are	O
considered	O
valid	O
.	O
</s>
<s>
Another	O
example	O
in	O
the	O
Intel	B-Device
Pentium	I-Device
Pro	I-Device
,	O
the	O
page	O
global	O
enable	O
(	O
PGE	O
)	O
flag	O
in	O
the	O
register	O
CR4	O
and	O
the	O
global	O
(	O
G	O
)	O
flag	O
of	O
a	O
page-directory	O
or	O
page-table	B-General_Concept
entry	O
can	O
be	O
used	O
to	O
prevent	O
frequently	O
used	O
pages	B-General_Concept
from	O
being	O
automatically	O
invalidated	O
in	O
the	O
TLBs	O
on	O
a	O
task	O
switch	O
or	O
a	O
load	O
of	O
register	O
CR3	O
.	O
</s>
<s>
Since	O
the	O
2010	O
Westmere	B-Device
microarchitecture	I-Device
Intel	O
64	O
processors	O
also	O
support	O
12-bit	O
process-context	O
identifiers	O
(	O
PCIDs	O
)	O
,	O
which	O
allow	O
retaining	O
TLB	O
entries	O
for	O
multiple	O
linear-address	O
spaces	O
,	O
with	O
only	O
those	O
that	O
match	O
the	O
current	O
PCID	O
being	O
used	O
for	O
address	O
translation	O
.	O
</s>
<s>
While	O
selective	O
flushing	O
of	O
the	O
TLB	O
is	O
an	O
option	O
in	O
software-managed	O
TLBs	O
,	O
the	O
only	O
option	O
in	O
some	O
hardware	O
TLBs	O
(	O
for	O
example	O
,	O
the	O
TLB	O
in	O
the	O
Intel	B-General_Concept
80386	I-General_Concept
)	O
is	O
the	O
complete	O
flushing	O
of	O
the	O
TLB	O
on	O
an	O
address-space	B-Operating_System
switch	I-Operating_System
.	O
</s>
<s>
Other	O
hardware	O
TLBs	O
(	O
for	O
example	O
,	O
the	O
TLB	O
in	O
the	O
Intel	B-General_Concept
80486	I-General_Concept
and	O
later	O
x86	B-Operating_System
processors	O
,	O
and	O
the	O
TLB	O
in	O
ARM	B-Architecture
processors	I-Architecture
)	O
allow	O
the	O
flushing	O
of	O
individual	O
entries	O
from	O
the	O
TLB	O
indexed	O
by	O
virtual	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
Flushing	O
of	O
the	O
TLB	O
can	O
be	O
an	O
important	O
security	O
mechanism	O
for	O
memory	O
isolation	O
between	O
processes	O
to	O
ensure	O
a	O
process	O
ca	O
n't	O
access	O
data	O
stored	O
in	O
memory	B-General_Concept
pages	I-General_Concept
of	O
another	O
process	O
.	O
</s>
<s>
Memory	O
isolation	O
is	O
especially	O
critical	O
during	O
switches	O
between	O
the	O
privileged	O
operating	B-General_Concept
system	I-General_Concept
kernel	O
process	O
and	O
the	O
user	O
processes	O
–	O
as	O
was	O
highlighted	O
by	O
the	O
Meltdown	B-Architecture
security	O
vulnerability	O
.	O
</s>
<s>
Mitigation	O
strategies	O
such	O
as	O
kernel	B-Application
page-table	I-Application
isolation	I-Application
(	O
KPTI	B-Application
)	O
rely	O
heavily	O
on	O
performance-impacting	O
TLB	B-Architecture
flushes	I-Architecture
and	O
benefit	O
greatly	O
from	O
hardware-enabled	O
selective	O
TLB	O
entry	O
management	O
such	O
as	O
PCID	O
.	O
</s>
<s>
With	O
the	O
advent	O
of	O
virtualization	O
for	O
server	O
consolidation	O
,	O
a	O
lot	O
of	O
effort	O
has	O
gone	O
into	O
making	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
easier	O
to	O
virtualize	O
and	O
to	O
ensure	O
better	O
performance	O
of	O
virtual	O
machines	O
on	O
x86	B-Operating_System
hardware	O
.	O
</s>
<s>
Normally	O
,	O
entries	O
in	O
the	O
x86	B-Operating_System
TLBs	O
are	O
not	O
associated	O
with	O
a	O
particular	O
address	O
space	O
;	O
they	O
implicitly	O
refer	O
to	O
the	O
current	O
address	O
space	O
.	O
</s>
<s>
Hence	O
,	O
every	O
time	O
there	O
is	O
a	O
change	O
in	O
address	O
space	O
,	O
such	O
as	O
a	O
context	B-Operating_System
switch	I-Operating_System
,	O
the	O
entire	O
TLB	O
has	O
to	O
be	O
flushed	O
.	O
</s>
<s>
Maintaining	O
a	O
tag	O
that	O
associates	O
each	O
TLB	O
entry	O
with	O
an	O
address	O
space	O
in	O
software	O
and	O
comparing	O
this	O
tag	O
during	O
TLB	O
lookup	O
and	O
TLB	B-Architecture
flush	I-Architecture
is	O
very	O
expensive	O
,	O
especially	O
since	O
the	O
x86	B-Operating_System
TLB	O
is	O
designed	O
to	O
operate	O
with	O
very	O
low	O
latency	O
and	O
completely	O
in	O
hardware	O
.	O
</s>
<s>
In	O
2008	O
,	O
both	O
Intel	O
(	O
Nehalem	B-Device
)	O
and	O
AMD	O
(	O
SVM	O
)	O
have	O
introduced	O
tags	O
as	O
part	O
of	O
the	O
TLB	O
entry	O
and	O
dedicated	O
hardware	O
that	O
checks	O
the	O
tag	O
during	O
lookup	O
.	O
</s>
<s>
Thus	O
a	O
context	B-Operating_System
switch	I-Operating_System
will	O
not	O
result	O
in	O
the	O
flushing	O
of	O
the	O
TLB	O
–	O
but	O
just	O
changing	O
the	O
tag	O
of	O
the	O
current	O
address	O
space	O
to	O
the	O
tag	O
of	O
the	O
address	O
space	O
of	O
the	O
new	O
task	O
.	O
</s>
