<s>
Transactional	B-Operating_System
Synchronization	I-Operating_System
Extensions	I-Operating_System
(	O
TSX	O
)	O
,	O
also	O
called	O
Transactional	B-Operating_System
Synchronization	I-Operating_System
Extensions	I-Operating_System
New	O
Instructions	O
(	O
TSX-NI	B-Operating_System
)	O
,	O
is	O
an	O
extension	O
to	O
the	O
x86	B-Operating_System
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
that	O
adds	O
hardware	B-Operating_System
transactional	I-Operating_System
memory	I-Operating_System
support	O
,	O
speeding	O
up	O
execution	O
of	O
multi-threaded	O
software	O
through	O
lock	O
elision	O
.	O
</s>
<s>
According	O
to	O
different	O
benchmarks	O
,	O
TSX/TSX	O
-NI	O
can	O
provide	O
around	O
40%	O
faster	O
applications	O
execution	O
in	O
specific	O
workloads	O
,	O
and	O
45	O
times	O
more	O
database	O
transactions	B-General_Concept
per	I-General_Concept
second	I-General_Concept
(	O
TPS	O
)	O
.	O
</s>
<s>
TSX/TSX	O
-NI	O
was	O
documented	O
by	O
Intel	O
in	O
February	O
2012	O
,	O
and	O
debuted	O
in	O
June	O
2013	O
on	O
selected	O
Intel	O
microprocessors	B-Architecture
based	O
on	O
the	O
Haswell	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
Haswell	B-Device
processors	O
below	O
45xx	O
as	O
well	O
as	O
R-series	O
and	O
K-series	O
(	O
with	O
unlocked	O
multiplier	O
)	O
SKUs	O
do	O
not	O
support	O
TSX/TSX	O
-NI	O
.	O
</s>
<s>
In	O
August	O
2014	O
,	O
Intel	O
announced	O
a	O
bug	O
in	O
the	O
TSX/TSX	O
-NI	O
implementation	O
on	O
current	O
steppings	O
of	O
Haswell	B-Device
,	O
Haswell-E	O
,	O
Haswell-EP	O
and	O
early	O
Broadwell	B-General_Concept
CPUs	O
,	O
which	O
resulted	O
in	O
disabling	O
the	O
TSX/TSX	O
-NI	O
feature	O
on	O
affected	O
CPUs	O
via	O
a	O
microcode	B-Device
update	O
.	O
</s>
<s>
In	O
2016	O
,	O
a	O
side-channel	O
timing	O
attack	O
was	O
found	O
by	O
abusing	O
the	O
way	O
TSX/TSX	O
-NI	O
handles	O
transactional	O
faults	O
(	O
i.e.	O
</s>
<s>
page	B-General_Concept
faults	I-General_Concept
)	O
in	O
order	O
to	O
break	O
kernel	O
address	O
space	O
layout	O
randomization	O
(	O
KASLR	O
)	O
on	O
all	O
major	O
operating	O
systems	O
.	O
</s>
<s>
In	O
2021	O
,	O
Intel	O
released	O
a	O
microcode	B-Device
update	O
that	O
disabled	O
the	O
TSX/TSX	O
-NI	O
feature	O
on	O
CPU	O
generations	O
from	O
Skylake	B-Architecture
to	O
Coffee	B-Device
Lake	I-Device
,	O
as	O
a	O
mitigation	O
for	O
discovered	O
security	O
issues	O
.	O
</s>
<s>
Support	O
for	O
TSX/TSX	O
-NI	O
emulation	O
is	O
provided	O
as	O
part	O
of	O
the	O
Intel	O
Software	O
Development	O
Emulator	O
.	O
</s>
<s>
There	O
is	O
also	O
experimental	O
support	O
for	O
TSX/TSX	O
-NI	O
emulation	O
in	O
a	O
QEMU	B-Application
fork	O
.	O
</s>
<s>
TSX/TSX	O
-NI	O
provides	O
two	O
software	O
interfaces	O
for	O
designating	O
code	O
regions	O
for	O
transactional	O
execution	O
.	O
</s>
<s>
Hardware	O
Lock	O
Elision	O
(	O
HLE	O
)	O
is	O
an	O
instruction	O
prefix-based	O
interface	O
designed	O
to	O
be	O
backward	O
compatible	O
with	O
processors	O
without	O
TSX/TSX	O
-NI	O
support	O
.	O
</s>
<s>
Restricted	O
Transactional	B-Operating_System
Memory	I-Operating_System
(	O
RTM	O
)	O
is	O
a	O
new	O
instruction	B-General_Concept
set	I-General_Concept
interface	O
that	O
provides	O
greater	O
flexibility	O
for	O
programmers	O
.	O
</s>
<s>
TSX/TSX	O
-NI	O
enables	O
optimistic	B-General_Concept
execution	I-General_Concept
of	O
transactional	O
code	O
regions	O
.	O
</s>
<s>
These	O
two	O
prefixes	O
reuse	O
the	O
opcodes	B-Language
of	O
the	O
existing	O
REPNE	O
/	O
REPE	O
prefixes	O
(	O
F2H	O
/	O
F3H	O
)	O
.	O
</s>
<s>
HLE	O
allows	O
optimistic	B-General_Concept
execution	I-General_Concept
of	O
a	O
critical	O
section	O
by	O
skipping	O
the	O
write	O
to	O
a	O
lock	O
,	O
so	O
that	O
the	O
lock	O
appears	O
to	O
be	O
free	O
to	O
other	O
threads	O
.	O
</s>
<s>
Restricted	O
Transactional	B-Operating_System
Memory	I-Operating_System
(	O
RTM	O
)	O
is	O
an	O
alternative	O
implementation	O
to	O
HLE	O
which	O
gives	O
the	O
programmer	O
the	O
flexibility	O
to	O
specify	O
a	O
fallback	O
code	O
path	O
that	O
is	O
executed	O
when	O
a	O
transaction	O
cannot	O
be	O
successfully	O
executed	O
.	O
</s>
<s>
TSX/TSX	O
-NI	O
provides	O
a	O
new	O
XTEST	O
instruction	O
that	O
returns	O
whether	O
the	O
processor	O
is	O
executing	O
a	O
transactional	O
region	O
.	O
</s>
<s>
TSX/TSX	O
-NI	O
Suspend	O
Load	O
Address	O
Tracking	O
(	O
TSXLDTRK	O
)	O
is	O
an	O
instruction	B-General_Concept
set	I-General_Concept
extension	O
that	O
allows	O
to	O
temporarily	O
disable	O
tracking	O
loads	O
from	O
memory	O
in	O
a	O
section	O
of	O
code	O
within	O
a	O
transactional	O
region	O
.	O
</s>
<s>
Intel	O
's	O
TSX/TSX	O
-NI	O
specification	O
describes	O
how	O
the	O
transactional	B-Operating_System
memory	I-Operating_System
is	O
exposed	O
to	O
programmers	O
,	O
but	O
withholds	O
details	O
on	O
the	O
actual	O
transactional	B-Operating_System
memory	I-Operating_System
implementation	O
.	O
</s>
<s>
Intel	O
specifies	O
in	O
its	O
developer	O
's	O
and	O
optimization	O
manuals	O
that	O
Haswell	B-Device
maintains	O
both	O
read-sets	O
and	O
write-sets	O
at	O
the	O
granularity	O
of	O
a	O
cache	O
line	O
,	O
tracking	O
addresses	O
in	O
the	O
L1	O
data	O
cache	O
of	O
the	O
processor	O
.	O
</s>
<s>
Intel	O
also	O
states	O
that	O
data	O
conflicts	O
are	O
detected	O
through	O
the	O
cache	B-General_Concept
coherence	I-General_Concept
protocol	O
.	O
</s>
<s>
Haswell	B-Device
's	O
L1	O
data	O
cache	O
has	O
an	O
associativity	O
of	O
eight	O
.	O
</s>
<s>
Additionally	O
,	O
in	O
CPU	O
configurations	O
with	O
Hyper-Threading	B-Operating_System
Technology	I-Operating_System
,	O
the	O
L1	O
cache	O
is	O
shared	O
between	O
the	O
two	O
threads	O
on	O
the	O
same	O
core	O
,	O
so	O
operations	O
in	O
a	O
sibling	O
logical	O
processor	O
of	O
the	O
same	O
core	O
can	O
cause	O
evictions	O
.	O
</s>
<s>
Independent	O
research	O
points	O
into	O
Haswell	B-Device
’s	O
transactional	B-Operating_System
memory	I-Operating_System
most	O
likely	O
being	O
a	O
deferred	O
update	O
system	O
using	O
the	O
per-core	O
caches	O
for	O
transactional	O
data	O
and	O
register	O
checkpoints	O
.	O
</s>
<s>
In	O
other	O
words	O
,	O
Haswell	B-Device
is	O
more	O
likely	O
to	O
use	O
the	O
cache-based	O
transactional	B-Operating_System
memory	I-Operating_System
system	O
,	O
as	O
it	O
is	O
a	O
much	O
less	O
risky	O
implementation	O
choice	O
.	O
</s>
<s>
On	O
the	O
other	O
hand	O
,	O
Intel	O
's	O
Skylake	B-Architecture
or	O
later	O
may	O
combine	O
this	O
cache-based	O
approach	O
with	O
memory	O
ordering	O
buffer	O
(	O
MOB	O
)	O
for	O
the	O
same	O
purpose	O
,	O
possibly	O
also	O
providing	O
multi-versioned	O
transactional	B-Operating_System
memory	I-Operating_System
that	O
is	O
more	O
amenable	O
to	O
speculative	B-Operating_System
multithreading	I-Operating_System
.	O
</s>
<s>
In	O
August	O
2014	O
,	O
Intel	O
announced	O
that	O
a	O
bug	O
exists	O
in	O
the	O
TSX/TSX	O
-NI	O
implementation	O
on	O
Haswell	B-Device
,	O
Haswell-E	O
,	O
Haswell-EP	O
and	O
early	O
Broadwell	B-General_Concept
CPUs	O
,	O
which	O
resulted	O
in	O
disabling	O
the	O
TSX/TSX	O
-NI	O
feature	O
on	O
affected	O
CPUs	O
via	O
a	O
microcode	B-Device
update	O
.	O
</s>
<s>
The	O
bug	O
was	O
fixed	O
in	O
F-0	O
steppings	O
of	O
the	O
vPro-enabled	O
Core	O
M-5Y70	O
Broadwell	B-General_Concept
CPU	O
in	O
November	O
2014	O
.	O
</s>
<s>
In	O
October	O
2018	O
,	O
Intel	O
disclosed	O
a	O
TSX/TSX	O
-NI	O
memory	O
ordering	O
issue	O
found	O
in	O
some	O
Skylake	B-Architecture
processors	O
.	O
</s>
<s>
As	O
a	O
result	O
of	O
a	O
microcode	B-Device
update	O
,	O
HLE	O
support	O
was	O
disabled	O
in	O
the	O
affected	O
CPUs	O
,	O
and	O
RTM	O
was	O
mitigated	O
by	O
sacrificing	O
one	O
performance	O
counter	O
when	O
used	O
outside	O
of	O
Intel	O
SGX	O
mode	O
or	O
System	B-Architecture
Management	I-Architecture
Mode	I-Architecture
(	O
SMM	B-Architecture
)	O
.	O
</s>
<s>
In	O
June	O
2021	O
,	O
Intel	O
published	O
a	O
microcode	B-Device
update	O
that	O
further	O
disables	O
TSX/TSX	O
-NI	O
on	O
various	O
Xeon	O
and	O
Core	O
processor	O
models	O
from	O
Skylake	B-Architecture
through	O
Coffee	B-Device
Lake	I-Device
and	O
Whiskey	B-Device
Lake	I-Device
as	O
a	O
mitigation	O
for	O
TSX	O
Asynchronous	O
Abort	O
(	O
TAA	O
)	O
vulnerability	O
.	O
</s>
<s>
By	O
default	O
,	O
with	O
the	O
updated	O
microcode	B-Device
,	O
the	O
processor	O
would	O
still	O
indicate	O
support	O
for	O
RTM	O
but	O
would	O
always	O
abort	O
the	O
transaction	O
.	O
</s>
<s>
System	O
software	O
is	O
able	O
to	O
detect	O
this	O
mode	O
of	O
operation	O
and	O
mask	O
support	O
for	O
TSX/TSX	O
-NI	O
from	O
the	O
CPUID	O
instruction	O
,	O
preventing	O
detection	O
of	O
TSX/TSX	O
-NI	O
by	O
applications	O
.	O
</s>
<s>
According	O
to	O
Intel	O
64	O
and	O
IA-32	O
Architectures	O
Software	O
Developer	O
's	O
Manual	O
from	O
May	O
2020	O
,	O
Volume	O
1	O
,	O
Chapter	O
2.5	O
Intel	O
Instruction	B-General_Concept
Set	I-General_Concept
Architecture	I-General_Concept
And	O
Features	O
Removed	O
,	O
HLE	O
has	O
been	O
removed	O
from	O
Intel	O
products	O
released	O
in	O
2019	O
and	O
later	O
.	O
</s>
<s>
However	O
,	O
Intel	O
10th	O
generation	O
Comet	B-Device
Lake	I-Device
and	O
Ice	B-Device
Lake	I-Device
CPUs	O
,	O
which	O
were	O
released	O
in	O
2020	O
,	O
do	O
not	O
support	O
TSX/TSX	O
-NI	O
,	O
including	O
both	O
HLE	O
and	O
RTM	O
.	O
</s>
<s>
Engineering	O
versions	O
of	O
Comet	B-Device
Lake	I-Device
processors	O
were	O
still	O
retaining	O
TSX/TSX	O
-NI	O
support	O
.	O
</s>
<s>
In	O
Intel	O
Architecture	O
Instruction	B-General_Concept
Set	I-General_Concept
Extensions	O
Programming	O
Reference	O
revision	O
41	O
from	O
October	O
2020	O
,	O
a	O
new	O
TSXLDTRK	O
instruction	B-General_Concept
set	I-General_Concept
extension	O
was	O
documented	O
.	O
</s>
<s>
It	O
was	O
first	O
included	O
in	O
Sapphire	B-Device
Rapids	I-Device
processors	O
released	O
in	O
January	O
2023	O
.	O
</s>
