<s>
In	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
a	O
trace	B-General_Concept
cache	I-General_Concept
or	O
execution	O
trace	B-General_Concept
cache	I-General_Concept
is	O
a	O
specialized	O
instruction	O
cache	O
which	O
stores	O
the	O
dynamic	O
stream	O
of	O
instructions	O
known	O
as	O
trace	O
.	O
</s>
<s>
It	O
helps	O
in	O
increasing	O
the	O
instruction	O
fetch	O
bandwidth	O
and	O
decreasing	O
power	O
consumption	O
(	O
in	O
the	O
case	O
of	O
Intel	B-General_Concept
Pentium	I-General_Concept
4	I-General_Concept
)	O
by	O
storing	O
traces	O
of	O
instructions	O
that	O
have	O
already	O
been	O
fetched	O
and	O
decoded	O
.	O
</s>
<s>
A	O
trace	O
processor	O
is	O
an	O
architecture	O
designed	O
around	O
the	O
trace	B-General_Concept
cache	I-General_Concept
and	O
processes	O
the	O
instructions	O
at	O
trace	O
level	O
granularity	O
.	O
</s>
<s>
The	O
earliest	O
academic	O
publication	O
of	O
trace	B-General_Concept
cache	I-General_Concept
was	O
"	O
Trace	B-General_Concept
Cache	I-General_Concept
:	O
a	O
Low	O
Latency	O
Approach	O
to	O
High	O
Bandwidth	O
Instruction	B-General_Concept
Fetching	I-General_Concept
"	O
.	O
</s>
<s>
Wider	O
superscalar	B-General_Concept
processors	I-General_Concept
demand	O
multiple	O
instructions	O
to	O
be	O
fetched	O
in	O
a	O
single	O
cycle	O
for	O
higher	O
performance	O
.	O
</s>
<s>
Instructions	O
to	O
be	O
fetched	O
are	O
not	O
always	O
in	O
contiguous	B-Architecture
memory	O
locations	O
(	O
basic	B-Application
blocks	I-Application
)	O
because	O
of	O
branch	B-General_Concept
and	O
jump	O
instructions	O
.	O
</s>
<s>
So	O
processors	O
need	O
additional	O
logic	O
and	O
hardware	O
support	O
to	O
fetch	O
and	O
align	O
such	O
instructions	O
from	O
non-contiguous	O
basic	B-Application
blocks	I-Application
.	O
</s>
<s>
If	O
multiple	O
branches	O
are	O
predicted	O
as	O
not-taken	O
,	O
then	O
processors	O
can	O
fetch	O
instructions	O
from	O
multiple	O
contiguous	B-Architecture
basic	B-Application
blocks	I-Application
in	O
a	O
single	O
cycle	O
.	O
</s>
<s>
Consider	O
these	O
four	O
basic	B-Application
blocks	I-Application
(	O
A	O
,	O
B	O
,	O
C	O
,	O
D	O
)	O
as	O
shown	O
in	O
the	O
figure	O
that	O
correspond	O
to	O
a	O
simple	O
if-else	B-Language
loop	I-Language
.	O
</s>
<s>
If	O
the	O
branch	B-General_Concept
D	O
is	O
predicted	O
not-taken	O
,	O
the	O
fetch	O
unit	O
can	O
fetch	O
the	O
basic	B-Application
blocks	I-Application
A	O
,	O
B	O
,	O
C	O
which	O
are	O
placed	O
contiguously	O
.	O
</s>
<s>
So	O
,	O
in	O
situations	O
like	O
these	O
,	O
the	O
trace	B-General_Concept
cache	I-General_Concept
comes	O
in	O
aid	O
to	O
the	O
processor	O
.	O
</s>
<s>
Once	O
fetched	O
,	O
the	O
trace	B-General_Concept
cache	I-General_Concept
stores	O
the	O
instructions	O
in	O
their	O
dynamic	O
sequence	O
.	O
</s>
<s>
When	O
these	O
instructions	O
are	O
encountered	O
again	O
,	O
the	O
trace	B-General_Concept
cache	I-General_Concept
allows	O
the	O
instruction	O
fetch	O
unit	O
of	O
a	O
processor	O
to	O
fetch	O
several	O
basic	B-Application
blocks	I-Application
from	O
it	O
without	O
having	O
to	O
worry	O
about	O
branches	O
in	O
the	O
execution	O
flow	O
.	O
</s>
<s>
Instructions	O
will	O
be	O
stored	O
in	O
the	O
trace	B-General_Concept
cache	I-General_Concept
either	O
after	O
they	O
have	O
been	O
decoded	O
,	O
or	O
as	O
they	O
are	O
retired	O
.	O
</s>
<s>
A	O
trace	O
,	O
also	O
called	O
a	O
dynamic	O
instruction	O
sequence	O
,	O
is	O
an	O
entry	O
in	O
the	O
trace	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
It	O
can	O
be	O
characterized	O
by	O
maximum	O
number	O
of	O
instructions	O
and	O
maximum	O
basic	B-Application
blocks	I-Application
.	O
</s>
<s>
Multiple	O
traces	O
can	O
have	O
same	O
starting	O
instruction	O
i.e.	O
,	O
same	O
starting	O
program	B-General_Concept
counter	I-General_Concept
(	O
PC	O
)	O
and	O
instructions	O
from	O
different	O
basic	B-Application
blocks	I-Application
as	O
per	O
the	O
branch	B-General_Concept
outcomes	O
.	O
</s>
<s>
They	O
both	O
start	O
at	O
the	O
same	O
PC	O
(	O
address	O
of	O
A	O
)	O
and	O
have	O
different	O
basic	B-Application
blocks	I-Application
as	O
per	O
D	O
's	O
prediction	O
.	O
</s>
<s>
Following	O
are	O
the	O
factors	O
that	O
need	O
to	O
be	O
considered	O
while	O
designing	O
a	O
trace	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Trace	O
lines	O
are	O
stored	O
in	O
the	O
trace	B-General_Concept
cache	I-General_Concept
based	O
on	O
the	O
PC	O
of	O
the	O
first	O
instruction	O
in	O
the	O
trace	O
and	O
a	O
set	O
of	O
branch	B-General_Concept
predictions	I-General_Concept
.	O
</s>
<s>
This	O
allows	O
for	O
storing	O
different	O
trace	O
paths	O
that	O
start	O
on	O
the	O
same	O
address	O
,	O
each	O
representing	O
different	O
branch	B-General_Concept
outcomes	O
.	O
</s>
<s>
This	O
method	O
of	O
tagging	O
helps	O
to	O
provide	O
path	O
associativity	B-General_Concept
to	O
the	O
trace	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Other	O
method	O
can	O
include	O
having	O
only	O
starting	O
PC	O
as	O
tag	O
in	O
trace	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
In	O
the	O
instruction	O
fetch	O
stage	O
of	O
a	O
pipeline	B-General_Concept
,	O
the	O
current	O
PC	O
along	O
with	O
a	O
set	O
of	O
branch	B-General_Concept
predictions	I-General_Concept
is	O
checked	O
in	O
the	O
trace	B-General_Concept
cache	I-General_Concept
for	O
a	O
hit	O
.	O
</s>
<s>
The	O
trace	B-General_Concept
cache	I-General_Concept
continues	O
to	O
feed	O
the	O
fetch	O
unit	O
until	O
the	O
trace	O
line	O
ends	O
or	O
until	O
there	O
is	O
a	O
misprediction	B-General_Concept
in	O
the	O
pipeline	B-General_Concept
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
4	I-General_Concept
's	O
execution	O
trace	B-General_Concept
cache	I-General_Concept
stores	O
micro-operations	B-General_Concept
resulting	O
from	O
decoding	O
x86	B-Device
instructions	I-Device
,	O
providing	O
also	O
the	O
functionality	O
of	O
a	O
micro-operation	B-General_Concept
cache	O
.	O
</s>
<s>
Having	O
this	O
,	O
the	O
next	O
time	O
an	O
instruction	O
is	O
needed	O
,	O
it	O
does	O
not	O
have	O
to	O
be	O
decoded	O
into	O
micro-ops	B-General_Concept
again	O
.	O
</s>
<s>
The	O
disadvantages	O
of	O
trace	B-General_Concept
cache	I-General_Concept
are	O
:	O
</s>
<s>
Redundant	O
instruction	O
storage	O
between	O
trace	B-General_Concept
cache	I-General_Concept
and	O
instruction	O
cache	O
and	O
within	O
trace	B-General_Concept
cache	I-General_Concept
itself	O
.	O
</s>
<s>
Within	O
the	O
L1	O
cache	O
of	O
the	O
NetBurst	B-Device
CPUs	O
,	O
Intel	O
incorporated	O
its	O
execution	O
trace	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
It	O
stores	O
decoded	O
micro-operations	B-General_Concept
,	O
so	O
that	O
when	O
executing	O
a	O
new	O
instruction	O
,	O
instead	O
of	O
fetching	O
and	O
decoding	O
the	O
instruction	O
again	O
,	O
the	O
CPU	O
directly	O
accesses	O
the	O
decoded	O
micro-ops	B-General_Concept
from	O
the	O
trace	B-General_Concept
cache	I-General_Concept
,	O
thereby	O
saving	O
considerable	O
time	O
.	O
</s>
<s>
Moreover	O
,	O
the	O
micro-ops	B-General_Concept
are	O
cached	O
in	O
their	O
predicted	O
path	O
of	O
execution	O
,	O
which	O
means	O
that	O
when	O
instructions	O
are	O
fetched	O
by	O
the	O
CPU	O
from	O
the	O
cache	O
,	O
they	O
are	O
already	O
present	O
in	O
the	O
correct	O
order	O
of	O
execution	O
.	O
</s>
<s>
Intel	O
later	O
introduced	O
a	O
similar	O
but	O
simpler	O
concept	O
with	O
Sandy	B-Device
Bridge	I-Device
called	O
micro-operation	B-General_Concept
cache	O
(	O
UOP	O
cache	O
)	O
.	O
</s>
