<s>
Torrenza	B-General_Concept
was	O
an	O
initiative	O
announced	O
by	O
Advanced	O
Micro	O
Devices	O
(	O
AMD	O
)	O
in	O
2006	O
to	O
improve	O
support	O
for	O
the	O
integration	O
of	O
specialized	O
coprocessors	B-General_Concept
in	O
systems	O
based	O
on	O
AMD	B-General_Concept
Opteron	I-General_Concept
microprocessors	O
.	O
</s>
<s>
Torrenza	B-General_Concept
does	O
not	O
refer	O
to	O
a	O
specific	O
product	O
or	O
specific	O
technology	O
,	O
though	O
the	O
primary	O
focus	O
is	O
on	O
the	O
integration	O
of	O
coprocessor	B-General_Concept
devices	O
directly	O
connected	O
to	O
the	O
Opteron	B-General_Concept
processors	O
 '	O
HyperTransport	B-Device
links	O
,	O
and	O
other	O
co-processors	B-General_Concept
connected	O
via	O
PCI	O
Express	O
.	O
</s>
<s>
The	O
initiative	O
's	O
stated	O
goals	O
include	O
improving	O
technical	O
and	O
technology	O
support	O
for	O
third-party	O
developers	O
of	O
coprocessing	O
devices	O
,	O
reducing	O
the	O
cost	O
of	O
implementing	O
HyperTransport	B-Device
interfaces	O
on	O
these	O
devices	O
,	O
and	O
improving	O
the	O
performance	O
of	O
the	O
integrated	O
system	O
.	O
</s>
<s>
It	O
can	O
be	O
argued	O
,	O
that	O
the	O
original	O
idea	O
behind	O
Torrenza	B-General_Concept
was	O
successfully	O
implemented	O
in	O
form	O
of	O
Heterogeneous	B-Architecture
System	I-Architecture
Architecture	I-Architecture
by	O
AMD	O
and	O
the	O
other	O
members	O
of	O
the	O
HSA	B-Application
Foundation	I-Application
.	O
</s>
<s>
AMD	O
expected	O
tightly-integrated	O
coprocessor	B-General_Concept
technology	O
to	O
be	O
a	O
proving	O
ground	O
for	O
developing	O
and	O
assessing	O
technologies	O
that	O
may	O
eventually	O
migrate	O
onto	O
the	O
processor	O
die	O
itself	O
.	O
</s>
<s>
Promoting	O
third-party	O
co-processors	B-General_Concept
was	O
envisioned	O
as	O
a	O
stepping	O
stone	O
to	O
the	O
advanced	O
CPU	O
designs	O
of	O
the	O
future	O
and	O
a	O
platform	O
for	O
software	O
development	O
needed	O
for	O
those	O
hardware	O
designs	O
.	O
</s>
<s>
On	O
June	O
1	O
,	O
2006	O
,	O
AMD	O
announced	O
the	O
Torrenza	B-General_Concept
program	O
.	O
</s>
<s>
The	O
Torrenza	B-General_Concept
label	O
was	O
applied	O
to	O
both	O
accelerator	O
projects	O
that	O
pre-dated	O
the	O
announcement	O
as	O
well	O
as	O
projects	O
announced	O
later	O
.	O
</s>
<s>
Intel	O
followed	O
suit	O
by	O
opening	O
up	O
its	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
to	O
third-party	O
companies	O
,	O
alongside	O
a	O
PCI	O
Express	O
extension	O
project	O
jointly	O
co-developed	O
with	O
IBM	O
codenamed	O
Geneseo	B-Architecture
.	O
</s>
<s>
HyperTransport-connected	O
devices	O
can	O
be	O
installed	O
in	O
HTX	B-Device
slots	O
or	O
in	O
Opteron	B-General_Concept
CPU	O
sockets	O
.	O
</s>
<s>
HTX	B-Device
slots	O
are	O
placed	O
to	O
allow	O
access	O
to	O
external	O
cabling	O
and	O
so	O
are	O
the	O
natural	O
location	O
for	O
network	O
devices	O
,	O
such	O
as	O
the	O
Qlogic	O
Infinipath	O
network	O
adapter	O
.	O
</s>
<s>
In	O
some	O
system	O
configurations	O
,	O
the	O
CPU	O
sockets	O
provide	O
access	O
to	O
multiple	O
HyperTransport	B-Device
links	O
that	O
support	O
higher	O
frequencies	O
than	O
single	O
16-bit	O
(	O
per	O
direction	O
)	O
800MHz	O
link	O
supported	O
by	O
the	O
HTX	B-Device
slot	O
.	O
</s>
<s>
Examples	O
of	O
devices	O
that	O
can	O
be	O
installed	O
in	O
AMD	B-General_Concept
Opteron	I-General_Concept
CPU	O
sockets	O
included	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
(	O
FPGA	B-Architecture
)	O
co-processor	B-General_Concept
modules	O
.	O
</s>
<s>
They	O
use	O
HyperTransport	B-Device
to	O
directly	O
connect	O
the	O
FPGA	B-Architecture
devices	O
to	O
the	O
other	O
CPU	O
socket	O
and	O
both	O
provide	O
memory	O
controllers	O
to	O
access	O
memory	O
on	O
the	O
motherboard	O
.	O
</s>
<s>
Torrenza	B-General_Concept
was	O
closely	O
(	O
though	O
not	O
exclusively	O
)	O
identified	O
with	O
HyperTransport	B-Device
technology	O
promoted	O
by	O
the	O
HyperTransport	B-Architecture
Consortium	I-Architecture
.	O
</s>
<s>
Technology	O
elements	O
of	O
Torrenza	B-General_Concept
were	O
related	O
to	O
the	O
AMD	B-Architecture
Fusion	I-Architecture
,	O
later	O
Accelerated	B-Architecture
Processing	I-Architecture
Unit	I-Architecture
,	O
project	O
,	O
which	O
targets	O
the	O
integration	O
of	O
graphics	O
processing	O
units	O
(	O
or	O
other	O
coprocessing	O
functions	O
)	O
and	O
CPU	O
cores	O
onto	O
one	O
chip	O
.	O
</s>
<s>
As	O
a	O
programmatic	O
distinction	O
,	O
Torrenza	B-General_Concept
refers	O
to	O
external	O
acceleration	O
technology	O
(	O
including	O
graphics	O
processing	O
units	O
in	O
PCIe	O
slots	O
)	O
,	O
while	O
Fusion	O
refers	O
to	O
integrated	O
acceleration	O
technology	O
.	O
</s>
<s>
It	O
was	O
rumored	O
in	O
2007	O
that	O
the	O
future	O
IBM	O
POWER7	B-Device
processors	O
would	O
be	O
socket	O
compatible	O
with	O
Opteron	B-General_Concept
processors	O
.	O
</s>
<s>
The	O
IBM	B-General_Concept
Roadrunner	I-General_Concept
supercomputer	O
connected	O
thousands	O
of	O
Opteron	B-General_Concept
cores	O
to	O
almost	O
as	O
many	O
Cell	O
Broadband	O
Engines	O
in	O
an	O
effort	O
to	O
reach	O
1petaflop	O
of	O
processing	O
power	O
.	O
</s>
<s>
However	O
,	O
it	O
is	O
not	O
clear	O
if	O
this	O
system	O
configuration	O
should	O
be	O
considered	O
an	O
example	O
of	O
a	O
coprocessing	O
architecture	O
because	O
the	O
Opteron	B-General_Concept
and	O
Cell	O
processors	O
run	O
independent	O
operating	O
systems	O
and	O
communicate	O
using	O
software-based	O
message-passing	O
protocols	O
.	O
</s>
<s>
Delivered	O
in	O
mid-2008	O
,	O
AMD	O
was	O
not	O
expected	O
to	O
emphasize	O
the	O
Torrenza	B-General_Concept
initiative	O
from	O
about	O
that	O
time	O
.	O
</s>
<s>
It	O
was	O
not	O
mentioned	O
in	O
a	O
2009	O
news	O
release	O
about	O
the	O
Roadrunner	B-General_Concept
,	O
for	O
example	O
.	O
</s>
