<s>
Tomasulo	B-General_Concept
's	I-General_Concept
algorithm	I-General_Concept
is	O
a	O
computer	B-General_Concept
architecture	I-General_Concept
hardware	O
algorithm	O
for	O
dynamic	O
scheduling	O
of	O
instructions	O
that	O
allows	O
out-of-order	B-General_Concept
execution	I-General_Concept
and	O
enables	O
more	O
efficient	O
use	O
of	O
multiple	O
execution	O
units	O
.	O
</s>
<s>
It	O
was	O
developed	O
by	O
Robert	O
Tomasulo	B-General_Concept
at	O
IBM	O
in	O
1967	O
and	O
was	O
first	O
implemented	O
in	O
the	O
IBM	B-Device
System/360	I-Device
Model	I-Device
91	I-Device
’s	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
major	O
innovations	O
of	O
Tomasulo	B-General_Concept
’s	O
algorithm	O
include	O
register	B-Architecture
renaming	I-Architecture
in	O
hardware	O
,	O
reservation	B-General_Concept
stations	I-General_Concept
for	O
all	O
execution	O
units	O
,	O
and	O
a	O
common	O
data	O
bus	O
(	O
CDB	O
)	O
on	O
which	O
computed	O
values	O
broadcast	O
to	O
all	O
reservation	B-General_Concept
stations	I-General_Concept
that	O
may	O
need	O
them	O
.	O
</s>
<s>
These	O
developments	O
allow	O
for	O
improved	O
parallel	B-Operating_System
execution	I-Operating_System
of	O
instructions	O
that	O
would	O
otherwise	O
stall	O
under	O
the	O
use	O
of	O
scoreboarding	B-General_Concept
or	O
other	O
earlier	O
algorithms	O
.	O
</s>
<s>
Robert	O
Tomasulo	B-General_Concept
received	O
the	O
Eckert	O
–	O
Mauchly	O
Award	O
in	O
1997	O
for	O
his	O
work	O
on	O
the	O
algorithm	O
.	O
</s>
<s>
The	O
following	O
are	O
the	O
concepts	O
necessary	O
to	O
the	O
implementation	O
of	O
Tomasulo	B-General_Concept
's	I-General_Concept
algorithm	I-General_Concept
:	O
</s>
<s>
The	O
Common	O
Data	O
Bus	O
(	O
CDB	O
)	O
connects	O
reservation	B-General_Concept
stations	I-General_Concept
directly	O
to	O
functional	O
units	O
.	O
</s>
<s>
According	O
to	O
Tomasulo	B-General_Concept
it	O
"	O
preserves	O
precedence	O
while	O
encouraging	O
concurrency	O
"	O
.	O
</s>
<s>
Hazard	B-General_Concept
Detection	O
and	O
control	O
execution	O
are	O
distributed	O
.	O
</s>
<s>
The	O
reservation	B-General_Concept
stations	I-General_Concept
control	O
when	O
an	O
instruction	O
can	O
execute	O
,	O
rather	O
than	O
a	O
single	O
dedicated	O
hazard	B-General_Concept
unit	O
.	O
</s>
<s>
Instructions	O
are	O
issued	O
sequentially	O
so	O
that	O
the	O
effects	O
of	O
a	O
sequence	O
of	O
instructions	O
,	O
such	O
as	O
exceptions	O
raised	O
by	O
these	O
instructions	O
,	O
occur	O
in	O
the	O
same	O
order	O
as	O
they	O
would	O
on	O
an	O
in-order	B-General_Concept
processor	O
,	O
regardless	O
of	O
the	O
fact	O
that	O
they	O
are	O
being	O
executed	O
out-of-order	O
(	O
i.e.	O
</s>
<s>
Tomasulo	B-General_Concept
's	I-General_Concept
algorithm	I-General_Concept
uses	O
register	B-Architecture
renaming	I-Architecture
to	O
correctly	O
perform	O
out-of-order	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
All	O
general-purpose	O
and	O
reservation	B-General_Concept
station	I-General_Concept
registers	O
hold	O
either	O
a	O
real	O
value	O
or	O
a	O
placeholder	O
value	O
.	O
</s>
<s>
The	O
placeholder	O
value	O
is	O
a	O
tag	O
indicating	O
which	O
reservation	B-General_Concept
station	I-General_Concept
will	O
produce	O
the	O
real	O
value	O
.	O
</s>
<s>
Each	O
functional	O
unit	O
has	O
a	O
single	O
reservation	B-General_Concept
station	I-General_Concept
.	O
</s>
<s>
Reservation	B-General_Concept
stations	I-General_Concept
hold	O
information	O
needed	O
to	O
execute	O
a	O
single	O
instruction	O
,	O
including	O
the	O
operation	O
and	O
the	O
operands	O
.	O
</s>
<s>
Practically	O
speaking	O
,	O
there	O
may	O
be	O
exceptions	O
for	O
which	O
not	O
enough	O
status	O
information	O
about	O
an	O
exception	B-General_Concept
is	O
available	O
,	O
in	O
which	O
case	O
the	O
processor	O
may	O
raise	O
a	O
special	O
exception	B-General_Concept
,	O
called	O
an	O
"	O
imprecise	O
"	O
exception	B-General_Concept
.	O
</s>
<s>
Imprecise	O
exceptions	O
cannot	O
occur	O
in	O
in-order	B-General_Concept
implementations	O
,	O
as	O
processor	O
state	O
is	O
changed	O
only	O
in	O
program	O
order	O
(	O
see	O
RISC	O
Pipeline	O
Exceptions	O
)	O
.	O
</s>
<s>
Programs	O
that	O
experience	O
"	O
precise	O
"	O
exceptions	O
,	O
where	O
the	O
specific	O
instruction	O
that	O
took	O
the	O
exception	B-General_Concept
can	O
be	O
determined	O
,	O
can	O
restart	O
or	O
re-execute	O
at	O
the	O
point	O
of	O
the	O
exception	B-General_Concept
.	O
</s>
<s>
However	O
,	O
those	O
that	O
experience	O
"	O
imprecise	O
"	O
exceptions	O
generally	O
cannot	O
restart	O
or	O
re-execute	O
,	O
as	O
the	O
system	O
cannot	O
determine	O
the	O
specific	O
instruction	O
that	O
took	O
the	O
exception	B-General_Concept
.	O
</s>
<s>
In	O
the	O
issue	O
stage	O
,	O
instructions	O
are	O
issued	O
for	O
execution	O
if	O
all	O
operands	O
and	O
reservation	B-General_Concept
stations	I-General_Concept
are	O
ready	O
or	O
else	O
they	O
are	O
stalled	O
.	O
</s>
<s>
Registers	O
are	O
renamed	O
in	O
this	O
step	O
,	O
eliminating	O
WAR	O
and	O
WAW	O
hazards	B-General_Concept
.	O
</s>
<s>
Instructions	O
are	O
delayed	O
in	O
this	O
step	O
until	O
all	O
of	O
their	O
operands	O
are	O
available	O
,	O
eliminating	O
RAW	O
hazards	B-General_Concept
.	O
</s>
<s>
Program	O
correctness	O
is	O
maintained	O
through	O
effective	O
address	O
calculation	O
to	O
prevent	O
hazards	B-General_Concept
through	O
memory	O
.	O
</s>
<s>
The	O
concepts	O
of	O
reservation	B-General_Concept
stations	I-General_Concept
,	O
register	B-Architecture
renaming	I-Architecture
,	O
and	O
the	O
common	O
data	O
bus	O
in	O
Tomasulo	B-General_Concept
's	I-General_Concept
algorithm	I-General_Concept
presents	O
significant	O
advancements	O
in	O
the	O
design	O
of	O
high-performance	O
computers	O
.	O
</s>
<s>
Reservation	B-General_Concept
stations	I-General_Concept
take	O
on	O
the	O
responsibility	O
of	O
waiting	O
for	O
operands	O
in	O
the	O
presence	O
of	O
data	O
dependencies	O
and	O
other	O
inconsistencies	O
such	O
as	O
varying	O
storage	O
access	O
time	O
and	O
circuit	O
speeds	O
,	O
thus	O
freeing	O
up	O
the	O
functional	O
units	O
.	O
</s>
<s>
This	O
is	O
a	O
result	O
of	O
the	O
common	O
data	O
bus	O
and	O
reservation	B-General_Concept
station	I-General_Concept
working	O
together	O
to	O
preserve	O
dependencies	O
as	O
well	O
as	O
encouraging	O
concurrency	O
.	O
</s>
<s>
By	O
tracking	O
operands	O
for	O
instructions	O
in	O
the	O
reservation	B-General_Concept
stations	I-General_Concept
and	O
register	B-Architecture
renaming	I-Architecture
in	O
hardware	O
the	O
algorithm	O
minimizes	O
read-after-write	O
(	O
RAW	O
)	O
and	O
eliminates	O
write-after-write	O
(	O
WAW	O
)	O
and	O
Write-after-Read	O
(	O
WAR	O
)	O
computer	B-General_Concept
architecture	I-General_Concept
hazards	B-General_Concept
.	O
</s>
<s>
Tomasulo	B-General_Concept
's	I-General_Concept
algorithm	I-General_Concept
,	O
outside	O
of	O
IBM	O
,	O
was	O
unused	O
for	O
several	O
years	O
after	O
its	O
implementation	O
in	O
the	O
System/360	O
Model	O
91	O
architecture	O
.	O
</s>
<s>
Once	O
caches	O
became	O
commonplace	O
,	O
the	O
Tomasulo	B-General_Concept
algorithm	I-General_Concept
's	O
ability	O
to	O
maintain	O
concurrency	O
during	O
unpredictable	O
load	O
times	O
caused	O
by	O
cache	O
misses	O
became	O
valuable	O
in	O
processors	O
.	O
</s>
<s>
Many	O
modern	O
processors	O
implement	O
dynamic	O
scheduling	O
schemes	O
that	O
are	O
derivative	O
of	O
Tomasulo	B-General_Concept
's	O
original	O
algorithm	O
,	O
including	O
popular	O
Intel	O
x86-64	B-Device
chips	O
.	O
</s>
