<s>
Titan	B-General_Concept
was	O
a	O
planned	O
family	O
of	O
32-bit	O
Power	O
ISA-based	O
microprocessor	B-Architecture
cores	I-Architecture
designed	O
by	O
Applied	O
Micro	O
Circuits	O
Corporation	O
(	O
AMCC	O
)	O
,	O
but	O
was	O
scrapped	O
in	O
2010	O
.	O
</s>
<s>
Applied	O
Micro	O
chose	O
to	O
continue	O
development	O
of	O
the	O
PowerPC	B-General_Concept
400	I-General_Concept
core	B-Architecture
instead	O
,	O
on	O
a	O
40nm	O
fabrication	O
process	O
.	O
</s>
<s>
It	O
was	O
designed	O
to	O
be	O
the	O
foundation	O
of	O
embedded	B-Architecture
processors	I-Architecture
and	O
system-on-a-chip	B-Architecture
(	O
SoC	O
)	O
solutions	O
.	O
</s>
<s>
While	O
being	O
high	O
performance	O
,	O
reaching	O
speeds	O
up	O
to	O
2GHz	O
,	O
it	O
would	O
remain	O
extremely	O
power	O
efficient	O
,	O
drawing	O
just	O
2.5	O
W	O
per	O
core	B-Architecture
.	O
</s>
<s>
Where	O
there	O
usually	O
is	O
a	O
trade-off	O
between	O
performance	O
and	O
power	O
,	O
AMCC	O
used	O
the	O
Fast14	O
technology	O
from	O
Intrinsity	O
to	O
build	O
an	O
extremely	O
efficient	O
microprocessor	B-Architecture
design	O
leveraging	O
high	O
performance	O
combined	O
with	O
low	O
power	O
and	O
comparably	O
cheap	O
bulk	O
90nm	O
CMOS	B-Device
manufacturing	O
.	O
</s>
<s>
By	O
using	O
NMOS	B-Algorithm
transistors	O
and	O
no	O
latches	B-General_Concept
,	O
the	O
design	O
results	O
in	O
a	O
chip	O
with	O
fewer	O
transistors	O
than	O
traditional	O
design	O
,	O
thus	O
reducing	O
cost	O
.	O
</s>
<s>
The	O
design	O
allows	O
for	O
dual	B-Architecture
core	I-Architecture
SoC	O
implementations	O
consuming	O
less	O
than	O
15	O
W	O
.	O
There	O
were	O
plans	O
for	O
single	O
,	O
dual	O
and	O
quad-core	B-Architecture
versions	O
.	O
</s>
<s>
The	O
Titan	B-General_Concept
had	O
a	O
new	O
superscalar	O
,	O
out	O
of	O
order	O
8-9	O
stage	O
core	B-Architecture
with	O
a	O
novel	O
three-stage	O
CPU	B-General_Concept
cache	I-General_Concept
design	O
.	O
</s>
<s>
Small	O
4/4	O
KiB	O
instruction	O
and	O
data	B-General_Concept
caches	I-General_Concept
at	O
"	O
level	O
0	O
"	O
sit	O
before	O
the	O
traditional	O
32/32	O
KiB	O
L1	O
caches	O
up	O
to	O
1	O
MB	O
L2	O
cache	O
that	O
will	O
be	O
shared	O
between	O
all	O
cores	O
(	O
supporting	O
up	O
to	O
four	O
)	O
.	O
</s>
<s>
The	O
Titan	B-General_Concept
was	O
compliant	O
with	O
the	O
Power	B-Architecture
ISA	I-Architecture
v.2.04	O
.	O
</s>
<s>
APM	O
83290	O
–	O
The	O
first	O
implementations	O
of	O
the	O
Titan	B-General_Concept
core	B-Architecture
design	O
,	O
codenamed	O
Gemeni	O
.	O
</s>
<s>
Two	O
1.5GHz	O
cores	O
with	O
FPU	B-General_Concept
,	O
512	O
kB	O
shared	O
L2	O
cache	O
,	O
DDR2	O
controller	O
,	O
security	O
engine	O
,	O
multi-channel	O
DMA	O
and	O
I/O	O
engine	O
for	O
gigabit	O
Ethernet	O
,	O
PCIe	O
,	O
USB	O
,	O
RapidIO	O
and	O
SATA	O
.	O
</s>
<s>
It	O
is	O
built	O
using	O
TSMC	O
's	O
90nm	O
bulk	O
CMOS	B-Device
fabrication	O
to	O
reduce	O
cost	O
.	O
</s>
