<s>
Tile	B-General_Concept
processors	I-General_Concept
for	O
computer	B-Architecture
hardware	I-Architecture
,	O
are	O
multicore	B-Architecture
or	O
manycore	B-General_Concept
chips	O
that	O
contain	O
one-dimensional	O
,	O
or	O
more	O
commonly	O
,	O
two-dimensional	O
arrays	O
of	O
identical	O
tiles	O
.	O
</s>
<s>
In	O
a	O
typical	O
Tile	B-General_Concept
Processor	I-General_Concept
configuration	O
,	O
the	O
switches	O
in	O
each	O
of	O
the	O
tiles	O
are	O
connected	O
to	O
each	O
other	O
using	O
one	O
or	O
more	O
mesh	B-Architecture
networks	I-Architecture
.	O
</s>
<s>
The	O
Tilera	B-Architecture
TILEPro64	B-General_Concept
,	O
for	O
example	O
,	O
contains	O
64	O
tiles	O
.	O
</s>
<s>
Each	O
of	O
the	O
tiles	O
comprises	O
a	O
CPU	O
,	O
L1	O
and	O
L2	O
caches	O
,	O
and	O
switches	O
for	O
several	O
mesh	B-Architecture
networks	I-Architecture
.	O
</s>
<s>
Other	O
processors	O
in	O
a	O
tile	O
configuration	O
include	O
SEAforth24	O
,	O
Kilocore	B-General_Concept
KC256	O
,	O
XMOS	O
xCORE	O
microcontrollers	O
,	O
and	O
some	O
massively	B-General_Concept
parallel	I-General_Concept
processor	I-General_Concept
arrays	I-General_Concept
.	O
</s>
