<s>
In	O
electronic	O
engineering	O
,	O
a	O
through-silicon	B-Algorithm
via	I-Algorithm
(	O
TSV	O
)	O
or	O
through-chip	B-Algorithm
via	I-Algorithm
is	O
a	O
vertical	O
electrical	B-Protocol
connection	I-Protocol
(	O
via	O
)	O
that	O
passes	O
completely	O
through	O
a	O
silicon	B-Architecture
wafer	I-Architecture
or	O
die	O
.	O
</s>
<s>
TSVs	O
are	O
high-performance	O
interconnect	O
techniques	O
used	O
as	O
an	O
alternative	O
to	O
wire-bond	B-Algorithm
and	O
flip	B-Device
chips	I-Device
to	O
create	O
3D	O
packages	O
and	O
3D	B-Architecture
integrated	I-Architecture
circuits	I-Architecture
.	I-Architecture
</s>
<s>
Compared	O
to	O
alternatives	O
such	O
as	O
package-on-package	B-Algorithm
,	O
the	O
interconnect	O
and	O
device	O
density	O
is	O
substantially	O
higher	O
,	O
and	O
the	O
length	O
of	O
the	O
connections	O
becomes	O
shorter	O
.	O
</s>
<s>
Dictated	O
by	O
the	O
manufacturing	O
process	O
,	O
there	O
exist	O
three	O
different	O
types	O
of	O
TSVs	O
:	O
via-first	O
TSVs	O
are	O
fabricated	B-Architecture
before	O
the	O
individual	O
component	O
(	O
transistors	B-Application
,	O
capacitors	O
,	O
resistors	O
,	O
etc	O
.	O
)	O
</s>
<s>
are	O
patterned	O
(	O
front	B-Algorithm
end	I-Algorithm
of	I-Algorithm
line	I-Algorithm
,	O
FEOL	B-Algorithm
)	O
,	O
via-middle	O
TSVs	O
are	O
fabricated	B-Architecture
after	O
the	O
individual	O
component	O
are	O
patterned	O
but	O
before	O
the	O
metal	O
layers	O
(	O
back-end-of-line	B-Algorithm
,	O
BEOL	B-Algorithm
)	O
,	O
and	O
via-last	O
TSVs	O
are	O
fabricated	B-Architecture
after	O
(	O
or	O
during	O
)	O
the	O
BEOL	B-Algorithm
process	O
.	O
</s>
<s>
Via-middle	O
TSVs	O
are	O
currently	O
a	O
popular	O
option	O
for	O
advanced	O
3D	B-Architecture
ICs	I-Architecture
as	O
well	O
as	O
for	O
interposer	O
stacks	O
.	O
</s>
<s>
TSVs	O
through	O
the	O
front	B-Algorithm
end	I-Algorithm
of	I-Algorithm
line	I-Algorithm
(	O
FEOL	B-Algorithm
)	O
have	O
to	O
be	O
carefully	O
accounted	O
for	O
during	O
the	O
EDA	O
and	O
manufacturing	O
phases	O
.	O
</s>
<s>
That	O
is	O
because	O
TSVs	O
induce	O
thermo-mechanical	O
stress	O
in	O
the	O
FEOL	B-Algorithm
layer	O
,	O
thereby	O
impacting	O
the	O
transistor	B-General_Concept
behaviour	O
.	O
</s>
<s>
CMOS	B-Architecture
image	I-Architecture
sensors	I-Architecture
(	O
CIS	O
)	O
were	O
among	O
the	O
first	O
applications	O
to	O
adopt	O
TSV(s )	O
in	O
volume	O
manufacturing	O
.	O
</s>
<s>
In	O
initial	O
CIS	O
applications	O
,	O
TSVs	O
were	O
formed	O
on	O
the	O
backside	O
of	O
the	O
image	B-Algorithm
sensor	I-Algorithm
wafer	B-Architecture
to	O
form	O
interconnects	O
,	O
eliminate	O
wire	B-Algorithm
bonds	I-Algorithm
,	O
and	O
allow	O
for	O
reduced	O
form	O
factor	O
and	O
higher-density	O
interconnects	O
.	O
</s>
<s>
This	O
was	O
accomplished	O
by	O
flipping	O
the	O
photodiode	O
wafer	B-Architecture
,	O
thinning	O
the	O
backside	O
,	O
and	O
then	O
bonding	O
it	O
on	O
top	O
of	O
the	O
readout	O
layer	O
using	O
a	O
direct	O
oxide	O
bond	O
,	O
with	O
TSVs	O
as	O
interconnects	O
around	O
the	O
perimeter	O
.	O
</s>
<s>
A	O
3D	O
package	O
(	O
System	B-Algorithm
in	I-Algorithm
Package	I-Algorithm
,	O
Chip	B-Algorithm
Stack	I-Algorithm
MCM	I-Algorithm
,	O
etc	O
.	O
)	O
</s>
<s>
An	O
alternate	O
type	O
of	O
3D	O
package	O
can	O
be	O
found	O
in	O
IBM	O
's	O
Silicon	O
Carrier	O
Packaging	O
Technology	O
,	O
where	O
ICs	O
are	O
not	O
stacked	O
but	O
a	O
carrier	O
substrate	B-Architecture
containing	O
TSVs	O
is	O
used	O
to	O
connect	O
multiple	O
ICs	O
together	O
in	O
a	O
package	O
.	O
</s>
<s>
A	O
3D	B-Architecture
integrated	I-Architecture
circuit	I-Architecture
(	O
3D	B-Architecture
IC	I-Architecture
)	O
is	O
a	O
single	O
integrated	O
circuit	O
built	O
by	O
stacking	O
silicon	B-Architecture
wafers	I-Architecture
and/or	O
dies	O
and	O
interconnecting	O
them	O
vertically	O
so	O
that	O
they	O
behave	O
as	O
a	O
single	O
device	O
.	O
</s>
<s>
By	O
using	O
TSV	O
technology	O
,	O
3D	B-Architecture
ICs	I-Architecture
can	O
pack	O
a	O
great	O
deal	O
of	O
functionality	O
into	O
a	O
small	O
“	O
footprint.	O
”	O
The	O
different	O
devices	O
in	O
the	O
stack	O
may	O
be	O
heterogeneous	O
,	O
e.g.	O
</s>
<s>
combining	O
CMOS	B-Device
logic	O
,	O
DRAM	O
and	O
III-V	O
materials	O
into	O
a	O
single	O
IC	O
.	O
</s>
<s>
The	O
origins	O
of	O
the	O
TSV	O
concept	O
can	O
be	O
traced	O
back	O
to	O
William	O
Shockley	O
's	O
patent	O
"	O
Semiconductive	O
Wafer	B-Architecture
and	O
Method	O
of	O
Making	O
the	O
Same	O
"	O
filed	O
in	O
1958	O
and	O
granted	O
in	O
1962	O
,	O
which	O
was	O
further	O
developed	O
by	O
IBM	O
researchers	O
Merlin	O
Smith	O
and	O
Emanuel	O
Stern	O
with	O
their	O
patent	O
"	O
Methods	O
of	O
Making	O
Thru-Connections	O
in	O
Semiconductor	B-Architecture
Wafers	I-Architecture
"	O
filed	O
in	O
1964	O
and	O
granted	O
in	O
1967	O
,	O
the	O
latter	O
describing	O
a	O
method	O
for	O
etching	O
a	O
hole	O
through	O
silicon	O
.	O
</s>
<s>
TSV	O
was	O
not	O
originally	O
designed	O
for	O
3D	O
integration	O
,	O
but	O
the	O
first	O
3D	B-Architecture
chips	I-Architecture
based	O
on	O
TSV	O
were	O
invented	O
later	O
in	O
the	O
1980s	O
.	O
</s>
<s>
The	O
first	O
three-dimensional	B-Architecture
integrated	I-Architecture
circuit	I-Architecture
(	O
3D	B-Architecture
IC	I-Architecture
)	O
stacked	O
chips	O
fabricated	B-Architecture
with	O
a	O
TSV	O
process	O
were	O
invented	O
in	O
1980s	O
Japan	O
.	O
</s>
<s>
In	O
1989	O
,	O
Mitsumasa	O
Koyonagi	O
of	O
Tohoku	O
University	O
pioneered	O
the	O
technique	O
of	O
wafer-to-wafer	O
bonding	O
with	O
TSV	O
,	O
which	O
he	O
used	O
to	O
fabricate	O
a	O
3D	O
LSI	O
chip	O
in	O
1989	O
.	O
</s>
<s>
In	O
1999	O
,	O
the	O
Association	O
of	O
Super-Advanced	O
Electronics	O
Technologies	O
(	O
ASET	O
)	O
in	O
Japan	O
began	O
funding	O
the	O
development	O
of	O
3D	B-Architecture
IC	I-Architecture
chips	O
using	O
TSV	O
technology	O
,	O
called	O
the	O
"	O
R&D	O
on	O
High	O
Density	O
Electronic	O
System	O
Integration	O
Technology	O
"	O
project	O
.	O
</s>
<s>
The	O
Koyanagi	O
Group	O
at	O
Tohoku	O
University	O
used	O
TSV	O
technology	O
to	O
fabricate	O
a	O
three-layer	O
stacked	O
image	B-Algorithm
sensor	I-Algorithm
chip	O
in	O
1999	O
,	O
a	O
three-layer	O
memory	B-Architecture
chip	I-Architecture
in	O
2000	O
,	O
a	O
three-layer	O
artificial	O
retina	O
chip	O
in	O
2001	O
,	O
a	O
three-layer	O
microprocessor	B-Architecture
in	O
2002	O
,	O
and	O
a	O
ten-layer	O
memory	B-Architecture
chip	I-Architecture
in	O
2005	O
.	O
</s>
<s>
The	O
term	O
"	O
through-silicon	B-Algorithm
via	I-Algorithm
"	O
(	O
TSV	O
)	O
was	O
coined	O
by	O
Tru-Si	O
Technologies	O
researchers	O
Sergey	O
Savastiouk	O
,	O
O	O
.	O
Siniaguine	O
,	O
and	O
E	O
.	O
Korczynski	O
,	O
who	O
proposed	O
a	O
TSV	O
method	O
for	O
a	O
3D	O
wafer-level	O
packaging	O
(	O
WLP	O
)	O
solution	O
in	O
2000	O
.	O
</s>
<s>
Savastiouk	O
later	O
became	O
the	O
co-founder	O
and	O
CEO	O
of	O
Inc	O
.	O
From	O
the	O
beginning	O
,	O
his	O
vision	O
of	O
the	O
business	O
plan	O
was	O
to	O
create	O
a	O
through	O
silicon	O
interconnect	O
since	O
these	O
would	O
offer	O
significant	O
performance	O
improvements	O
over	O
wire	B-Algorithm
bonds	I-Algorithm
.	O
</s>
<s>
This	O
article	O
outlined	O
the	O
roadmap	O
of	O
the	O
TSV	O
development	O
as	O
a	O
transition	O
from	O
2D	O
chip	O
stacking	O
to	O
wafer	B-Architecture
level	O
stacking	O
in	O
the	O
future	O
.	O
</s>
<s>
In	O
one	O
of	O
the	O
sections	O
titled	O
Through	B-Algorithm
Silicon	I-Algorithm
Vias	I-Algorithm
,	O
Dr.	O
Sergey	O
Savastiouk	O
wrote	O
,	O
“	O
Investment	O
in	O
technologies	O
that	O
provide	O
both	O
wafer-level	O
vertical	O
miniaturization	O
(	O
wafer	B-Architecture
thinning	O
)	O
and	O
preparation	O
for	O
vertical	O
integration	O
(	O
through	B-Algorithm
silicon	I-Algorithm
vias	I-Algorithm
)	O
makes	O
good	O
sense.	O
”	O
He	O
continued	O
,	O
“	O
By	O
removing	O
the	O
arbitrary	O
2D	O
conceptual	O
barrier	O
associated	O
with	O
Moore	O
’s	O
Law	O
,	O
we	O
can	O
open	O
up	O
a	O
new	O
dimension	O
in	O
ease	O
of	O
design	O
,	O
test	O
,	O
and	O
manufacturing	O
of	O
IC	O
packages	O
.	O
</s>
<s>
When	O
we	O
need	O
it	O
the	O
most	O
–	O
for	O
portable	O
computing	O
,	O
memory	O
cards	O
,	O
smart	O
cards	O
,	O
cellular	O
phones	O
,	O
and	O
other	O
uses	O
–	O
we	O
can	O
follow	O
Moore	O
’s	O
Law	O
into	O
the	O
Z	O
dimension.	O
”	O
This	O
was	O
the	O
first	O
time	O
the	O
term	O
"	O
through-silicon	B-Algorithm
via	I-Algorithm
"	O
was	O
used	O
in	O
a	O
technical	O
publication	O
.	O
</s>
<s>
CMOS	B-Architecture
image	I-Architecture
sensors	I-Architecture
utilising	O
TSV	O
were	O
commercialized	O
by	O
companies	O
including	O
Toshiba	O
,	O
Aptina	O
and	O
STMicroelectronics	O
during	O
20072008	O
,	O
with	O
Toshiba	O
naming	O
their	O
technology	O
"	O
Through	O
Chip	O
Via	O
"	O
(	O
TCV	O
)	O
.	O
</s>
<s>
3D-stacked	O
random-access	B-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
was	O
commercialized	O
by	O
Elpida	O
Memory	O
,	O
which	O
developed	O
the	O
first	O
8GB	O
DRAM	O
chip	O
(	O
stacked	O
with	O
four	O
DDR3	O
SDRAM	O
dies	O
)	O
in	O
September	O
2009	O
,	O
and	O
released	O
it	O
in	O
June	O
2011	O
.	O
</s>
<s>
TSMC	O
announced	O
plans	O
for	O
3D	B-Architecture
IC	I-Architecture
production	O
with	O
TSV	O
technology	O
in	O
January	O
2010	O
.	O
</s>
<s>
In	O
2011	O
,	O
SK	O
Hynix	O
introduced	O
16GB	O
DDR3	O
SDRAM	O
(	O
40nm	O
class	O
)	O
using	O
TSV	O
technology	O
,	O
Samsung	O
Electronics	O
introduced	O
3D-stacked	O
32GB	O
DDR3	O
(	O
30nm	O
class	O
)	O
based	O
on	O
TSV	O
in	O
September	O
,	O
and	O
then	O
Samsung	O
and	O
Micron	O
Technology	O
announced	O
TSV-based	O
Hybrid	B-General_Concept
Memory	I-General_Concept
Cube	I-General_Concept
(	O
HMC	O
)	O
technology	O
in	O
October	O
.	O
</s>
