<s>
Systems	O
implementing	O
three-state	O
logic	O
on	O
their	O
bus	O
are	O
known	O
as	O
a	O
three-state	B-Architecture
bus	I-Architecture
or	O
tri-state	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
For	O
example	O
,	O
in	O
a	O
computer	O
system	O
,	O
multiple	O
devices	O
such	O
as	O
the	O
CPU	O
,	O
memory	O
,	O
and	O
peripherals	O
may	O
be	O
connected	O
to	O
the	O
same	O
data	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
Three-state	O
buffers	O
can	O
also	O
be	O
used	O
to	O
implement	O
efficient	O
multiplexers	B-Protocol
,	O
especially	O
those	O
with	O
large	O
numbers	O
of	O
inputs	O
.	O
</s>
<s>
Three-state	O
buffers	O
are	O
essential	O
to	O
the	O
operation	O
of	O
a	O
shared	O
electronic	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
Many	O
memory	O
devices	O
designed	O
to	O
connect	O
to	O
a	O
bus	O
(	O
such	O
as	O
RAM	O
and	O
ROM	O
chips	O
)	O
have	O
both	O
(	O
chip	B-Architecture
select	I-Architecture
)	O
and	O
(	O
output	O
enable	O
)	O
pins	O
,	O
which	O
superficially	O
appear	O
to	O
do	O
the	O
same	O
thing	O
.	O
</s>
<s>
When	O
chip	B-Architecture
select	I-Architecture
is	O
deasserted	O
,	O
the	O
chip	O
does	O
not	O
operate	O
internally	O
,	O
and	O
there	O
will	O
be	O
a	O
significant	O
delay	O
between	O
providing	O
an	O
address	O
and	O
receiving	O
the	O
data	O
.	O
</s>
<s>
When	O
chip	B-Architecture
select	I-Architecture
is	O
asserted	O
,	O
the	O
chip	O
internally	O
performs	O
the	O
access	O
,	O
and	O
only	O
the	O
final	O
output	O
drivers	O
are	O
disabled	O
by	O
deasserting	O
output	O
enable	O
.	O
</s>
<s>
A	O
ROM	O
or	O
static	O
RAM	O
chip	O
with	O
an	O
output	O
enable	O
line	O
will	O
typically	O
list	O
two	O
access	O
times	O
:	O
one	O
from	O
chip	B-Architecture
select	I-Architecture
asserted	O
and	O
address	O
valid	O
,	O
and	O
a	O
second	O
,	O
shorter	O
time	O
beginning	O
when	O
output	O
enable	O
is	O
asserted	O
.	O
</s>
<s>
The	O
PCI	B-Protocol
local	I-Protocol
bus	I-Protocol
provides	O
pull-up	O
resistors	O
,	O
but	O
they	O
would	O
require	O
several	O
clock	O
cycles	O
to	O
pull	O
a	O
signal	O
high	O
given	O
the	O
bus	O
's	O
large	O
distributed	O
capacitance	O
.	O
</s>
<s>
Early	O
microcontrollers	B-Architecture
often	O
have	O
some	O
pins	O
that	O
can	O
only	O
act	O
as	O
an	O
input	O
,	O
other	O
pins	O
that	O
can	O
only	O
act	O
as	O
a	O
push	O
–	O
pull	O
output	O
,	O
and	O
a	O
few	O
pins	O
that	O
can	O
only	O
act	O
as	O
an	O
open	O
collector	O
input/output	O
.	O
</s>
<s>
A	O
typical	O
modern	O
microcontroller	B-Architecture
has	O
many	O
three-state	O
general-purpose	B-Architecture
input/output	I-Architecture
pins	O
that	O
can	O
be	O
programmed	O
to	O
act	O
as	O
any	O
of	O
those	O
kinds	O
of	O
pins	O
.	O
</s>
<s>
A	O
three-state	B-Architecture
bus	I-Architecture
is	O
typically	O
used	O
between	O
chips	O
on	O
a	O
single	O
printed	O
circuit	O
board	O
(	O
PCB	O
)	O
,	O
or	O
sometimes	O
between	O
PCBs	O
plugged	O
into	O
a	O
common	O
backplane	B-Architecture
.	O
</s>
<s>
Three-state	O
buffers	O
,	O
when	O
used	O
to	O
enable	O
multiple	O
devices	O
to	O
communicate	O
on	O
a	O
data	B-General_Concept
bus	I-General_Concept
,	O
can	O
be	O
functionally	O
replaced	O
by	O
a	O
multiplexer	B-Protocol
.	O
</s>
