<s>
A	O
three-dimensional	B-Architecture
integrated	I-Architecture
circuit	I-Architecture
(	O
3D	B-Architecture
IC	I-Architecture
)	O
is	O
a	O
MOS	B-Architecture
(	O
metal-oxide	O
semiconductor	O
)	O
integrated	O
circuit	O
(	O
IC	O
)	O
manufactured	O
by	O
stacking	O
as	O
many	O
as	O
16	O
or	O
more	O
ICs	O
and	O
interconnecting	O
them	O
vertically	O
using	O
,	O
for	O
instance	O
,	O
through-silicon	B-Algorithm
vias	I-Algorithm
(	O
TSVs	O
)	O
or	O
Cu-Cu	O
connections	B-Protocol
,	O
so	O
that	O
they	O
behave	O
as	O
a	O
single	O
device	O
to	O
achieve	O
performance	O
improvements	O
at	O
reduced	O
power	O
and	O
smaller	O
footprint	O
than	O
conventional	O
two	O
dimensional	O
processes	O
.	O
</s>
<s>
The	O
3DIC	B-Architecture
is	O
one	O
of	O
several	O
3D	O
integration	O
schemes	O
that	O
exploit	O
the	O
z-direction	O
to	O
achieve	O
electrical	O
performance	O
benefits	O
in	O
microelectronics	O
and	O
nanoelectronics	B-Algorithm
.	O
</s>
<s>
3D	B-Architecture
integrated	I-Architecture
circuits	I-Architecture
can	O
be	O
classified	O
by	O
their	O
level	O
of	O
interconnect	B-General_Concept
hierarchy	O
at	O
the	O
global	O
(	O
package	B-Algorithm
)	O
,	O
intermediate	O
(	O
bond	O
pad	O
)	O
and	O
local	O
(	O
transistor	B-Application
)	O
level	O
.	O
</s>
<s>
In	O
general	O
,	O
3D	O
integration	O
is	O
a	O
broad	O
term	O
that	O
includes	O
such	O
technologies	O
as	O
3D	O
wafer-level	O
packaging	B-Algorithm
(	O
3DWLP	O
)	O
;	O
2.5D	O
and	O
3D	O
interposer-based	O
integration	O
;	O
3D	O
stacked	O
ICs	O
(	O
3D-SICs	O
)	O
;	O
3D	O
heterogeneous	B-Algorithm
integration	I-Algorithm
;	O
and	O
3D	O
systems	O
integration	O
.	O
</s>
<s>
As	O
of	O
the	O
2010s	O
,	O
3DICs	B-Architecture
are	O
widely	O
used	O
for	O
NAND	O
flash	B-Device
memory	I-Device
and	O
in	O
mobile	B-Application
devices	I-Application
.	O
</s>
<s>
3D	O
packaging	B-Algorithm
refers	O
to	O
3D	O
integration	O
schemes	O
that	O
rely	O
on	O
traditional	O
interconnection	O
methods	O
such	O
as	O
wire	B-Algorithm
bonding	I-Algorithm
and	O
flip	B-Device
chip	I-Device
to	O
achieve	O
vertical	O
stacking	O
.	O
</s>
<s>
3D	O
packaging	B-Algorithm
can	O
be	O
divided	O
into	O
3D	O
system	B-Algorithm
in	I-Algorithm
package	I-Algorithm
(	O
3D	O
SiP	O
)	O
and	O
3D	O
wafer	B-Architecture
level	O
package	B-Algorithm
(	O
3D	O
WLP	O
)	O
.	O
</s>
<s>
3D	O
SiPs	O
that	O
have	O
been	O
in	O
mainstream	O
manufacturing	O
for	O
some	O
time	O
and	O
have	O
a	O
well-established	O
infrastructure	O
include	O
stacked	O
memory	B-General_Concept
dies	O
interconnected	O
with	O
wire	B-Algorithm
bonds	I-Algorithm
and	O
package	B-Algorithm
on	I-Algorithm
package	I-Algorithm
(	O
PoP	O
)	O
configurations	O
interconnected	O
with	O
wire	B-Algorithm
bonds	I-Algorithm
or	O
flip	B-Device
chip	I-Device
technology	O
.	O
</s>
<s>
3D	O
WLP	O
uses	O
wafer	B-Architecture
level	O
processes	O
such	O
as	O
redistribution	B-Algorithm
layers	I-Algorithm
(	O
RDLs	O
)	O
and	O
wafer	B-Architecture
bumping	O
processes	O
to	O
form	O
interconnects	B-General_Concept
.	O
</s>
<s>
2.5D	O
interposer	O
is	O
a	O
3D	O
WLP	O
that	O
interconnects	B-General_Concept
dies	O
side-by-side	O
on	O
a	O
silicon	O
,	O
glass	O
,	O
or	O
organic	O
interposer	O
using	O
through	B-Algorithm
silicon	I-Algorithm
vias	I-Algorithm
(	O
TSVs	O
)	O
and	O
an	O
RDL	O
.	O
</s>
<s>
In	O
all	O
types	O
of	O
3D	O
packaging	B-Algorithm
,	O
chips	O
in	O
the	O
package	B-Algorithm
communicate	O
using	O
off-chip	O
signaling	O
,	O
much	O
as	O
if	O
they	O
were	O
mounted	O
in	O
separate	O
packages	O
on	O
a	O
normal	O
circuit	O
board	O
.	O
</s>
<s>
3DICs	B-Architecture
can	O
be	O
divided	O
into	O
3D	O
Stacked	O
ICs	O
(	O
3D	O
SIC	O
)	O
,	O
which	O
refers	O
to	O
stacking	O
IC	O
chips	O
using	O
TSV	O
interconnects	B-General_Concept
,	O
and	O
monolithic	O
3DICs	B-Architecture
,	O
which	O
use	O
fab	O
processes	O
to	O
realize	O
3D	O
interconnects	B-General_Concept
at	O
the	O
local	O
levels	O
of	O
the	O
on-chip	O
wiring	O
hierarchy	O
as	O
set	O
forth	O
by	O
the	O
ITRS	O
,	O
this	O
results	O
in	O
direct	O
vertical	O
interconnects	B-General_Concept
between	O
device	O
layers	O
.	O
</s>
<s>
As	O
of	O
the	O
2010s	O
,	O
3DIC	B-Architecture
packages	O
are	O
widely	O
used	O
for	O
NAND	O
flash	B-Device
memory	I-Device
in	O
mobile	B-Application
devices	I-Application
.	O
</s>
<s>
The	O
digital	O
electronics	O
market	O
requires	O
a	O
higher	O
density	O
semiconductor	B-Architecture
memory	I-Architecture
chip	O
to	O
cater	O
to	O
recently	O
released	O
CPU	B-General_Concept
components	O
,	O
and	O
the	O
multiple	O
die	O
stacking	O
technique	O
has	O
been	O
suggested	O
as	O
a	O
solution	O
to	O
this	O
problem	O
.	O
</s>
<s>
JEDEC	O
disclosed	O
the	O
upcoming	O
DRAM	O
technology	O
includes	O
the	O
"	O
3D	O
SiC	O
"	O
die	O
stacking	O
plan	O
at	O
"	O
Server	O
Memory	B-General_Concept
Forum	O
"	O
,	O
November	O
1	O
–	O
2	O
,	O
2011	O
,	O
Santa	O
Clara	O
,	O
CA	O
.	O
</s>
<s>
In	O
August	O
2014	O
,	O
Samsung	O
Electronics	O
started	O
producing	O
64GB	O
SDRAM	O
modules	O
for	O
servers	O
based	O
on	O
emerging	O
DDR4	O
(	O
double-data	O
rate	O
4	O
)	O
memory	B-General_Concept
using	O
3D	O
TSV	O
package	B-Algorithm
technology	O
.	O
</s>
<s>
Newer	O
proposed	O
standards	O
for	O
3D	O
stacked	O
DRAM	O
include	O
Wide	O
I/O	O
,	O
Wide	O
I/O	O
2	O
,	O
Hybrid	B-General_Concept
Memory	I-General_Concept
Cube	I-General_Concept
,	O
High	O
Bandwidth	B-Algorithm
Memory	B-General_Concept
.	O
</s>
<s>
True	O
monolithic	O
3D	B-Architecture
ICs	I-Architecture
are	O
built	O
in	O
layers	O
on	O
a	O
single	O
semiconductor	B-Architecture
wafer	I-Architecture
,	O
which	O
is	O
then	O
diced	B-Algorithm
into	O
3DICs	B-Architecture
.	O
</s>
<s>
There	O
is	O
only	O
one	O
substrate	B-Architecture
,	O
hence	O
no	O
need	O
for	O
aligning	O
,	O
thinning	O
,	O
bonding	O
,	O
or	O
through-silicon	B-Algorithm
vias	I-Algorithm
.	O
</s>
<s>
In	O
general	O
,	O
monolithic	O
3D	B-Architecture
ICs	I-Architecture
are	O
still	O
a	O
developing	O
technology	O
and	O
are	O
considered	O
by	O
most	O
to	O
be	O
several	O
years	O
away	O
from	O
production	O
.	O
</s>
<s>
Process	O
temperature	O
limitations	O
can	O
be	O
addressed	O
by	O
partitioning	O
the	O
transistor	B-Application
fabrication	B-Architecture
into	O
two	O
phases	O
.	O
</s>
<s>
A	O
high	O
temperature	O
phase	O
which	O
is	O
done	O
before	O
layer	O
transfer	O
followed	O
by	O
a	O
layer	O
transfer	O
using	O
,	O
also	O
known	O
as	O
layer	O
transfer	O
,	O
which	O
has	O
been	O
used	O
to	O
produce	O
Silicon	B-Algorithm
on	I-Algorithm
Insulator	I-Algorithm
(	O
SOI	O
)	O
wafers	B-Architecture
for	O
the	O
past	O
two	O
decades	O
.	O
</s>
<s>
Multiple	O
thin	O
(	O
10s	O
–	O
100s	O
nanometer	O
scale	O
)	O
layers	O
of	O
virtually	O
defect-free	O
Silicon	O
can	O
be	O
created	O
by	O
utilizing	O
low	O
temperature	O
(	O
<	O
400°C	O
)	O
bond	O
and	O
cleave	O
techniques	O
,	O
and	O
placed	O
on	O
top	O
of	O
active	O
transistor	B-Application
circuitry	O
.	O
</s>
<s>
Follow	O
by	O
finalizing	O
the	O
transistors	B-Application
using	O
etch	O
and	O
deposition	O
processes	O
.	O
</s>
<s>
This	O
monolithic	O
3DIC	B-Architecture
technology	O
has	O
been	O
researched	O
at	O
Stanford	O
University	O
under	O
a	O
DARPA-sponsored	O
grant	O
.	O
</s>
<s>
CEA-Leti	O
also	O
developed	O
monolithic	O
3DIC	B-Architecture
approaches	O
,	O
called	O
sequential	O
3DIC	B-Architecture
.	O
</s>
<s>
At	O
Stanford	O
University	O
,	O
researchers	O
designed	O
monolithic	O
3DICs	B-Architecture
using	O
carbon	O
nanotube	O
(	O
CNT	O
)	O
structures	O
vs.	O
silicon	O
using	O
a	O
wafer-scale	O
low	O
temperature	O
CNT	O
transfer	O
processes	O
that	O
can	O
be	O
done	O
at	O
120°C	O
.	O
</s>
<s>
There	O
are	O
several	O
methods	O
for	O
3D	B-Architecture
IC	I-Architecture
design	O
,	O
including	O
recrystallization	O
and	O
wafer	B-Algorithm
bonding	I-Algorithm
methods	O
.	O
</s>
<s>
There	O
are	O
two	O
major	O
types	O
of	O
wafer	B-Algorithm
bonding	I-Algorithm
,	O
Cu-Cu	O
connections	B-Protocol
(	O
copper-to-copper	O
connections	B-Protocol
between	O
stacked	O
ICs	O
,	O
used	O
in	O
TSVs	O
)	O
and	O
through-silicon	B-Algorithm
via	I-Algorithm
(	O
TSV	O
)	O
.	O
</s>
<s>
As	O
of	O
2014	O
,	O
a	O
number	O
of	O
memory	B-General_Concept
products	O
such	O
as	O
High	O
Bandwidth	B-Algorithm
Memory	B-General_Concept
(	O
HBM	O
)	O
and	O
the	B-General_Concept
Hybrid	I-General_Concept
Memory	I-General_Concept
Cube	I-General_Concept
have	O
been	O
launched	O
that	O
implement	O
3DIC	B-Architecture
stacking	O
with	O
TSVs	O
.	O
</s>
<s>
These	O
include	O
die-to-die	O
,	O
die-to-wafer	O
,	O
and	O
wafer-to-wafer	O
.	O
</s>
<s>
Moreover	O
,	O
each	O
die	O
in	O
the	O
3DIC	B-Architecture
can	O
be	O
binned	O
beforehand	O
,	O
so	O
that	O
they	O
can	O
be	O
mixed	O
and	O
matched	O
to	O
optimize	O
power	O
consumption	O
and	O
performance	O
(	O
e.g.	O
</s>
<s>
Die-to-Wafer	O
Electronic	O
components	O
are	O
built	O
on	O
two	O
semiconductor	B-Architecture
wafers	I-Architecture
.	O
</s>
<s>
One	O
wafer	B-Architecture
is	O
diced	B-Algorithm
;	O
the	O
singulated	O
dice	O
are	O
aligned	O
and	O
bonded	O
onto	O
die	O
sites	O
of	O
the	O
second	O
wafer	B-Architecture
.	O
</s>
<s>
As	O
in	O
the	O
wafer-on-wafer	O
method	O
,	O
thinning	O
and	O
TSV	O
creation	O
are	O
performed	O
either	O
before	O
or	O
after	O
bonding	O
.	O
</s>
<s>
Wafer-to-Wafer	O
Electronic	O
components	O
are	O
built	O
on	O
two	O
or	O
more	O
semiconductor	B-Architecture
wafers	I-Architecture
,	O
which	O
are	O
then	O
aligned	O
,	O
bonded	O
,	O
and	O
diced	B-Algorithm
into	O
3DICs	B-Architecture
.	O
</s>
<s>
Each	O
wafer	B-Architecture
may	O
be	O
thinned	O
before	O
or	O
after	O
bonding	O
.	O
</s>
<s>
Vertical	O
connections	B-Protocol
are	O
either	O
built	O
into	O
the	O
wafers	B-Architecture
before	O
bonding	O
or	O
else	O
created	O
in	O
the	O
stack	O
after	O
bonding	O
.	O
</s>
<s>
These	O
"	O
through-silicon	B-Algorithm
vias	I-Algorithm
"	O
(	O
TSVs	O
)	O
pass	O
through	O
the	O
silicon	O
substrate(s )	O
between	O
active	O
layers	O
and/or	O
between	O
an	O
active	O
layer	O
and	O
an	O
external	O
bond	O
pad	O
.	O
</s>
<s>
Wafer-to-wafer	O
bonding	O
can	O
reduce	O
yields	O
,	O
since	O
if	O
any	O
1	O
of	O
N	O
chips	O
in	O
a	O
3DIC	B-Architecture
are	O
defective	O
,	O
the	O
entire	O
3DIC	B-Architecture
will	O
be	O
defective	O
.	O
</s>
<s>
Moreover	O
,	O
the	O
wafers	B-Architecture
must	O
be	O
the	O
same	O
size	O
,	O
but	O
many	O
exotic	O
materials	O
(	O
e.g.	O
</s>
<s>
III-Vs	O
)	O
are	O
manufactured	O
on	O
much	O
smaller	O
wafers	B-Architecture
than	O
CMOS	B-Device
logic	O
or	O
DRAM	O
(	O
typically	O
300mm	O
)	O
,	O
complicating	O
heterogeneous	B-Algorithm
integration	I-Algorithm
.	O
</s>
<s>
While	O
traditional	O
CMOS	B-Device
scaling	O
processes	O
improves	O
signal	O
propagation	O
speed	O
,	O
scaling	O
from	O
current	O
manufacturing	O
and	O
chip-design	O
technologies	O
is	O
becoming	O
more	O
difficult	O
and	O
costly	O
,	O
in	O
part	O
because	O
of	O
power-density	O
constraints	O
,	O
and	O
in	O
part	O
because	O
interconnects	B-General_Concept
do	O
not	O
become	O
faster	O
while	O
transistors	B-Application
do	O
.	O
</s>
<s>
3DICs	B-Architecture
address	O
the	O
scaling	O
challenge	O
by	O
stacking	O
2D	O
dies	O
and	O
connecting	O
them	O
in	O
the	O
3rd	O
dimension	O
.	O
</s>
<s>
3DICs	B-Architecture
promise	O
many	O
significant	O
benefits	O
,	O
including	O
:	O
</s>
<s>
Cost	O
Partitioning	O
a	O
large	O
chip	O
into	O
multiple	O
smaller	O
dies	O
with	O
3D	O
stacking	O
can	O
improve	O
the	O
yield	O
and	O
reduce	O
the	O
fabrication	B-Architecture
cost	O
if	O
individual	O
dies	O
are	O
tested	O
separately	O
.	O
</s>
<s>
Heterogeneous	B-Algorithm
integration	I-Algorithm
Circuit	O
layers	O
can	O
be	O
built	O
with	O
different	O
processes	O
,	O
or	O
even	O
on	O
different	O
types	O
of	O
wafers	B-Architecture
.	O
</s>
<s>
This	O
means	O
that	O
components	O
can	O
be	O
optimized	O
to	O
a	O
much	O
greater	O
degree	O
than	O
if	O
they	O
were	O
built	O
together	O
on	O
a	O
single	O
wafer	B-Architecture
.	O
</s>
<s>
Moreover	O
,	O
components	O
with	O
incompatible	O
manufacturing	O
could	O
be	O
combined	O
in	O
a	O
single	O
3DIC	B-Architecture
.	O
</s>
<s>
Shorter	O
interconnect	B-General_Concept
The	O
average	O
wire	O
length	O
is	O
reduced	O
.	O
</s>
<s>
Common	O
figures	O
reported	O
by	O
researchers	O
are	O
on	O
the	O
order	O
of	O
10	O
–	O
15%	O
,	O
but	O
this	O
reduction	O
mostly	O
applies	O
to	O
longer	O
interconnect	B-General_Concept
,	O
which	O
may	O
affect	O
circuit	O
delay	O
by	O
a	O
greater	O
amount	O
.	O
</s>
<s>
The	O
objective	O
here	O
is	O
to	O
implement	O
some	O
kind	O
of	O
hardware	O
firewall	B-Application
for	O
any	O
commodity	O
components/chips	O
to	O
be	O
monitored	O
at	O
runtime	O
,	O
seeking	O
to	O
protect	O
the	O
whole	O
electronic	O
system	O
against	O
run-time	O
attacks	O
as	O
well	O
as	O
malicious	O
hardware	O
modifications	O
.	O
</s>
<s>
Bandwidth	B-Algorithm
3D	O
integration	O
allows	O
large	O
numbers	O
of	O
vertical	O
vias	O
between	O
the	O
layers	O
.	O
</s>
<s>
This	O
allows	O
construction	O
of	O
wide	O
bandwidth	B-Algorithm
buses	B-General_Concept
between	O
functional	O
blocks	O
in	O
different	O
layers	O
.	O
</s>
<s>
A	O
typical	O
example	O
would	O
be	O
a	O
processor+memory	O
3D	O
stack	O
,	O
with	O
the	O
cache	O
memory	B-General_Concept
stacked	O
on	O
top	O
of	O
the	O
processor	O
.	O
</s>
<s>
Wide	O
buses	B-General_Concept
in	O
turn	O
alleviate	O
the	O
memory	B-General_Concept
wall	O
problem	O
.	O
</s>
<s>
Cost	O
While	O
cost	O
is	O
a	O
benefit	O
when	O
compared	O
with	O
scaling	O
,	O
it	O
has	O
also	O
been	O
identified	O
as	O
a	O
challenge	O
to	O
the	O
commercialization	O
of	O
3DICs	B-Architecture
in	O
mainstream	O
consumer	O
applications	O
.	O
</s>
<s>
In	O
order	O
for	O
3DICs	B-Architecture
to	O
be	O
commercially	O
viable	O
,	O
defects	O
could	O
be	O
repaired	O
or	O
tolerated	O
,	O
or	O
defect	O
density	O
can	O
be	O
improved	O
.	O
</s>
<s>
Design	O
complexity	O
Taking	O
full	O
advantage	O
of	O
3D	O
integration	O
requires	O
sophisticated	O
design	O
techniques	O
and	O
new	O
CAD	B-Application
tools	O
.	O
</s>
<s>
However	O
,	O
tight	O
integration	O
between	O
adjacent	O
active	O
layers	O
in	O
3DICs	B-Architecture
entails	O
a	O
significant	O
amount	O
of	O
interconnect	B-General_Concept
between	O
different	O
sections	O
of	O
the	O
same	O
circuit	O
module	O
that	O
were	O
partitioned	O
to	O
different	O
dies	O
.	O
</s>
<s>
Lack	O
of	O
standards	O
There	O
are	O
few	O
standards	O
for	O
TSV-based	O
3DIC	B-Architecture
design	O
,	O
manufacturing	O
,	O
and	O
packaging	B-Algorithm
,	O
although	O
this	O
issue	O
is	O
being	O
addressed	O
.	O
</s>
<s>
Heterogeneous	B-Algorithm
integration	I-Algorithm
supply	O
chain	O
In	O
heterogeneously	O
integrated	O
systems	O
,	O
the	O
delay	O
of	O
one	O
part	O
from	O
one	O
of	O
the	O
different	O
parts	O
suppliers	O
delays	O
the	O
delivery	O
of	O
the	O
whole	O
product	O
,	O
and	O
so	O
delays	O
the	O
revenue	O
for	O
each	O
of	O
the	O
3DIC	B-Architecture
part	O
suppliers	O
.	O
</s>
<s>
Lack	O
of	O
clearly	O
defined	O
ownership	O
It	O
is	O
unclear	O
who	O
should	O
own	O
the	O
3DIC	B-Architecture
integration	O
and	O
packaging/assembly	O
.	O
</s>
<s>
On	O
the	O
other	O
hand	O
,	O
its	O
adverse	O
effects	O
include	O
the	O
massive	O
number	O
of	O
necessary	O
TSVs	O
for	O
interconnects	B-General_Concept
.	O
</s>
<s>
This	O
style	O
also	O
amplifies	O
the	O
impact	O
of	O
process	B-Algorithm
variation	I-Algorithm
,	O
especially	O
inter-die	O
variation	O
.	O
</s>
<s>
In	O
fact	O
,	O
a	O
3D	O
layout	O
may	O
yield	O
more	O
poorly	O
than	O
the	O
same	O
circuit	O
laid	O
out	O
in	O
2D	O
,	O
contrary	O
to	O
the	O
original	O
promise	O
of	O
3DIC	B-Architecture
integration	O
.	O
</s>
<s>
Furthermore	O
,	O
this	O
design	O
style	O
requires	O
to	O
redesign	O
available	O
Intellectual	O
Property	O
,	O
since	O
existing	O
IP	B-Architecture
blocks	I-Architecture
and	O
EDA	O
tools	O
do	O
not	O
provision	O
for	O
3D	O
integration	O
.	O
</s>
<s>
Design	O
blocks	O
subsume	O
most	O
of	O
the	O
netlist	O
connectivity	O
and	O
are	O
linked	O
by	O
a	O
small	O
number	O
of	O
global	O
interconnects	B-General_Concept
.	O
</s>
<s>
Sophisticated	O
3D	O
systems	O
combining	O
heterogeneous	O
dies	O
require	O
distinct	O
manufacturing	O
processes	O
at	O
different	O
technology	O
nodes	O
for	O
fast	O
and	O
low-power	O
random	O
logic	O
,	O
several	O
memory	B-General_Concept
types	O
,	O
analog	O
and	O
RF	O
circuits	O
,	O
etc	O
.	O
</s>
<s>
Furthermore	O
,	O
this	O
style	O
might	O
facilitate	O
the	O
transition	O
from	O
current	O
2D	O
design	O
towards	O
3DIC	B-Architecture
design	O
.	O
</s>
<s>
This	O
is	O
motivated	O
by	O
the	O
broad	O
availability	O
of	O
reliable	O
IP	B-Architecture
blocks	I-Architecture
.	O
</s>
<s>
It	O
is	O
more	O
convenient	O
to	O
use	O
available	O
2D	O
IP	B-Architecture
blocks	I-Architecture
and	O
to	O
place	O
the	O
mandatory	O
TSVs	O
in	O
the	O
unoccupied	O
space	O
between	O
blocks	O
instead	O
of	O
redesigning	O
IP	B-Architecture
blocks	I-Architecture
and	O
embedding	O
TSVs	O
.	O
</s>
<s>
Design-for-testability	O
structures	O
are	O
a	O
key	O
component	O
of	O
IP	B-Architecture
blocks	I-Architecture
and	O
can	O
therefore	O
be	O
used	O
to	O
facilitate	O
testing	O
for	O
3DICs	B-Architecture
.	O
</s>
<s>
Also	O
,	O
critical	O
paths	O
can	O
be	O
mostly	O
embedded	B-Architecture
within	O
2D	O
blocks	O
,	O
which	O
limits	O
the	O
impact	O
of	O
TSV	O
and	O
inter-die	O
variation	O
on	O
manufacturing	O
yield	O
.	O
</s>
<s>
Several	O
years	O
after	O
the	O
MOS	B-Architecture
integrated	O
circuit	O
(	O
MOS	B-Architecture
IC	O
)	O
chip	O
was	O
first	O
proposed	O
by	O
Mohamed	O
Atalla	O
at	O
Bell	O
Labs	O
in	O
1960	O
,	O
the	O
concept	O
of	O
a	O
three-dimensional	O
MOS	B-Architecture
integrated	O
circuit	O
was	O
proposed	O
by	O
Texas	O
Instruments	O
researchers	O
Robert	O
W	O
.	O
Haisty	O
,	O
Rowland	O
E	O
.	O
Johnson	O
and	O
Edward	O
W	O
.	O
Mehal	O
in	O
1964	O
.	O
</s>
<s>
In	O
1969	O
,	O
the	O
concept	O
of	O
a	O
three-dimensional	O
MOS	B-Architecture
integrated	O
circuit	O
memory	B-Architecture
chip	I-Architecture
was	O
proposed	O
by	O
NEC	O
researchers	O
Katsuhiro	O
Onoda	O
,	O
Ryo	O
Igarashi	O
,	O
Toshio	O
Wada	O
,	O
Sho	O
Nakanuma	O
and	O
Toru	O
Tsujide	O
.	O
</s>
<s>
Arm	O
has	O
made	O
a	O
high-density	O
3D	O
logic	O
test	O
chip	O
,	O
and	O
Intel	O
with	O
its	O
Foveros	B-Architecture
3D	O
logic	O
chip	O
packing	O
is	O
planning	O
to	O
ship	O
CPUs	O
using	O
it	O
.	O
</s>
<s>
3D	B-Architecture
ICs	I-Architecture
were	O
first	O
successfully	O
demonstrated	O
in	O
1980s	O
Japan	O
,	O
where	O
research	O
and	O
development	O
(	O
R&D	O
)	O
on	O
3DICs	B-Architecture
was	O
initiated	O
in	O
1981	O
with	O
the	O
"	O
Three	O
Dimensional	O
Circuit	O
Element	O
R&D	O
Project	O
"	O
by	O
the	O
Research	O
and	O
Development	O
Association	O
for	O
Future	O
(	O
New	O
)	O
Electron	O
Devices	O
.	O
</s>
<s>
There	O
were	O
initially	O
two	O
forms	O
of	O
3DIC	B-Architecture
design	O
being	O
investigated	O
,	O
recrystallization	O
and	O
wafer	B-Algorithm
bonding	I-Algorithm
,	O
with	O
the	O
earliest	O
successful	O
demonstrations	O
using	O
recrystallization	O
.	O
</s>
<s>
In	O
October	O
1983	O
,	O
a	O
Fujitsu	O
research	O
team	O
including	O
S	O
.	O
Kawamura	O
,	O
Nobuo	O
Sasaki	O
and	O
T	O
.	O
Iwai	O
successfully	O
fabricated	B-Architecture
a	O
three-dimensional	O
complementary	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
(	O
CMOS	B-Device
)	O
integrated	O
circuit	O
,	O
using	O
laser	O
beam	O
recrystallization	O
.	O
</s>
<s>
It	O
consisted	O
of	O
a	O
structure	O
in	O
which	O
one	O
type	O
of	O
transistor	B-Application
is	O
fabricated	B-Architecture
directly	O
above	O
a	O
transistor	B-Application
of	O
the	O
opposite	O
type	O
,	O
with	O
separate	O
gates	O
and	O
an	O
insulator	O
in	O
between	O
.	O
</s>
<s>
This	O
provided	O
the	O
basis	O
for	O
realizing	O
a	O
multi-layered	O
3D	O
device	O
composed	O
of	O
vertically-stacked	O
transistors	B-Application
,	O
with	O
separate	O
gates	O
and	O
an	O
insulating	O
layer	O
in	O
between	O
.	O
</s>
<s>
In	O
December	O
1983	O
,	O
the	O
same	O
Fujitsu	O
research	O
team	O
fabricated	B-Architecture
a	O
3D	B-Architecture
integrated	I-Architecture
circuit	I-Architecture
with	O
a	O
silicon-on-insulator	B-Algorithm
(	O
SOI	O
)	O
CMOS	B-Device
structure	O
.	O
</s>
<s>
The	O
following	O
year	O
,	O
they	O
fabricated	B-Architecture
a	O
3D	O
gate	O
array	O
with	O
vertically-stacked	O
dual	O
SOI/CMOS	O
structure	O
using	O
beam	O
recrystallization	O
.	O
</s>
<s>
In	O
1986	O
,	O
Mitsubishi	O
Electric	O
researchers	O
Yoichi	O
Akasaka	O
and	O
Tadashi	O
Nishimura	O
laid	O
out	O
the	O
basic	O
concepts	O
and	O
proposed	O
technologies	O
for	O
3DICs	B-Architecture
.	O
</s>
<s>
The	O
following	O
year	O
,	O
a	O
Mitsubishi	O
research	O
team	O
including	O
Nishimura	O
,	O
Akasaka	O
and	O
Osaka	O
University	O
graduate	O
Yasuo	O
Inoue	O
fabricated	B-Architecture
an	O
image	B-General_Concept
signal	I-General_Concept
processor	I-General_Concept
(	O
ISP	O
)	O
on	O
a	O
3DIC	B-Architecture
,	O
with	O
an	O
array	O
of	O
photosensors	O
,	O
CMOS	B-Device
A-to-D	O
converters	O
,	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
(	O
ALU	O
)	O
and	O
shift	B-General_Concept
registers	I-General_Concept
arranged	O
in	O
a	O
three-layer	O
structure	O
.	O
</s>
<s>
In	O
1989	O
,	O
an	O
NEC	O
research	O
team	O
led	O
by	O
Yoshihiro	O
Hayashi	O
fabricated	B-Architecture
a	O
3DIC	B-Architecture
with	O
a	O
four-layer	O
structure	O
using	O
laser	O
beam	O
crystallisation	O
.	O
</s>
<s>
In	O
1990	O
,	O
a	O
Matsushita	O
research	O
team	O
including	O
K	O
.	O
Yamazaki	O
,	O
Y	O
.	O
Itoh	O
and	O
A	O
.	O
Wada	O
fabricated	B-Architecture
a	O
parallel	B-Operating_System
image	B-General_Concept
signal	I-General_Concept
processor	I-General_Concept
on	O
a	O
four-layer	O
3DIC	B-Architecture
,	O
with	O
SOI	O
(	O
silicon-on-insulator	B-Algorithm
)	O
layers	O
formed	O
by	O
laser	O
recrystallization	O
,	O
and	O
the	O
four	O
layers	O
consisting	O
of	O
an	O
optical	B-Application
sensor	I-Application
,	O
level	O
detector	B-Application
,	O
memory	B-General_Concept
and	O
ALU	O
.	O
</s>
<s>
The	O
most	O
common	O
form	O
of	O
3D	B-Architecture
IC	I-Architecture
design	O
is	O
wafer	B-Algorithm
bonding	I-Algorithm
.	O
</s>
<s>
Wafer	B-Algorithm
bonding	I-Algorithm
was	O
initially	O
called	O
"	O
cumulatively	O
bonded	O
IC	O
"	O
(	O
CUBIC	O
)	O
,	O
which	O
began	O
development	O
in	O
1981	O
with	O
the	O
"	O
Three	O
Dimensional	O
Circuit	O
Element	O
R&D	O
Project	O
"	O
in	O
Japan	O
and	O
was	O
completed	O
in	O
1990	O
by	O
Yoshihiro	O
Hayashi	O
's	O
NEC	O
research	O
team	O
,	O
who	O
demonstrated	O
a	O
method	O
where	O
several	O
thin-film	O
devices	O
are	O
bonded	O
cumulatively	O
,	O
which	O
would	O
allow	O
a	O
large	O
number	O
of	O
device	O
layers	O
.	O
</s>
<s>
They	O
proposed	O
fabrication	B-Architecture
of	O
separate	O
devices	O
in	O
separate	O
wafers	B-Architecture
,	O
reduction	O
in	O
the	O
thickness	O
of	O
the	O
wafers	B-Architecture
,	O
providing	O
front	O
and	O
back	O
leads	O
,	O
and	O
connecting	O
the	O
thinned	O
die	O
to	O
each	O
other	O
.	O
</s>
<s>
They	O
used	O
CUBIC	O
technology	O
to	O
fabricate	O
and	O
test	O
a	O
two	O
active	O
layer	O
device	O
in	O
a	O
top-to-bottom	O
fashion	O
,	O
having	O
a	O
bulk-Si	O
NMOS	B-Architecture
FET	I-Architecture
lower	O
layer	O
and	O
a	O
thinned	O
NMOS	B-Architecture
FET	I-Architecture
upper	O
layer	O
,	O
and	O
proposed	O
CUBIC	O
technology	O
that	O
could	O
fabricate	O
3DICs	B-Architecture
with	O
more	O
than	O
three	O
active	O
layers	O
.	O
</s>
<s>
The	O
first	O
3D	B-Architecture
IC	I-Architecture
stacked	O
chips	O
fabricated	B-Architecture
with	O
a	O
through-silicon	B-Algorithm
via	I-Algorithm
(	O
TSV	O
)	O
process	O
were	O
invented	O
in	O
1980s	O
Japan	O
.	O
</s>
<s>
In	O
1989	O
,	O
Mitsumasa	O
Koyonagi	O
of	O
Tohoku	O
University	O
pioneered	O
the	O
technique	O
of	O
wafer-to-wafer	O
bonding	O
with	O
TSV	O
,	O
which	O
he	O
used	O
to	O
fabricate	O
a	O
3D	O
LSI	O
chip	O
in	O
1989	O
.	O
</s>
<s>
In	O
1999	O
,	O
the	O
Association	O
of	O
Super-Advanced	O
Electronics	O
Technologies	O
(	O
ASET	O
)	O
in	O
Japan	O
began	O
funding	O
the	O
development	O
of	O
3DIC	B-Architecture
chips	O
using	O
TSV	O
technology	O
,	O
called	O
the	O
"	O
R&D	O
on	O
High	O
Density	O
Electronic	O
System	O
Integration	O
Technology	O
"	O
project	O
.	O
</s>
<s>
The	O
term	O
"	O
through-silicon	B-Algorithm
via	I-Algorithm
"	O
(	O
TSV	O
)	O
was	O
coined	O
by	O
Tru-Si	O
Technologies	O
researchers	O
Sergey	O
Savastiouk	O
,	O
O	O
.	O
Siniaguine	O
,	O
and	O
E	O
.	O
Korczynski	O
,	O
who	O
proposed	O
a	O
TSV	O
method	O
for	O
a	O
3D	O
wafer-level	O
packaging	B-Algorithm
(	O
WLP	O
)	O
solution	O
in	O
2000	O
.	O
</s>
<s>
The	O
Koyanagi	O
Group	O
at	O
Tohoku	O
University	O
,	O
led	O
by	O
Mitsumasa	O
Koyanagi	O
,	O
used	O
TSV	O
technology	O
to	O
fabricate	O
a	O
three-layer	O
memory	B-Architecture
chip	I-Architecture
in	O
2000	O
,	O
a	O
three-layer	O
artificial	O
retina	O
chip	O
in	O
2001	O
,	O
a	O
three-layer	O
microprocessor	B-Architecture
in	O
2002	O
,	O
and	O
a	O
ten-layer	O
memory	B-Architecture
chip	I-Architecture
in	O
2005	O
.	O
</s>
<s>
The	O
same	O
year	O
,	O
a	O
Stanford	O
University	O
research	O
team	O
consisting	O
of	O
Kaustav	O
Banerjee	O
,	O
Shukri	O
J	O
.	O
Souri	O
,	O
Pawan	O
Kapur	O
and	O
Krishna	O
C	O
.	O
Saraswat	O
presented	O
a	O
novel	O
3D	B-Architecture
chip	I-Architecture
design	O
that	O
exploits	O
the	O
vertical	O
dimension	O
to	O
alleviate	O
the	O
interconnect	B-General_Concept
related	O
problems	O
and	O
facilitates	O
heterogeneous	B-Algorithm
integration	I-Algorithm
of	O
technologies	O
to	O
realize	O
a	O
system-on-a-chip	B-Architecture
(	O
SoC	O
)	O
design	O
.	O
</s>
<s>
In	O
2001	O
,	O
a	O
Toshiba	O
research	O
team	O
including	O
T	O
.	O
Imoto	O
,	O
M	O
.	O
Matsui	O
and	O
C	O
.	O
Takubo	O
developed	O
a	O
"	O
System	O
Block	O
Module	O
"	O
wafer	B-Algorithm
bonding	I-Algorithm
process	O
for	O
manufacturing	O
3DIC	B-Architecture
packages	O
.	O
</s>
<s>
Fraunhofer	O
and	O
Siemens	O
began	O
research	O
on	O
3DIC	B-Architecture
integration	O
in	O
1987	O
.	O
</s>
<s>
In	O
1988	O
,	O
they	O
fabricated	B-Architecture
3D	O
CMOS	B-Device
IC	O
devices	O
based	O
on	O
re-crystallization	O
of	O
poly-silicon	O
.	O
</s>
<s>
It	O
was	O
a	O
first	O
industrial	O
3DIC	B-Architecture
process	O
,	O
based	O
on	O
Siemens	O
CMOS	B-Device
fab	O
wafers	B-Architecture
.	O
</s>
<s>
It	O
was	O
an	O
approach	O
to	O
3DIC	B-Architecture
design	O
based	O
on	O
low	O
temperature	O
wafer	B-Algorithm
bonding	I-Algorithm
and	O
vertical	O
integration	O
of	O
IC	O
devices	O
using	O
inter-chip	O
vias	O
,	O
which	O
they	O
patented	O
.	O
</s>
<s>
In	O
the	O
German	O
funded	O
cooperative	O
VIC	O
project	O
between	O
Siemens	O
and	O
Fraunhofer	O
,	O
they	O
demonstrated	O
a	O
complete	O
industrial	O
3DIC	B-Architecture
stacking	O
process	O
(	O
1993	O
–	O
1996	O
)	O
.	O
</s>
<s>
With	O
his	O
Siemens	O
and	O
Fraunhofer	O
colleagues	O
,	O
Ramm	O
published	O
results	O
showing	O
the	O
details	O
of	O
key	O
processes	O
such	O
as	O
3D	O
metallization	O
[	O
T	O
.	O
Grassl	O
,	O
P	O
.	O
Ramm	O
,	O
M	O
.	O
Engelhardt	O
,	O
Z	O
.	O
Gabric	O
,	O
O	O
.	O
Spindler	O
,	O
First	O
International	O
Dielectrics	O
for	O
VLSI/ULSI	O
Interconnection	O
Metallization	O
Conference	O
–	O
DUMIC	O
,	O
Santa	O
Clara	O
,	O
CA	O
,	O
20	O
–	O
22	O
Feb	O
,	O
1995 ]	O
and	O
at	O
ECTC	O
1995	O
they	O
presented	O
early	O
investigations	O
on	O
stacked	O
memory	B-General_Concept
in	O
processors	O
.	O
</s>
<s>
In	O
the	O
early	O
2000s	O
,	O
a	O
team	O
of	O
Fraunhofer	O
and	O
Infineon	O
Munich	O
researchers	O
investigated	O
3D	O
TSV	O
technologies	O
with	O
particular	O
focus	O
on	O
die-to-substrate	O
stacking	O
within	O
the	O
German/Austrian	O
EUREKA	O
project	O
VSI	O
and	O
initiated	O
the	O
European	O
Integrating	O
Projects	O
e-CUBES	O
,	O
as	O
a	O
first	O
European	O
3D	O
technology	O
platform	O
,	O
and	O
e-BRAINS	O
with	O
a.o.	O
,	O
Infineon	O
,	O
Siemens	O
,	O
EPFL	O
,	O
IMEC	O
and	O
Tyndall	O
,	O
where	O
heterogeneous	O
3D	O
integrated	O
system	O
demonstrators	O
were	O
fabricated	B-Architecture
and	O
evaluated	O
.	O
</s>
<s>
Copper-to-copper	O
wafer	B-Algorithm
bonding	I-Algorithm
,	O
also	O
called	O
Cu-Cu	O
connections	B-Protocol
or	O
Cu-Cu	O
wafer	B-Algorithm
bonding	I-Algorithm
,	O
was	O
developed	O
at	O
MIT	O
by	O
a	O
research	O
team	O
consisting	O
of	O
Andy	O
Fan	O
,	O
Adnan-ur	O
Rahman	O
and	O
Rafael	O
Reif	O
in	O
1999	O
.	O
</s>
<s>
Reif	O
and	O
Fan	O
further	O
investigated	O
Cu-Cu	O
wafer	B-Algorithm
bonding	I-Algorithm
with	O
other	O
MIT	O
researchers	O
including	O
Kuan-Neng	O
Chen	O
,	O
Shamik	O
Das	O
,	O
Chuan	O
Seng	O
Tan	O
and	O
Nisha	O
Checka	O
during	O
20012002	O
.	O
</s>
<s>
In	O
2003	O
,	O
DARPA	O
and	O
the	O
Microelectronics	O
Center	O
of	O
North	O
Carolina	O
(	O
MCNC	O
)	O
began	O
funding	O
R&D	O
on	O
3DIC	B-Architecture
technology	O
.	O
</s>
<s>
Two	O
wafers	B-Architecture
were	O
stacked	O
face-to-face	O
and	O
bonded	O
with	O
a	O
copper	O
process	O
.	O
</s>
<s>
The	O
top	O
wafer	B-Architecture
was	O
thinned	O
and	O
the	O
two-wafer	O
stack	O
was	O
then	O
diced	B-Algorithm
into	O
chips	O
.	O
</s>
<s>
The	O
first	O
chip	O
tested	O
was	O
a	O
simple	O
memory	B-General_Concept
register	O
,	O
but	O
the	O
most	O
notable	O
of	O
the	O
set	O
was	O
an	O
8051	O
processor/memory	O
stack	O
that	O
exhibited	O
much	O
higher	O
speed	O
and	O
lower	O
power	O
consumption	O
than	O
an	O
analogous	O
2D	O
assembly	O
.	O
</s>
<s>
In	O
2004	O
,	O
Intel	O
presented	O
a	O
3D	O
version	O
of	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
CPU	B-General_Concept
.	O
</s>
<s>
The	O
3D	O
design	O
provides	O
15%	O
performance	O
improvement	O
(	O
due	O
to	O
eliminated	O
pipeline	O
stages	O
)	O
and	O
15%	O
power	O
saving	O
(	O
due	O
to	O
eliminated	O
repeaters	O
and	O
reduced	O
wiring	O
)	O
compared	O
to	O
the	O
2D	O
Pentium	B-General_Concept
4	I-General_Concept
.	O
</s>
<s>
The	O
Teraflops	B-General_Concept
Research	I-General_Concept
Chip	I-General_Concept
introduced	O
in	O
2007	O
by	O
Intel	O
is	O
an	O
experimental	O
80-core	O
design	O
with	O
stacked	O
memory	B-General_Concept
.	O
</s>
<s>
Due	O
to	O
the	O
high	O
demand	O
for	O
memory	B-General_Concept
bandwidth	B-Algorithm
,	O
a	O
traditional	O
I/O	O
approach	O
would	O
consume	O
10	O
to	O
25W	O
.	O
</s>
<s>
To	O
improve	O
upon	O
that	O
,	O
Intel	O
designers	O
implemented	O
a	O
TSV-based	O
memory	B-General_Concept
bus	O
.	O
</s>
<s>
Each	O
core	O
is	O
connected	O
to	O
one	O
memory	B-General_Concept
tile	O
in	O
the	O
SRAM	B-Architecture
die	O
with	O
a	O
link	O
that	O
provides	O
12GB/s	O
bandwidth	B-Algorithm
,	O
resulting	O
in	O
a	O
total	O
bandwidth	B-Algorithm
of	O
1TB/s	O
while	O
consuming	O
only	O
2.2W	O
.	O
</s>
<s>
In	O
ISSCC	O
2012	O
,	O
two	O
3D-IC-based	O
multi-core	O
designs	O
using	O
GlobalFoundries	O
 '	O
130nm	O
process	O
and	O
Tezzaron	O
's	O
FaStack	O
technology	O
were	O
presented	O
and	O
demonstrated	O
:	O
</s>
<s>
The	O
earliest	O
known	O
commercial	O
use	O
of	O
a	O
3DIC	B-Architecture
chip	O
was	O
in	O
Sony	B-Operating_System
's	I-Operating_System
PlayStation	I-Operating_System
Portable	I-Operating_System
(	O
PSP	B-Operating_System
)	O
handheld	B-Application
game	I-Application
console	I-Application
,	O
released	O
in	O
2004	O
.	O
</s>
<s>
The	O
PSP	B-Device
hardware	I-Device
includes	O
eDRAM	O
(	O
embedded	B-Architecture
DRAM	O
)	O
memory	B-General_Concept
manufactured	O
by	O
Toshiba	O
in	O
a	O
3D	O
system-in-package	B-Algorithm
chip	O
with	O
two	O
dies	O
stacked	O
vertically	O
.	O
</s>
<s>
Toshiba	O
called	O
it	O
"	O
semi-embedded	O
DRAM	O
"	O
at	O
the	O
time	O
,	O
before	O
later	O
calling	O
it	O
a	O
stacked	O
"	O
chip-on-chip	B-Algorithm
"	O
(	O
CoC	O
)	O
solution	O
.	O
</s>
<s>
In	O
April	O
2007	O
,	O
Toshiba	O
commercialized	O
an	O
eight-layer	O
3DIC	B-Architecture
,	O
the	O
16GB	O
THGAM	O
embedded	B-Architecture
NAND	O
flash	B-Device
memory	I-Device
chip	O
,	O
which	O
was	O
manufactured	O
with	O
eight	O
stacked	O
2GB	O
NAND	O
flash	B-Device
chips	I-Device
.	O
</s>
<s>
In	O
September	O
2007	O
,	O
Hynix	O
introduced	O
24-layer	O
3DIC	B-Architecture
technology	O
,	O
with	O
a	O
16GB	O
flash	B-Device
memory	I-Device
chip	O
that	O
was	O
manufactured	O
with	O
24	O
stacked	O
NAND	O
flash	B-Device
chips	I-Device
using	O
a	O
wafer	B-Algorithm
bonding	I-Algorithm
process	O
.	O
</s>
<s>
Toshiba	O
also	O
used	O
an	O
eight-layer	O
3DIC	B-Architecture
for	O
their	O
32GB	O
THGBM	O
flash	B-Device
chip	I-Device
in	O
2008	O
.	O
</s>
<s>
In	O
2010	O
,	O
Toshiba	O
used	O
a	O
16-layer	O
3DIC	B-Architecture
for	O
their	O
128GB	O
THGBM2	O
flash	B-Device
chip	I-Device
,	O
which	O
was	O
manufactured	O
with	O
16	O
stacked	O
8GB	O
chips	O
.	O
</s>
<s>
In	O
the	O
2010s	O
,	O
3DICs	B-Architecture
came	O
into	O
widespread	O
commercial	O
use	O
in	O
the	O
form	O
of	O
multi-chip	B-Algorithm
package	I-Algorithm
and	O
package	B-Algorithm
on	I-Algorithm
package	I-Algorithm
solutions	O
for	O
NAND	O
flash	B-Device
memory	I-Device
in	O
mobile	B-Application
devices	I-Application
.	O
</s>
<s>
Elpida	O
Memory	B-General_Concept
developed	O
the	O
first	O
8GB	O
DRAM	O
chip	O
(	O
stacked	O
with	O
four	O
DDR3	O
SDRAM	O
dies	O
)	O
in	O
September	O
2009	O
,	O
and	O
released	O
it	O
in	O
June	O
2011	O
.	O
</s>
<s>
TSMC	O
announced	O
plans	O
for	O
3DIC	B-Architecture
production	O
with	O
TSV	O
technology	O
in	O
January	O
2010	O
.	O
</s>
<s>
In	O
2011	O
,	O
SK	O
Hynix	O
introduced	O
16GB	O
DDR3	O
SDRAM	O
(	O
40nm	O
class	O
)	O
using	O
TSV	O
technology	O
,	O
Samsung	O
Electronics	O
introduced	O
3D-stacked	O
32GB	O
DDR3	O
(	O
30nm	O
class	O
)	O
based	O
on	O
TSV	O
in	O
September	O
,	O
and	O
then	O
Samsung	O
and	O
Micron	O
Technology	O
announced	O
TSV-based	O
Hybrid	B-General_Concept
Memory	I-General_Concept
Cube	I-General_Concept
(	O
HMC	O
)	O
technology	O
in	O
October	O
.	O
</s>
<s>
High	O
Bandwidth	B-Algorithm
Memory	B-General_Concept
(	O
HBM	O
)	O
,	O
developed	O
by	O
Samsung	O
,	O
AMD	O
,	O
and	O
SK	O
Hynix	O
,	O
uses	O
stacked	O
chips	O
and	O
TSVs	O
.	O
</s>
<s>
The	O
first	O
HBM	O
memory	B-Architecture
chip	I-Architecture
was	O
manufactured	O
by	O
SK	O
Hynix	O
in	O
2013	O
.	O
</s>
<s>
In	O
2017	O
,	O
Samsung	O
Electronics	O
combined	O
3DIC	B-Architecture
stacking	O
with	O
its	O
3DV-NAND	O
technology	O
(	O
based	O
on	O
charge	B-Algorithm
trap	I-Algorithm
flash	I-Algorithm
technology	O
)	O
,	O
manufacturing	O
its	O
512GB	O
KLUFG8R1EM	O
flash	B-Device
memory	I-Device
chip	O
with	O
eight	O
stacked	O
64-layer	O
V-NAND	O
chips	O
.	O
</s>
<s>
In	O
2019	O
,	O
Samsung	O
produced	O
a	O
1TB	O
flash	B-Device
chip	I-Device
with	O
16	O
stacked	O
V-NAND	O
dies	O
.	O
</s>
<s>
As	O
of	O
2018	O
,	O
Intel	O
is	O
considering	O
the	O
use	O
of	O
3DICs	B-Architecture
to	O
improve	O
performance	O
.	O
</s>
<s>
memory	B-General_Concept
device	I-General_Concept
,	O
chips	O
are	O
made	O
by	O
Micron	O
,	O
that	O
previously	O
in	O
April	O
2019	O
were	O
making	O
96-layer	O
chips	O
;	O
and	O
Toshiba	O
made	O
96-layer	O
devices	O
in	O
2018	O
.	O
</s>
