<s>
Tesla	B-Operating_System
is	O
the	O
codename	O
for	O
a	O
GPU	O
microarchitecture	B-General_Concept
developed	O
by	O
Nvidia	O
,	O
and	O
released	O
in	O
2006	O
,	O
as	O
the	O
successor	O
to	O
Curie	B-Operating_System
microarchitecture	B-General_Concept
.	O
</s>
<s>
It	O
was	O
named	O
after	O
the	O
pioneering	O
electrical	O
engineer	O
Nikola	O
Tesla	B-Operating_System
.	O
</s>
<s>
As	O
Nvidia	O
's	O
first	O
microarchitecture	B-General_Concept
to	O
implement	O
unified	O
shaders	O
,	O
it	O
was	O
used	O
with	O
GeForce	O
8	O
Series	O
,	O
GeForce	O
9	O
Series	O
,	O
GeForce	O
100	O
Series	O
,	O
GeForce	O
200	O
Series	O
,	O
and	O
GeForce	O
300	O
Series	O
of	O
GPUs	O
collectively	O
manufactured	O
in	O
90nm	O
,	O
80nm	O
,	O
65nm	O
,	O
55nm	O
,	O
and	O
40nm	O
.	O
</s>
<s>
It	O
was	O
also	O
in	O
the	O
GeForce	O
405	O
and	O
in	O
the	O
Quadro	B-Application
FX	I-Application
,	O
Quadro	B-Application
x000	O
,	O
Quadro	B-Application
NVS	O
series	O
,	O
and	O
Nvidia	B-Device
Tesla	I-Device
computing	O
modules	O
.	O
</s>
<s>
Tesla	B-Operating_System
replaced	O
the	O
old	O
fixed-pipeline	B-General_Concept
microarchitectures	B-General_Concept
,	O
represented	O
at	O
the	O
time	O
of	O
introduction	O
by	O
the	O
GeForce	O
7	O
series	O
.	O
</s>
<s>
It	O
competed	O
directly	O
with	O
AMD	O
's	O
first	O
unified	O
shader	O
microarchitecture	B-General_Concept
named	O
TeraScale	B-Architecture
,	O
a	O
development	O
of	O
ATI	O
's	O
work	O
on	O
the	B-Operating_System
Xbox	I-Operating_System
360	I-Operating_System
which	O
used	O
a	O
similar	O
design	O
.	O
</s>
<s>
Tesla	B-Operating_System
was	O
followed	O
by	O
Fermi	B-General_Concept
.	O
</s>
<s>
Tesla	B-Operating_System
is	O
Nvidia	O
's	O
first	O
microarchitecture	B-General_Concept
implementing	O
the	O
unified	O
shader	B-Language
model	I-Language
.	O
</s>
<s>
The	O
driver	O
supports	O
Direct3D	B-Application
10	I-Application
Shader	B-Language
Model	I-Language
4.0	I-Language
/	O
OpenGL	B-Application
2.1	O
(	O
later	O
drivers	O
have	O
OpenGL	B-Application
3.3	O
support	O
)	O
architecture	O
.	O
</s>
<s>
The	O
design	O
is	O
a	O
major	O
shift	O
for	O
NVIDIA	O
in	O
GPU	O
functionality	O
and	O
capability	O
,	O
the	O
most	O
obvious	O
change	O
being	O
the	O
move	O
from	O
the	O
separate	O
functional	O
units	O
(	O
pixel	O
shaders	O
,	O
vertex	O
shaders	O
)	O
within	O
previous	O
GPUs	O
to	O
a	O
homogeneous	O
collection	O
of	O
universal	O
floating	B-Algorithm
point	I-Algorithm
processors	O
(	O
called	O
"	O
stream	B-Application
processors	I-Application
"	O
)	O
that	O
can	O
perform	O
a	O
more	O
universal	O
set	O
of	O
tasks	O
.	O
</s>
<s>
GeForce	O
8	O
's	O
unified	O
shader	O
architecture	O
consists	O
of	O
a	O
number	O
of	O
stream	B-Application
processors	I-Application
(	O
SPs	O
)	O
.	O
</s>
<s>
Unlike	O
the	O
vector	B-Operating_System
processing	I-Operating_System
approach	O
taken	O
with	O
older	O
shader	O
units	O
,	O
each	O
SP	O
is	O
scalar	B-General_Concept
and	O
thus	O
can	O
operate	O
only	O
on	O
one	O
component	O
at	O
a	O
time	O
.	O
</s>
<s>
Scalar	B-General_Concept
shader	O
units	O
also	O
have	O
the	O
advantage	O
of	O
being	O
more	O
efficient	O
in	O
a	O
number	O
of	O
cases	O
as	O
compared	O
to	O
previous	O
generation	O
vector	B-Operating_System
shader	O
units	O
that	O
rely	O
on	O
ideal	O
instruction	O
mixture	O
and	O
ordering	O
to	O
reach	O
peak	O
throughput	O
.	O
</s>
<s>
The	O
lower	O
maximum	O
throughput	O
of	O
these	O
scalar	B-General_Concept
processors	I-General_Concept
is	O
compensated	O
for	O
by	O
efficiency	O
and	O
by	O
running	O
them	O
at	O
a	O
high	O
clock	O
speed	O
(	O
made	O
possible	O
by	O
their	O
simplicity	O
)	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
stream	B-Application
processors	I-Application
of	O
GeForce	O
8800	O
GTX	O
operate	O
at	O
a	O
1.35GHz	O
clock	O
rate	O
while	O
the	O
rest	O
of	O
the	O
chip	O
is	O
operating	O
at	O
575MHz	O
.	O
</s>
<s>
NVIDIA	O
has	O
also	O
introduced	O
new	O
polygon	O
edge	O
anti-aliasing	B-Algorithm
methods	O
,	O
including	O
the	O
ability	O
of	O
the	O
GPU	O
's	O
ROPs	B-General_Concept
to	O
perform	O
both	O
Multisample	B-Algorithm
anti-aliasing	I-Algorithm
(	O
MSAA	O
)	O
and	O
HDR	B-Device
lighting	I-Device
at	O
the	O
same	O
time	O
,	O
correcting	O
various	O
limitations	O
of	O
previous	O
generations	O
.	O
</s>
<s>
GeForce	O
8	O
supports	O
128-bit	O
HDR	B-Device
rendering	I-Device
,	O
an	O
increase	O
from	O
prior	O
cards	O
 '	O
64-bit	O
support	O
.	O
</s>
<s>
The	O
chip	O
's	O
new	O
anti-aliasing	B-Algorithm
technology	O
,	O
called	O
coverage	O
sampling	O
AA	O
(	O
CSAA	O
)	O
,	O
uses	O
Z	O
,	O
color	O
,	O
and	O
coverage	O
information	O
to	O
determine	O
final	O
pixel	O
color	O
.	O
</s>
<s>
The	O
claimed	O
theoretical	O
single-precision	O
processing	O
power	O
for	O
Tesla-based	O
cards	O
given	O
in	O
FLOPS	O
may	O
be	O
hard	O
to	O
reach	O
in	O
real-world	O
workloads	O
.	O
</s>
<s>
In	O
G80/G90/GT200	O
,	O
each	O
Streaming	O
Multiprocessor	O
(	O
SM	O
)	O
contains	O
8	O
Shader	O
Processors	O
(	O
SP	O
,	O
or	O
Unified	O
Shader	O
,	O
or	O
CUDA	B-Architecture
Core	O
)	O
and	O
2	O
Special	O
Function	O
Units	O
(	O
SFU	O
)	O
.	O
</s>
<s>
Each	O
SP	O
can	O
fulfill	O
up	O
to	O
two	O
single-precision	O
operations	O
per	O
clock	O
:	O
1	O
Multiply	O
and	O
1	O
Add	O
,	O
using	O
a	O
single	O
MAD	B-Algorithm
instruction	O
.	O
</s>
<s>
Therefore	O
,	O
to	O
calculate	O
the	O
theoretical	O
dual-issue	O
MAD+MUL	O
performance	O
in	O
floating	B-Algorithm
point	I-Algorithm
operations	O
per	O
second	O
[	O
FLOPSsp+sfu	O
,	O
GFLOPS ]	O
of	O
a	O
graphics	O
card	O
with	O
SP	O
count	O
 [ n ] 	O
and	O
shader	O
frequency	O
[	O
f	O
,	O
GHz ]	O
,	O
the	O
formula	O
is	O
:	O
FLOPSsp+sfu	O
=	O
3	O
×	O
n	O
×	O
f	O
.	O
</s>
<s>
However	O
leveraging	O
dual-issue	O
performance	O
like	O
MAD+MUL	O
is	O
problematic	O
:	O
</s>
<s>
Not	O
all	O
combinations	O
of	O
instructions	O
like	O
MAD+MUL	O
can	O
be	O
executed	O
in	O
parallel	O
on	O
the	O
SP	O
and	O
SFU	O
,	O
because	O
the	O
SFU	O
is	O
rather	O
specialized	O
as	O
it	O
can	O
only	O
handle	O
a	O
specific	O
subset	O
of	O
instructions	O
:	O
32-bit	O
floating	B-Algorithm
point	I-Algorithm
multiplication	O
,	O
transcendental	O
functions	O
,	O
interpolation	O
for	O
parameter	O
blending	O
,	O
reciprocal	O
,	O
reciprocal	O
square	O
root	O
,	O
sine	O
,	O
cosine	O
,	O
etc	O
.	O
</s>
<s>
For	O
these	O
reasons	O
,	O
in	O
order	O
to	O
estimate	O
the	O
performance	O
of	O
real-world	O
workloads	O
,	O
it	O
may	O
be	O
more	O
helpful	O
to	O
ignore	O
the	O
SFU	O
and	O
to	O
assume	O
only	O
1	O
MAD	B-Algorithm
(	O
2	O
operations	O
)	O
per	O
SP	O
per	O
cycle	O
.	O
</s>
<s>
In	O
this	O
case	O
the	O
formula	O
to	O
calculate	O
the	O
theoretical	O
performance	O
in	O
floating	B-Algorithm
point	I-Algorithm
operations	O
per	O
second	O
becomes	O
:	O
FLOPSsp	O
=	O
2	O
×	O
n	O
×	O
f	O
.	O
</s>
<s>
The	O
theoretical	O
double-precision	O
processing	O
power	O
of	O
a	O
Tesla	B-Operating_System
GPU	I-Operating_System
is	O
1/8	O
of	O
the	O
single	O
precision	O
performance	O
on	O
GT200	O
;	O
there	O
is	O
no	O
double	O
precision	O
support	O
on	O
G8x	O
and	O
G9x	O
.	O
</s>
