<s>
Intel	O
Teraflops	B-General_Concept
Research	I-General_Concept
Chip	I-General_Concept
(	O
codenamed	O
Polaris	B-General_Concept
)	O
is	O
a	O
research	O
manycore	B-General_Concept
processor	I-General_Concept
containing	O
80	O
cores	B-Architecture
,	O
using	O
a	O
network-on-chip	B-Architecture
architecture	O
,	O
developed	O
by	O
Intel	O
's	O
Tera-Scale	B-General_Concept
Computing	O
Research	O
Program	O
.	O
</s>
<s>
It	O
was	O
manufactured	O
using	O
a	O
65nm	O
CMOS	B-Device
process	O
with	O
eight	O
layers	O
of	O
copper	O
interconnect	O
and	O
contains	O
100	O
million	O
transistors	B-Application
on	O
a	O
275mm2	O
die	O
.	O
</s>
<s>
Its	O
design	O
goal	O
was	O
to	O
demonstrate	O
a	O
modular	O
architecture	O
capable	O
of	O
a	O
sustained	O
performance	O
of	O
1.0	O
TFLOPS	O
while	O
dissipating	O
less	O
than	O
100	O
W	O
.	O
Research	O
from	O
the	O
project	O
was	O
later	O
incorporated	O
into	O
Xeon	B-General_Concept
Phi	I-General_Concept
.	O
</s>
<s>
The	O
chip	O
consists	O
of	O
a	O
10x8	O
2D	O
mesh	B-Architecture
network	I-Architecture
of	O
cores	B-Architecture
and	O
nominally	O
operates	O
at	O
4GHz	O
.	O
</s>
<s>
Each	O
core	O
,	O
called	O
a	O
tile	O
(	O
3mm2	O
)	O
,	O
contains	O
a	O
processing	O
engine	O
and	O
a	O
5-port	O
wormhole-switched	B-Protocol
router	O
(	O
0.34mm2	O
)	O
with	O
mesochronous	B-Architecture
interfaces	O
,	O
with	O
a	O
bandwidth	O
of	O
80	O
GB/s	O
and	O
latency	O
of	O
1.25	O
ns	O
at	O
4GHz	O
.	O
</s>
<s>
The	O
processing	O
engine	O
in	O
each	O
tile	O
contains	O
two	O
independent	O
,	O
9-stage	O
pipeline	B-General_Concept
,	O
single-precision	O
floating-point	O
multiplyaccumulator	O
(	O
FPMAC	O
)	O
units	O
,	O
3	O
KB	O
of	O
single-cycle	O
instruction	O
memory	O
and	O
2	O
KB	O
of	O
data	O
memory	O
.	O
</s>
<s>
Each	O
FPMAC	O
unit	O
is	O
capable	O
of	O
performing	O
2	O
single-precision	O
floating-point	O
operations	O
per	O
cycle	B-General_Concept
.	O
</s>
<s>
A	O
96-bit	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
encodes	O
up	O
to	O
eight	O
operations	O
per	O
cycle	B-General_Concept
.	O
</s>
<s>
Underneath	O
each	O
tile	O
,	O
a	O
256	O
KB	O
SRAM	B-Architecture
module	O
(	O
codenamed	O
Freya	O
)	O
was	O
3D	B-Architecture
stacked	I-Architecture
,	O
thus	O
bringing	O
memory	O
nearer	O
to	O
the	O
processor	O
to	O
increase	O
overall	O
memory	O
bandwidth	O
to	O
1	O
TB/s	O
,	O
at	O
the	O
expense	O
of	O
higher	O
cost	O
,	O
thermal	O
stress	O
and	O
latency	O
,	O
and	O
a	O
small	O
total	O
capacity	O
of	O
20	O
MB	O
.	O
</s>
<s>
The	O
network	O
of	O
Polaris	B-General_Concept
was	O
shown	O
to	O
have	O
a	O
bisection	O
bandwidth	O
of	O
1.6	O
Tbit/s	O
at	O
3.16GHz	O
and	O
2.92	O
Tbit/s	O
at	O
5.67GHz	O
.	O
</s>
<s>
Other	O
prominent	O
features	O
of	O
the	O
Teraflops	B-General_Concept
Research	I-General_Concept
chip	I-General_Concept
include	O
its	O
fine-grained	O
power	O
management	O
with	O
21	O
independent	O
sleep	O
regions	O
on	O
a	O
tile	O
and	O
dynamic	O
tile	O
sleep	O
,	O
and	O
very	O
high	O
energy	O
efficiency	O
with	O
27	O
GFLOPS/W	O
theoretical	O
peak	O
at	O
0.6	O
V	O
and	O
19.4	O
GFLOPS/W	O
actual	O
for	O
stencil	B-Application
at	O
0.75	O
V	O
.	O
</s>
<s>
Intel	O
aimed	O
to	O
help	O
software	O
development	O
for	O
the	O
new	O
exotic	O
architecture	O
by	O
creating	O
a	O
new	O
programming	O
model	O
,	O
especially	O
for	O
the	O
chip	O
,	O
called	O
Ct	B-General_Concept
.	O
</s>
<s>
The	O
model	O
never	O
gained	O
the	O
following	O
Intel	O
hoped	O
for	O
and	O
has	O
been	O
eventually	O
incorporated	O
into	O
Intel	B-Application
Array	I-Application
Building	I-Application
Blocks	I-Application
,	O
a	O
now	O
defunct	O
C++	O
library	O
.	O
</s>
