<s>
Tejas	O
was	O
a	O
code	O
name	O
for	O
Intel	O
's	O
microprocessor	B-Architecture
,	O
which	O
was	O
to	O
be	O
a	O
successor	O
to	O
the	O
latest	O
Pentium	B-General_Concept
4	I-General_Concept
with	O
the	O
Prescott	O
core	O
and	O
was	O
sometimes	O
referred	O
to	O
as	O
Pentium	B-Device
V	I-Device
.	O
Jayhawk	O
was	O
a	O
code	O
name	O
for	O
its	O
Xeon	B-Device
counterpart	O
.	O
</s>
<s>
The	O
cancellation	O
of	O
the	O
processors	O
in	O
May	O
2004	O
underscored	O
Intel	O
's	O
historical	O
transition	O
of	O
its	O
focus	O
on	O
single-core	O
processors	O
to	O
multi-core	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
Tejas	O
went	O
even	O
further	O
ahead	O
with	O
this	O
paradigm	O
,	O
with	O
Intel	O
targeting	O
10GHz	O
clock	O
speeds	O
by	O
2011	O
back	O
in	O
July	O
2000	O
(	O
NetBurst	B-Device
was	O
launched	O
in	O
November	O
2000	O
)	O
.	O
</s>
<s>
This	O
cancellation	O
reflected	O
Intel	O
's	O
intention	O
to	O
focus	O
on	O
dual-core	B-Architecture
chips	I-Architecture
for	O
the	O
Itanium	B-General_Concept
platform	O
.	O
</s>
<s>
With	O
respect	O
to	O
desktop	B-Device
processors	O
,	O
Intel	O
's	O
development	O
efforts	O
shifted	O
to	O
the	O
Pentium	O
M	O
microarchitecture	O
(	O
itself	O
a	O
derivative	O
of	O
the	O
P6	B-Device
microarchitecture	I-Device
)	O
used	O
in	O
the	O
Centrino	B-Device
notebook	B-Device
platform	O
,	O
which	O
offered	O
greatly	O
improved	O
performance	O
per	O
watt	O
consumed	O
than	O
offered	O
by	O
Prescott	O
and	O
other	O
NetBurst	B-Device
designs	O
.	O
</s>
<s>
The	O
outcome	O
of	O
these	O
development	O
efforts	O
was	O
the	O
Intel	B-Device
Core	I-Device
processor	O
line	O
,	O
and	O
later	O
the	O
Intel	B-Device
Core	I-Device
2	I-Device
line	O
,	O
providing	O
and	O
building	O
on	O
the	O
benefits	O
of	O
Pentium	O
M	O
and	O
offering	O
Intel	O
's	O
first	O
native	O
dual	B-Architecture
core	I-Architecture
products	O
for	O
desktops	O
and	O
laptops	B-Device
.	O
</s>
<s>
This	O
defined	O
the	O
end	O
for	O
the	O
NetBurst	B-Device
architecture	O
,	O
with	O
Core	O
setting	O
the	O
foundation	O
and	O
path	O
for	O
power	O
efficient	O
architectures	O
that	O
followed	O
along	O
the	O
Tick	B-Device
–	I-Device
tock	I-Device
model	I-Device
.	O
</s>
<s>
Tejas	B-Device
and	I-Device
Jayhawk	I-Device
were	O
to	O
make	O
several	O
improvements	O
on	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
's	O
NetBurst	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
Tejas	O
was	O
originally	O
to	O
be	O
built	O
on	O
a	O
90	O
nm	O
process	O
,	O
later	O
moving	O
to	O
a	O
65	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
.	O
</s>
<s>
The	O
90nm	O
version	O
of	O
the	O
processor	O
was	O
reported	O
to	O
have	O
1	O
MB	O
L2	O
cache	B-General_Concept
,	O
while	O
the	O
65nm	B-Algorithm
chip	O
would	O
increase	O
the	O
cache	B-General_Concept
to	O
2	O
MB	O
.	O
</s>
<s>
There	O
was	O
also	O
to	O
be	O
a	O
dual	B-Architecture
core	I-Architecture
version	O
of	O
Tejas	O
called	O
Cedarmill	O
(	O
or	O
Cedar	O
Mill	O
depending	O
on	O
the	O
source	O
)	O
.	O
</s>
<s>
This	O
Cedarmill	O
should	O
not	O
be	O
confused	O
with	O
the	O
65nm	B-Algorithm
Cedar	O
Mill-based	O
Pentium	B-General_Concept
4	I-General_Concept
,	O
which	O
appears	O
to	O
be	O
what	O
the	O
codename	O
was	O
recycled	O
for	O
.	O
</s>
<s>
The	O
trace	B-General_Concept
cache	I-General_Concept
capacity	O
would	O
likely	O
have	O
been	O
increased	O
,	O
and	O
the	O
number	O
of	O
pipeline	O
stages	O
was	O
increased	O
to	O
between	O
40	O
and	O
50	O
stages	O
.	O
</s>
<s>
There	O
would	O
have	O
been	O
an	O
improved	O
version	O
of	O
Hyper-Threading	B-Operating_System
,	O
as	O
well	O
as	O
a	O
new	O
version	O
of	O
SSE	B-General_Concept
,	O
which	O
was	O
later	O
backported	O
to	O
the	O
Intel	B-Device
Core	I-Device
2	I-Device
series	O
after	O
Tejas	O
 '	O
cancellation	O
and	O
named	O
SSSE3	B-General_Concept
.	O
</s>
<s>
However	O
,	O
it	O
's	O
likely	O
that	O
Tejas	O
would	O
n't	O
have	O
had	O
linear	O
performance	O
scaling	O
,	O
as	O
it	O
would	O
on	O
average	O
have	O
executed	O
fewer	O
instructions	O
per	O
clock	O
cycle	O
due	O
to	O
more	O
pipeline	O
bubbles	O
from	O
branch	O
mispredicts	O
and	O
data	B-General_Concept
cache	I-General_Concept
misses	O
.	O
</s>
<s>
Also	O
,	O
it	O
would	O
have	O
run	O
hotter	O
as	O
well	O
with	O
a	O
TDP	B-General_Concept
much	O
higher	O
than	O
the	O
Prescott	O
core	O
of	O
Pentium	B-General_Concept
4	I-General_Concept
.	O
</s>
<s>
Initial	O
claims	O
reported	O
early	O
samples	O
of	O
single	O
core	O
90nm	O
Tejas	O
running	O
at	O
2.8GHz	O
and	O
rated	O
for	O
150	O
W	O
TDP	B-General_Concept
on	O
the	O
LGA	B-Device
775	I-Device
socket	O
,	O
a	O
notable	O
increase	O
over	O
single	O
core	O
90nm	O
Prescott	O
(	O
Pentium	B-General_Concept
4	I-General_Concept
521	O
,	O
2.8GHz	O
,	O
84	O
W	O
TDP	B-General_Concept
)	O
and	O
higher	O
than	O
90nm	O
dual	B-Architecture
core	I-Architecture
Smithfield	O
(	O
Pentium	O
D	O
820	O
,	O
2.8GHz	O
,	O
95	O
W	O
TDP	B-General_Concept
)	O
.	O
</s>
<s>
In	O
contrast	O
,	O
65nm	B-Algorithm
dual	B-Architecture
core	I-Architecture
Core	B-Device
2	I-Device
Duo	O
processors	O
based	O
on	O
the	O
Core	B-Device
microarchitecture	I-Device
had	O
a	O
maximum	O
of	O
65	O
W	O
TDP	B-General_Concept
(	O
E6850	O
,	O
3.00GHz	O
)	O
while	O
being	O
much	O
more	O
efficient	O
with	O
markedly	O
higher	O
performance	O
per	O
clock	O
.	O
</s>
