<s>
TRIPS	O
was	O
a	O
microprocessor	B-Architecture
architecture	O
designed	O
by	O
a	O
team	O
at	O
the	O
University	O
of	O
Texas	O
at	O
Austin	O
in	O
conjunction	O
with	O
IBM	O
,	O
Intel	O
,	O
and	O
Sun	O
Microsystems	O
.	O
</s>
<s>
TRIPS	O
uses	O
an	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
designed	O
to	O
be	O
easily	O
broken	O
down	O
into	O
large	O
groups	O
of	O
instructions	O
(	O
Graphs	O
)	O
that	O
can	O
be	O
run	O
on	O
independent	O
processing	O
elements	O
.	O
</s>
<s>
Computer	B-Application
programs	I-Application
consist	O
of	O
a	O
series	O
of	O
instructions	O
stored	O
in	O
memory	O
.	O
</s>
<s>
For	O
instance	O
,	O
an	O
instruction	O
that	O
adds	O
two	O
numbers	O
might	O
take	O
three	O
or	O
four	O
instruction	B-General_Concept
cycles	I-General_Concept
,	O
while	O
fetching	O
the	O
numbers	O
from	O
memory	O
might	O
take	O
one	O
or	O
two	O
cycles	O
.	O
</s>
<s>
In	O
these	O
machines	O
,	O
there	O
was	O
no	O
penalty	O
for	O
data	O
being	O
in	O
main	O
memory	O
,	O
and	O
the	O
instruction	B-General_Concept
set	I-General_Concept
architectures	I-General_Concept
were	O
generally	O
designed	O
to	O
allow	O
direct	O
access	O
,	O
for	O
instance	O
,	O
an	O
add	O
instruction	O
might	O
take	O
a	O
value	O
from	O
one	O
location	O
in	O
memory	O
,	O
add	O
it	O
to	O
the	O
value	O
from	O
another	O
,	O
and	O
then	O
store	O
the	O
result	O
in	O
a	O
third	O
location	O
.	O
</s>
<s>
The	O
introduction	O
of	O
increasingly	O
fast	O
microprocessors	B-Architecture
and	O
cheap-but-slower	O
dynamic	O
RAM	O
changed	O
this	O
equation	O
dramatically	O
.	O
</s>
<s>
One	O
of	O
the	O
key	O
advances	O
in	O
the	O
RISC	B-Architecture
concept	O
was	O
to	O
include	O
more	O
processor	B-General_Concept
registers	I-General_Concept
than	O
earlier	O
designs	O
,	O
typically	O
several	O
dozen	O
rather	O
than	O
two	O
or	O
three	O
.	O
</s>
<s>
This	O
technique	O
quickly	O
reached	O
its	O
limits	O
,	O
and	O
since	O
the	O
1990s	O
modern	O
CPUs	O
have	O
added	O
increasing	O
amounts	O
of	O
CPU	B-General_Concept
cache	I-General_Concept
to	O
increase	O
local	O
storage	O
,	O
although	O
cache	O
is	O
slower	O
than	O
registers	O
.	O
</s>
<s>
One	O
attempt	O
to	O
break	O
out	O
of	O
this	O
limit	O
is	O
the	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
concept	O
.	O
</s>
<s>
VLIW	B-General_Concept
hands	O
the	O
task	O
of	O
looking	O
for	O
instruction	O
parallelism	O
to	O
the	O
compiler	B-Language
,	O
removing	O
it	O
from	O
the	O
processor	O
itself	O
.	O
</s>
<s>
However	O
,	O
this	O
has	O
proven	O
difficult	O
in	O
practice	O
,	O
and	O
VLIW	B-General_Concept
processors	O
have	O
not	O
become	O
widely	O
popular	O
.	O
</s>
<s>
Even	O
in	O
the	O
case	O
of	O
VLIW	B-General_Concept
,	O
another	O
problem	O
has	O
grown	O
to	O
become	O
an	O
issue	O
.	O
</s>
<s>
TRIPS	O
is	O
a	O
processor	O
based	O
on	O
the	O
Explicit	B-Architecture
Data	I-Architecture
Graph	I-Architecture
Execution	I-Architecture
(	O
EDGE	O
)	O
concept	O
.	O
</s>
<s>
The	O
compilers	B-Language
examine	O
the	O
code	O
and	O
find	O
blocks	O
of	O
code	O
that	O
share	O
information	O
in	O
a	O
specific	O
way	O
.	O
</s>
<s>
These	O
are	O
then	O
assembled	O
into	O
compiled	B-Language
"	O
hyperblocks	O
"	O
and	O
fed	O
into	O
the	O
CPU	O
.	O
</s>
<s>
Since	O
the	O
compiler	B-Language
is	O
guaranteeing	O
that	O
these	O
blocks	O
have	O
specific	O
interdependencies	O
between	O
them	O
,	O
the	O
processor	O
can	O
isolate	O
the	O
code	O
in	O
a	O
single	O
functional	O
unit	O
with	O
its	O
own	O
local	O
memory	O
.	O
</s>
<s>
In	O
an	O
EDGE	O
processor	O
,	O
the	O
interdependencies	O
between	O
the	O
data	O
in	O
the	O
code	O
would	O
be	O
noticed	O
by	O
the	O
compiler	B-Language
,	O
which	O
would	O
compile	B-Language
these	O
instructions	O
into	O
a	O
single	O
block	O
.	O
</s>
<s>
Code	O
that	O
did	O
not	O
rely	O
on	O
this	O
intermediate	O
data	O
would	O
be	O
compiled	B-Language
into	O
separate	O
hyperblocks	O
.	O
</s>
<s>
Of	O
course	O
its	O
possible	O
that	O
an	O
entire	O
program	O
would	O
use	O
the	O
same	O
data	O
,	O
so	O
the	O
compilers	B-Language
also	O
look	O
for	O
instances	O
where	O
data	O
is	O
handed	O
off	O
to	O
other	O
code	O
and	O
then	O
effectively	O
abandoned	O
by	O
the	O
original	O
block	O
,	O
which	O
is	O
a	O
common	O
access	O
pattern	O
.	O
</s>
<s>
In	O
this	O
case	O
the	O
compiler	B-Language
will	O
still	O
produce	O
two	O
separate	O
hyperblocks	O
,	O
but	O
explicitly	O
encode	O
the	O
handoff	O
of	O
the	O
data	O
rather	O
than	O
simply	O
leaving	O
it	O
stored	O
in	O
some	O
shared	O
memory	O
location	O
.	O
</s>
<s>
Blocks	O
that	O
have	O
considerable	O
interdependencies	O
are	O
re-arranged	O
by	O
the	O
compiler	B-Language
to	O
spread	O
out	O
the	O
communications	O
in	O
order	O
to	O
avoid	O
bottlenecking	O
the	O
transport	O
.	O
</s>
<s>
EDGE	O
processors	O
are	O
limited	O
in	O
parallelism	O
by	O
the	O
capabilities	O
of	O
the	O
compiler	B-Language
,	O
not	O
the	O
on-chip	O
systems	O
.	O
</s>
<s>
The	O
TRIPS	O
design	O
's	O
use	O
of	O
hyperblocks	O
that	O
are	O
loaded	O
en-masse	O
allows	O
for	O
dramatic	O
gains	O
in	O
speculative	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
TRIPS	O
is	O
so	O
flexible	O
in	O
this	O
regard	O
that	O
the	O
developers	O
have	O
suggested	O
it	O
would	O
even	O
replace	O
some	O
custom	O
high-speed	O
designs	O
like	O
DSPs	B-Architecture
.	O
</s>
<s>
Like	O
TRIPS	O
,	O
DSPs	B-Architecture
gain	O
additional	O
performance	O
by	O
limiting	O
data	O
inter-dependencies	O
,	O
but	O
unlike	O
TRIPS	O
they	O
do	O
so	O
by	O
allowing	O
only	O
a	O
very	O
limited	O
workflow	O
to	O
run	O
on	O
them	O
.	O
</s>
<s>
As	O
the	O
designers	O
have	O
noted	O
,	O
it	O
is	O
unlikely	O
a	O
TRIPS	O
processor	O
could	O
be	O
used	O
to	O
replace	O
highly	O
customized	O
designs	O
like	O
GPUs	B-Architecture
in	O
modern	O
graphics	B-Device
cards	I-Device
,	O
but	O
they	O
may	O
be	O
able	O
to	O
replace	O
or	O
outperform	O
many	O
lower-performance	O
chips	O
like	O
those	O
used	O
for	O
media	O
processing	O
.	O
</s>
<s>
However	O
,	O
as	O
of	O
2008	O
,	O
GPUs	B-Architecture
from	O
ATI	O
and	O
NVIDIA	O
have	O
already	O
exceeded	O
the	O
1	O
teraflop	O
barrier	O
(	O
albeit	O
for	O
specialized	O
applications	O
)	O
.	O
</s>
<s>
As	O
for	O
traditional	O
CPUs	O
,	O
a	O
contemporary	O
(	O
2007	O
)	O
Mac	B-Device
Pro	I-Device
using	O
a	O
2-core	O
Intel	B-Device
Xeon	I-Device
can	O
only	O
perform	O
about	O
5	O
GFLOPs	O
on	O
single	O
applications	O
.	O
</s>
<s>
In	O
the	O
current	O
implementation	O
,	O
the	O
compiler	B-Language
constructs	O
"	O
hyperblocks	O
"	O
of	O
128	O
instructions	O
each	O
,	O
and	O
allows	O
the	O
system	O
to	O
keep	O
eight	O
blocks	O
"	O
in	O
flight	O
"	O
at	O
the	O
same	O
time	O
,	O
for	O
a	O
total	O
of	O
1,024	O
instructions	O
per	O
core	O
.	O
</s>
