<s>
The	O
Advanced	B-Device
Scientific	I-Device
Computer	I-Device
(	O
ASC	O
)	O
is	O
a	O
supercomputer	B-Architecture
designed	O
and	O
manufactured	O
by	O
Texas	O
Instruments	O
(	O
TI	O
)	O
between	O
1966	O
and	O
1973	O
.	O
</s>
<s>
The	O
ASC	O
's	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
supported	O
vector	B-Operating_System
processing	I-Operating_System
,	O
a	O
performance-enhancing	O
technique	O
which	O
was	O
key	O
to	O
its	O
high-performance	O
.	O
</s>
<s>
The	O
ASC	O
,	O
along	O
with	O
the	O
Control	O
Data	O
Corporation	O
STAR-100	B-Device
supercomputer	B-Architecture
(	O
which	O
was	O
introduced	O
in	O
the	O
same	O
year	O
)	O
,	O
were	O
the	O
first	O
computers	O
to	O
feature	O
vector	B-Operating_System
processing	I-Operating_System
.	O
</s>
<s>
However	O
,	O
this	O
technique	O
's	O
potential	O
was	O
not	O
fully	O
realized	O
by	O
either	O
the	O
ASC	O
or	O
STAR-100	B-Device
due	O
to	O
an	O
insufficient	O
understanding	O
of	O
the	O
technique	O
;	O
it	O
was	O
the	O
Cray	O
Research	O
Cray-1	B-Device
supercomputer	B-Architecture
,	O
announced	O
in	O
1975	O
that	O
would	O
fully	O
realize	O
and	O
popularize	O
vector	B-Operating_System
processing	I-Operating_System
.	O
</s>
<s>
The	O
more	O
successful	O
implementation	O
of	O
vector	B-Operating_System
processing	I-Operating_System
in	O
the	O
Cray-1	B-Device
would	O
demarcate	O
the	O
ASC	O
(	O
and	O
STAR-100	B-Device
)	O
as	O
first-generation	O
vector	B-Operating_System
processors	I-Operating_System
,	O
with	O
the	O
Cray-1	B-Device
belonging	O
in	O
the	O
second	O
.	O
</s>
<s>
Originally	O
the	O
software	O
,	O
including	O
an	O
operating	B-General_Concept
system	I-General_Concept
and	O
a	O
FORTRAN	B-Application
compiler	O
,	O
were	O
done	O
under	O
contract	O
by	O
Computer	O
Usage	O
Company	O
,	O
under	O
direction	O
of	O
George	O
R	O
.	O
Trimble	O
,	O
Jr.	O
</s>
<s>
The	O
ASC	O
was	O
based	O
around	O
a	O
single	O
high-speed	O
shared	O
memory	O
,	O
which	O
was	O
accessed	O
by	O
the	O
CPU	O
and	O
eight	O
I/O	B-Device
channel	I-Device
controllers	O
,	O
in	O
an	O
organization	O
similar	O
to	O
Seymour	O
Cray	O
's	O
groundbreaking	O
CDC	B-Device
6600	I-Device
.	O
</s>
<s>
The	O
MCU	O
also	O
acted	O
as	O
a	O
cache	B-General_Concept
controller	O
,	O
offering	O
high-speed	O
access	O
to	O
a	O
semiconductor-based	O
memory	O
for	O
the	O
eight	O
processor	O
ports	O
,	O
and	O
handling	O
all	O
communications	O
to	O
the	O
24-bit	O
address	O
space	O
in	O
main	O
memory	O
.	O
</s>
<s>
For	O
instance	O
,	O
main	O
memory	O
could	O
be	O
constructed	O
out	O
of	O
slower	O
but	O
less	O
expensive	O
core	B-General_Concept
memory	I-General_Concept
,	O
although	O
this	O
was	O
not	O
used	O
in	O
practice	O
.	O
</s>
<s>
The	O
CPU	O
had	O
a	O
60ns	O
clock	O
cycle	O
(	O
16.67MHz	O
clock	O
frequency	O
)	O
and	O
its	O
logic	O
was	O
built	O
from	O
20-gate	O
emitter-coupled	B-General_Concept
logic	I-General_Concept
integrated	O
circuits	O
originally	O
developed	O
by	O
TI	O
for	O
the	O
ILLIAC	B-Device
IV	I-Device
supercomputer	B-Architecture
.	O
</s>
<s>
The	O
CPU	O
had	O
an	O
extremely	O
advanced	O
architecture	O
and	O
organization	O
for	O
its	O
era	O
,	O
supporting	O
microcoded	B-Device
arithmetic	O
and	O
mathematical	O
instructions	O
that	O
operated	O
on	O
scalars	O
,	O
vectors	O
,	O
or	O
matrices	O
.	O
</s>
<s>
The	O
vector	B-Operating_System
processing	I-Operating_System
facilities	O
had	O
a	O
memory-to-memory	O
architecture	O
;	O
where	O
the	O
vector	O
operands	O
were	O
read	O
from	O
,	O
and	O
the	O
resulting	O
vector	O
written	O
to	O
,	O
memory	O
.	O
</s>
<s>
Most	O
vector	B-Operating_System
processors	I-Operating_System
tended	O
to	O
be	O
memory	O
bandwidth-limited	O
,	O
that	O
is	O
,	O
they	O
could	O
process	O
data	O
faster	O
than	O
they	O
could	O
get	O
it	O
from	O
memory	O
.	O
</s>
<s>
The	O
"	O
Peripheral	O
Processor	O
"	O
was	O
a	O
separate	O
system	O
dedicated	O
entirely	O
to	O
quickly	O
running	O
the	O
operating	B-General_Concept
system	I-General_Concept
and	O
programs	O
running	O
within	O
it	O
,	O
as	O
well	O
as	O
feeding	O
data	O
to	O
the	O
CPU	O
.	O
</s>
<s>
Each	O
VP	O
had	O
its	O
own	O
program	B-General_Concept
counter	I-General_Concept
and	O
registers	O
,	O
and	O
the	O
system	O
could	O
thus	O
run	O
eight	O
programs	O
at	O
the	O
same	O
time	O
,	O
limited	O
only	O
by	O
memory	O
accesses	O
.	O
</s>
<s>
The	O
CRs	O
stored	O
the	O
state	O
required	O
for	O
communication	O
between	O
the	O
various	O
parts	O
of	O
the	O
ASC	O
:	O
the	O
CPU	O
,	O
VPs	O
,	O
and	O
channel	B-Device
controllers	I-Device
.	O
</s>
<s>
When	O
ASC	O
machines	O
first	O
became	O
available	O
in	O
the	O
early	O
1970s	O
,	O
they	O
outperformed	O
almost	O
all	O
other	O
machines	O
,	O
including	O
the	O
CDC	B-Device
STAR-100	I-Device
,	O
and	O
under	O
certain	O
conditions	O
matched	O
that	O
of	O
the	O
one-off	O
ILLIAC	B-Device
IV	I-Device
.	O
</s>
<s>
However	O
,	O
only	O
seven	O
had	O
been	O
installed	O
when	O
the	O
Cray-1	B-Device
was	O
announced	O
in	O
1975	O
.	O
</s>
<s>
The	O
Cray-1	B-Device
dedicated	O
almost	O
all	O
of	O
its	O
design	O
to	O
sustained	O
high-speed	O
access	O
to	O
memory	O
,	O
including	O
over	O
one	O
million	O
64-bit	O
words	O
of	O
semiconductor	O
memory	O
and	O
a	O
cycle	O
time	O
that	O
was	O
one-fifth	O
that	O
of	O
the	O
ASC	O
(	O
12.5ns	O
)	O
.	O
</s>
<s>
Although	O
the	O
ASC	O
was	O
in	O
some	O
ways	O
a	O
more	O
expandable	O
design	O
,	O
in	O
the	O
supercomputer	B-Architecture
market	O
speed	O
is	O
preferred	O
,	O
and	O
the	O
Cray-1	B-Device
was	O
much	O
faster	O
.	O
</s>
