<s>
TILEPro64	B-General_Concept
is	O
a	O
VLIW	B-General_Concept
ISA	B-General_Concept
multicore	B-Architecture
processor	I-Architecture
(	O
Tile	B-General_Concept
processor	I-General_Concept
)	O
manufactured	O
by	O
Tilera	B-Architecture
.	O
</s>
<s>
It	O
consists	O
of	O
a	O
cache-coherent	O
mesh	B-Architecture
network	I-Architecture
of	O
64	O
"	O
tiles	O
"	O
,	O
where	O
each	O
tile	O
houses	O
a	O
general	O
purpose	O
processor	B-Architecture
,	O
cache	B-General_Concept
,	O
and	O
a	O
non-blocking	O
router	B-Protocol
,	O
which	O
the	O
tile	O
uses	O
to	O
communicate	O
with	O
the	O
other	O
tiles	O
on	O
the	O
processor	B-Architecture
.	O
</s>
<s>
The	O
short-pipeline	O
,	O
in-order	O
,	O
three-issue	O
cores	O
implement	O
a	O
VLIW	B-General_Concept
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Each	O
core	O
has	O
a	O
register	B-General_Concept
file	O
and	O
three	O
functional	O
units	O
:	O
two	O
integer	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
and	O
a	O
load-store	O
unit	O
.	O
</s>
<s>
Each	O
of	O
the	O
cores	O
(	O
"	O
tile	O
"	O
)	O
has	O
its	O
own	O
L1	O
and	O
L2	O
caches	O
plus	O
an	O
overall	O
virtual	O
L3	O
cache	B-General_Concept
which	O
is	O
an	O
aggregate	O
of	O
all	O
the	O
L2	O
caches	O
.	O
</s>
<s>
TILEPro64	B-General_Concept
has	O
four	O
DDR2	O
controllers	O
at	O
up	O
to	O
800MT/s	O
,	O
two	O
10-gigabit	O
Ethernet	O
XAUI	B-Protocol
interfaces	O
,	O
two	O
four-lane	O
PCIe	O
interfaces	O
,	O
and	O
a	O
"	O
flexible	O
"	O
input/output	O
interface	O
,	O
which	O
can	O
be	O
software-configured	O
to	O
handle	O
a	O
number	O
of	O
protocols	O
.	O
</s>
<s>
The	O
processor	B-Architecture
is	O
fabricated	O
using	O
a	O
90nm	O
process	O
and	O
runs	O
at	O
speeds	O
of	O
600	O
to	O
866MHz	O
.	O
</s>
<s>
According	O
to	O
the	O
company	O
,	O
Tilera	B-Architecture
targets	O
the	O
chip	O
at	O
networking	O
equipment	O
,	O
digital	O
video	O
,	O
and	O
wireless	O
infrastructure	O
markets	O
where	O
the	O
demands	O
for	O
computing	O
processing	O
are	O
high	O
.	O
</s>
<s>
More	O
recently	O
,	O
Tilera	B-Architecture
has	O
positioned	O
this	O
processor	B-Architecture
in	O
the	O
cloud	O
computing	O
space	O
with	O
an	O
8-processor	O
(	O
512-core	O
)	O
2U	O
server	O
built	O
by	O
Quanta	O
Computer	O
.	O
</s>
<s>
TILEPro	O
was	O
supported	O
by	O
the	O
Linux	B-Operating_System
kernel	I-Operating_System
from	O
version	O
2.6.36	O
to	O
version	O
4.16	O
.	O
</s>
<s>
The	O
TILEPro	O
family	O
incorporates	O
a	O
number	O
of	O
enhancements	O
over	O
Tilera	B-Architecture
's	O
first	O
generation	O
TILE64	B-General_Concept
family	O
:	O
</s>
<s>
The	O
networking	O
software	O
company	O
6WIND	O
provides	O
high-performance	O
packet	O
processing	O
software	O
for	O
the	O
TILEPro64	B-General_Concept
platform	O
.	O
</s>
