<s>
Thyristor	B-Device
RAM	I-Device
(	O
T-RAM	B-Device
)	O
is	O
a	O
type	O
of	O
random-access	B-Architecture
memory	I-Architecture
dating	O
from	O
2009	O
invented	O
and	O
developed	O
by	O
T-RAM	B-Device
Semiconductor	O
,	O
which	O
departs	O
from	O
the	O
usual	O
designs	O
of	O
memory	B-Algorithm
cells	I-Algorithm
,	O
combining	O
the	O
strengths	O
of	O
the	O
DRAM	O
and	O
SRAM	B-Architecture
:	O
high	O
density	O
and	O
high	O
speed	O
.	O
</s>
<s>
This	O
technology	O
,	O
which	O
exploits	O
the	O
electrical	O
property	O
known	O
as	O
negative	O
differential	O
resistance	O
and	O
is	O
called	O
thin	O
capacitively-coupled	O
thyristor	O
,	O
is	O
used	O
to	O
create	O
memory	B-Algorithm
cells	I-Algorithm
capable	O
of	O
very	O
high	O
packing	O
densities	O
.	O
</s>
<s>
Due	O
to	O
this	O
,	O
the	O
memory	O
is	O
highly	O
scalable	O
,	O
and	O
already	O
has	O
a	O
storage	O
density	O
that	O
is	O
several	O
times	O
higher	O
than	O
found	O
in	O
conventional	O
6T	O
SRAM	B-Architecture
.	O
</s>
<s>
It	O
was	O
expected	O
that	O
the	O
next	O
generation	O
of	O
T-RAM	B-Device
memory	O
will	O
have	O
the	O
same	O
density	O
as	O
DRAM	O
.	O
</s>
<s>
This	O
technology	O
exploits	O
the	O
electrical	O
property	O
known	O
as	O
negative	O
differential	O
resistor	O
and	O
is	O
characterized	O
by	O
the	O
way	O
in	O
which	O
its	O
memory	B-Algorithm
cells	I-Algorithm
are	O
built	O
,	O
combining	O
DRAM	O
efficiency	O
in	O
terms	O
of	O
space	O
with	O
that	O
of	O
SRAM	B-Architecture
in	O
terms	O
of	O
speed	O
.	O
</s>
<s>
Very	O
similar	O
to	O
the	O
current	O
6T-SRAM	O
,	O
or	O
SRAM	B-Architecture
memories	O
with	O
6	O
cell	O
transistors	O
,	O
is	O
substantially	O
different	O
because	O
the	O
SRAM	B-Architecture
latch	O
CMOS	O
,	O
consisting	O
of	O
4	O
of	O
the	O
6	O
transistors	O
of	O
each	O
cell	O
,	O
is	O
replaced	O
by	O
a	O
bipolar	O
latch	O
PNP	O
-NPN	O
of	O
a	O
single	O
Thyristor	O
.	O
</s>
<s>
The	O
result	O
is	O
to	O
significantly	O
reduce	O
the	O
area	O
occupied	O
by	O
each	O
cell	O
,	O
thus	O
obtaining	O
a	O
highly	O
scalable	O
memory	O
that	O
has	O
already	O
reached	O
storage	O
density	O
several	O
times	O
higher	O
than	O
the	O
current	O
SRAM	B-Architecture
.	O
</s>
<s>
The	O
Thyristor-RAM	O
provides	O
the	O
best	O
density	O
/	O
performance	O
ratio	O
available	O
between	O
the	O
various	O
integrated	O
memories	O
,	O
matching	O
the	O
performance	O
of	O
an	O
SRAM	B-Architecture
memory	O
,	O
but	O
allowing	O
2-3	O
times	O
greater	O
storage	O
density	O
and	O
lower	O
power	O
consumption	O
.	O
</s>
<s>
It	O
is	O
expected	O
that	O
the	O
new	O
generation	O
of	O
T-RAM	B-Device
memory	O
will	O
have	O
the	O
same	O
storage	O
density	O
as	O
DRAMs	O
.	O
</s>
