<s>
In	O
parallel	B-Operating_System
computer	I-Operating_System
architectures	O
,	O
a	O
systolic	B-Architecture
array	I-Architecture
is	O
a	O
homogeneous	O
network	O
of	O
tightly	O
coupled	O
data	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
(	O
DPUs	O
)	O
called	O
cells	O
or	O
nodes	O
.	O
</s>
<s>
Each	O
node	B-Data_Structure
or	O
DPU	B-General_Concept
independently	O
computes	O
a	O
partial	O
result	O
as	O
a	O
function	O
of	O
the	O
data	O
received	O
from	O
its	O
upstream	O
neighbours	O
,	O
stores	O
the	O
result	O
within	O
itself	O
and	O
passes	O
it	O
downstream	O
.	O
</s>
<s>
Systolic	B-Architecture
arrays	I-Architecture
were	O
first	O
used	O
in	O
Colossus	B-Device
,	O
which	O
was	O
an	O
early	O
computer	O
used	O
to	O
break	O
German	O
Lorenz	O
ciphers	O
during	O
World	O
War	O
II	O
.	O
</s>
<s>
Due	O
to	O
the	O
classified	O
nature	O
of	O
Colossus	B-Device
,	O
they	O
were	O
independently	O
invented	O
or	O
rediscovered	O
by	O
H	O
.	O
T	O
.	O
Kung	O
and	O
Charles	O
Leiserson	O
who	O
described	O
arrays	O
for	O
many	O
dense	O
linear	O
algebra	O
computations	O
(	O
matrix	B-Architecture
product	O
,	O
solving	O
systems	O
of	O
linear	O
equations	O
,	O
LU	O
decomposition	O
,	O
etc	O
.	O
)	O
</s>
<s>
They	O
are	O
sometimes	O
classified	O
as	O
multiple-instruction	B-Operating_System
single-data	I-Operating_System
(	O
MISD	B-Operating_System
)	O
architectures	O
under	O
Flynn	B-Operating_System
's	I-Operating_System
taxonomy	I-Operating_System
,	O
but	O
this	O
classification	O
is	O
questionable	O
because	O
a	O
strong	O
argument	O
can	O
be	O
made	O
to	O
distinguish	O
systolic	B-Architecture
arrays	I-Architecture
from	O
any	O
of	O
Flynn	O
's	O
four	O
categories	O
:	O
SISD	B-Operating_System
,	O
SIMD	B-Device
,	O
MISD	B-Operating_System
,	O
MIMD	B-Operating_System
,	O
as	O
discussed	O
later	O
in	O
this	O
article	O
.	O
</s>
<s>
The	O
parallel	B-Operating_System
input	B-General_Concept
data	O
flows	O
through	O
a	O
network	O
of	O
hard-wired	O
processor	B-Architecture
nodes	O
,	O
which	O
combine	O
,	O
process	O
,	O
merge	B-Algorithm
or	O
sort	B-Algorithm
the	O
input	B-General_Concept
data	O
into	O
a	O
derived	O
result	O
.	O
</s>
<s>
Because	O
the	O
wave-like	O
propagation	O
of	O
data	O
through	O
a	O
systolic	B-Architecture
array	I-Architecture
resembles	O
the	O
pulse	O
of	O
the	O
human	O
circulatory	O
system	O
,	O
the	O
name	O
systolic	O
was	O
coined	O
from	O
medical	O
terminology	O
.	O
</s>
<s>
Systolic	B-Architecture
arrays	I-Architecture
are	O
often	O
hard-wired	O
for	O
specific	O
operations	O
,	O
such	O
as	O
"	O
multiply	O
and	O
accumulate	O
"	O
,	O
to	O
perform	O
massively	O
parallel	B-Operating_System
integration	O
,	O
convolution	B-Language
,	O
correlation	O
,	O
matrix	B-Architecture
multiplication	O
or	O
data	O
sorting	B-Algorithm
tasks	O
.	O
</s>
<s>
They	O
are	O
also	O
used	O
for	O
dynamic	B-Algorithm
programming	I-Algorithm
algorithms	O
,	O
used	O
in	O
DNA	O
and	O
protein	O
sequence	O
analysis	O
.	O
</s>
<s>
A	O
systolic	B-Architecture
array	I-Architecture
typically	O
consists	O
of	O
a	O
large	O
monolithic	B-Architecture
network	O
of	O
primitive	O
computing	O
nodes	O
which	O
can	O
be	O
hardwired	O
or	O
software	O
configured	O
for	O
a	O
specific	O
application	O
.	O
</s>
<s>
The	O
more	O
general	O
wave	O
front	O
processors	O
,	O
by	O
contrast	O
,	O
employ	O
sophisticated	O
and	O
individually	O
programmable	O
nodes	O
which	O
may	O
or	O
may	O
not	O
be	O
monolithic	B-Architecture
,	O
depending	O
on	O
the	O
array	B-Data_Structure
size	O
and	O
design	O
parameters	O
.	O
</s>
<s>
The	O
other	O
distinction	O
is	O
that	O
systolic	B-Architecture
arrays	I-Architecture
rely	O
on	O
synchronous	O
data	O
transfers	O
,	O
while	O
wavefront	O
tend	O
to	O
work	O
asynchronously	O
.	O
</s>
<s>
Unlike	O
the	O
more	O
common	O
Von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
,	O
where	O
program	O
execution	O
follows	O
a	O
script	O
of	O
instructions	O
stored	O
in	O
common	O
memory	O
,	O
addressed	B-General_Concept
and	O
sequenced	O
under	O
the	O
control	O
of	O
the	O
CPU	B-Device
's	O
program	B-General_Concept
counter	I-General_Concept
(	O
PC	O
)	O
,	O
the	O
individual	O
nodes	O
within	O
a	O
systolic	B-Architecture
array	I-Architecture
are	O
triggered	O
by	O
the	O
arrival	O
of	O
new	O
data	O
and	O
always	O
process	O
the	O
data	O
in	O
exactly	O
the	O
same	O
way	O
.	O
</s>
<s>
The	O
actual	O
processing	O
within	O
each	O
node	B-Data_Structure
may	O
be	O
hard	O
wired	O
or	O
block	O
micro	O
coded	O
,	O
in	O
which	O
case	O
the	O
common	O
node	B-Data_Structure
personality	O
can	O
be	O
block	O
programmable	O
.	O
</s>
<s>
The	O
systolic	B-Architecture
array	I-Architecture
paradigm	O
with	O
data-streams	O
driven	O
by	O
data	O
counters	O
,	O
is	O
the	O
counterpart	O
of	O
the	O
Von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
with	O
instruction-stream	O
driven	O
by	O
a	O
program	B-General_Concept
counter	I-General_Concept
.	O
</s>
<s>
Because	O
a	O
systolic	B-Architecture
array	I-Architecture
usually	O
sends	O
and	O
receives	O
multiple	O
data	O
streams	O
,	O
and	O
multiple	O
data	O
counters	O
are	O
needed	O
to	O
generate	O
these	O
data	O
streams	O
,	O
it	O
supports	O
data	B-Operating_System
parallelism	I-Operating_System
.	O
</s>
<s>
A	O
major	O
benefit	O
of	O
systolic	B-Architecture
arrays	I-Architecture
is	O
that	O
all	O
operand	O
data	O
and	O
partial	O
results	O
are	O
stored	O
within	O
(	O
passing	O
through	O
)	O
the	O
processor	B-Architecture
array	B-Data_Structure
.	O
</s>
<s>
There	O
is	O
no	O
need	O
to	O
access	O
external	O
buses	O
,	O
main	O
memory	O
or	O
internal	O
caches	O
during	O
each	O
operation	O
as	O
is	O
the	O
case	O
with	O
Von	O
Neumann	O
or	O
Harvard	B-Architecture
sequential	O
machines	O
.	O
</s>
<s>
The	O
sequential	O
limits	O
on	O
parallel	B-Operating_System
performance	O
dictated	O
by	O
Amdahl	B-Operating_System
's	I-Operating_System
Law	I-Operating_System
also	O
do	O
not	O
apply	O
in	O
the	O
same	O
way	O
,	O
because	O
data	O
dependencies	O
are	O
implicitly	O
handled	O
by	O
the	O
programmable	O
node	B-Data_Structure
interconnect	O
and	O
there	O
are	O
no	O
sequential	O
steps	O
in	O
managing	O
the	O
highly	O
parallel	B-Operating_System
data	O
flow	O
.	O
</s>
<s>
Systolic	B-Architecture
arrays	I-Architecture
are	O
therefore	O
extremely	O
good	O
at	O
artificial	B-Application
intelligence	I-Application
,	O
image	O
processing	O
,	O
pattern	O
recognition	O
,	O
computer	O
vision	O
and	O
other	O
tasks	O
that	O
animal	O
brains	O
do	O
particularly	O
well	O
.	O
</s>
<s>
While	O
systolic	B-Architecture
arrays	I-Architecture
are	O
officially	O
classified	O
as	O
MISD	B-Operating_System
,	O
their	O
classification	O
is	O
somewhat	O
problematic	O
.	O
</s>
<s>
of	O
independent	O
values	O
,	O
the	O
systolic	B-Architecture
array	I-Architecture
is	O
definitely	O
not	O
SISD	B-Operating_System
.	O
</s>
<s>
Since	O
these	O
input	B-General_Concept
values	O
are	O
merged	O
and	O
combined	O
into	O
the	O
result(s )	O
and	O
do	O
not	O
maintain	O
their	O
independence	O
as	O
they	O
would	O
in	O
a	O
SIMD	B-Device
vector	O
processing	O
unit	O
,	O
the	O
array	B-Data_Structure
cannot	O
be	O
classified	O
as	O
such	O
.	O
</s>
<s>
Consequently	O
,	O
the	O
array	B-Data_Structure
cannot	O
be	O
classified	O
as	O
a	O
MIMD	B-Operating_System
either	O
,	O
because	O
MIMD	B-Operating_System
can	O
be	O
viewed	O
as	O
a	O
mere	O
collection	O
of	O
smaller	O
SISD	B-Operating_System
and	O
SIMD	B-Device
machines	O
.	O
</s>
<s>
Finally	O
,	O
because	O
the	O
data	O
swarm	B-Application
is	O
transformed	O
as	O
it	O
passes	O
through	O
the	O
array	B-Data_Structure
from	O
node	B-Data_Structure
to	O
node	B-Data_Structure
,	O
the	O
multiple	O
nodes	O
are	O
not	O
operating	O
on	O
the	O
same	O
data	O
,	O
which	O
makes	O
the	O
MISD	B-Operating_System
classification	O
a	O
misnomer	O
.	O
</s>
<s>
The	O
other	O
reason	O
why	O
a	O
systolic	B-Architecture
array	I-Architecture
should	O
not	O
qualify	O
as	O
a	O
MISD	B-Operating_System
is	O
the	O
same	O
as	O
the	O
one	O
which	O
disqualifies	O
it	O
from	O
the	O
SISD	B-Operating_System
category	O
:	O
The	O
input	B-General_Concept
data	O
is	O
typically	O
a	O
vector	O
not	O
a	O
single	O
data	O
value	O
,	O
although	O
one	O
could	O
argue	O
that	O
any	O
given	O
input	B-General_Concept
vector	O
is	O
a	O
single	O
item	O
of	O
data	O
.	O
</s>
<s>
In	O
spite	O
of	O
all	O
of	O
the	O
above	O
,	O
systolic	B-Architecture
arrays	I-Architecture
are	O
often	O
offered	O
as	O
a	O
classic	O
example	O
of	O
MISD	B-Operating_System
architecture	O
in	O
textbooks	O
on	O
parallel	B-Operating_System
computing	I-Operating_System
and	O
in	O
engineering	O
classes	O
.	O
</s>
<s>
If	O
the	O
array	B-Data_Structure
is	O
viewed	O
from	O
the	O
outside	O
as	O
atomic	B-General_Concept
it	O
should	O
perhaps	O
be	O
classified	O
as	O
SFMuDMeR	O
=	O
Single	O
Function	O
,	O
Multiple	O
Data	O
,	O
Merged	O
Result(s )	O
.	O
</s>
<s>
Systolic	B-Architecture
arrays	I-Architecture
use	O
a	O
pre-defined	O
computational	O
flow	O
graph	O
that	O
connects	O
their	O
nodes	O
.	O
</s>
<s>
between	O
each	O
node	B-Data_Structure
.	O
</s>
<s>
A	O
systolic	B-Architecture
array	I-Architecture
is	O
composed	O
of	O
matrix-like	O
rows	O
of	O
data	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
called	O
cells	O
.	O
</s>
<s>
Data	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
(	O
DPUs	O
)	O
are	O
similar	O
to	O
central	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
(	O
CPUs	B-Device
)	O
,	O
(	O
except	O
for	O
the	O
usual	O
lack	O
of	O
a	O
program	B-General_Concept
counter	I-General_Concept
,	O
since	O
operation	O
is	O
transport-triggered	B-General_Concept
,	O
i.e.	O
,	O
by	O
the	O
arrival	O
of	O
a	O
data	O
object	O
)	O
.	O
</s>
<s>
The	O
systolic	B-Architecture
array	I-Architecture
is	O
often	O
rectangular	O
where	O
data	O
flows	O
across	O
the	O
array	B-Data_Structure
between	O
neighbour	O
DPUs	O
,	O
often	O
with	O
different	O
data	O
flowing	O
in	O
different	O
directions	O
.	O
</s>
<s>
The	O
data	O
streams	O
entering	O
and	O
leaving	O
the	O
ports	O
of	O
the	O
array	B-Data_Structure
are	O
generated	O
by	O
auto-sequencing	O
memory	O
units	O
,	O
ASMs	O
.	O
</s>
<s>
In	O
embedded	B-Architecture
systems	I-Architecture
a	O
data	O
stream	O
may	O
also	O
be	O
input	B-General_Concept
from	O
and/or	O
output	O
to	O
an	O
external	O
source	O
.	O
</s>
<s>
An	O
example	O
of	O
a	O
systolic	O
algorithm	O
might	O
be	O
designed	O
for	O
matrix	B-Architecture
multiplication	O
.	O
</s>
<s>
One	O
matrix	B-Architecture
is	O
fed	O
in	O
a	O
row	O
at	O
a	O
time	O
from	O
the	O
top	O
of	O
the	O
array	B-Data_Structure
and	O
is	O
passed	O
down	O
the	O
array	B-Data_Structure
,	O
the	O
other	O
matrix	B-Architecture
is	O
fed	O
in	O
a	O
column	O
at	O
a	O
time	O
from	O
the	O
left	O
hand	O
side	O
of	O
the	O
array	B-Data_Structure
and	O
passes	O
from	O
left	O
to	O
right	O
.	O
</s>
<s>
Dummy	O
values	O
are	O
then	O
passed	O
in	O
until	O
each	O
processor	B-Architecture
has	O
seen	O
one	O
whole	O
row	O
and	O
one	O
whole	O
column	O
.	O
</s>
<s>
At	O
this	O
point	O
,	O
the	O
result	O
of	O
the	O
multiplication	O
is	O
stored	O
in	O
the	O
array	B-Data_Structure
and	O
can	O
now	O
be	O
output	O
a	O
row	O
or	O
a	O
column	O
at	O
a	O
time	O
,	O
flowing	O
down	O
or	O
across	O
the	O
array	B-Data_Structure
.	O
</s>
<s>
Systolic	B-Architecture
arrays	I-Architecture
are	O
arrays	O
of	O
DPUs	O
which	O
are	O
connected	O
to	O
a	O
small	O
number	O
of	O
nearest	O
neighbour	O
DPUs	O
in	O
a	O
mesh-like	O
topology	O
.	O
</s>
<s>
Because	O
the	O
traditional	O
systolic	B-Architecture
array	I-Architecture
synthesis	O
methods	O
have	O
been	O
practiced	O
by	O
algebraic	O
algorithms	O
,	O
only	O
uniform	O
arrays	O
with	O
only	O
linear	O
pipes	O
can	O
be	O
obtained	O
,	O
so	O
that	O
the	O
architectures	O
are	O
the	O
same	O
in	O
all	O
DPUs	O
.	O
</s>
<s>
The	O
consequence	O
is	O
,	O
that	O
only	O
applications	O
with	O
regular	O
data	O
dependencies	O
can	O
be	O
implemented	O
on	O
classical	O
systolic	B-Architecture
arrays	I-Architecture
.	O
</s>
<s>
Like	O
SIMD	B-Device
machines	O
,	O
clocked	O
systolic	B-Architecture
arrays	I-Architecture
compute	O
in	O
"	O
lock-step	O
"	O
with	O
each	O
processor	B-Architecture
undertaking	O
alternate	O
compute	O
|	O
communicate	O
phases	O
.	O
</s>
<s>
But	O
systolic	B-Architecture
arrays	I-Architecture
with	O
asynchronous	O
handshake	O
between	O
DPUs	O
are	O
called	O
wavefront	O
arrays	O
.	O
</s>
<s>
One	O
well-known	O
systolic	B-Architecture
array	I-Architecture
is	O
Carnegie	O
Mellon	O
University	O
's	O
iWarp	B-Device
processor	B-Architecture
,	O
which	O
has	O
been	O
manufactured	O
by	O
Intel	O
.	O
</s>
<s>
An	O
iWarp	B-Device
system	O
has	O
a	O
linear	O
array	B-Data_Structure
processor	B-Architecture
connected	O
by	O
data	O
buses	O
going	O
in	O
both	O
directions	O
.	O
</s>
<s>
Systolic	B-Architecture
arrays	I-Architecture
(	O
also	O
known	O
as	O
wavefront	O
processors	O
)	O
,	O
were	O
first	O
described	O
by	O
H	O
.	O
T	O
.	O
Kung	O
and	O
Charles	O
E	O
.	O
Leiserson	O
,	O
who	O
published	O
the	O
first	O
paper	O
describing	O
systolic	B-Architecture
arrays	I-Architecture
in	O
1979	O
.	O
</s>
<s>
However	O
,	O
the	O
first	O
machine	O
known	O
to	O
have	O
used	O
a	O
similar	O
technique	O
was	O
the	O
Colossus	B-Device
Mark	I-Device
II	I-Device
in	O
1944	O
.	O
</s>
<s>
A	O
linear	O
systolic	B-Architecture
array	I-Architecture
in	O
which	O
the	O
processors	O
are	O
arranged	O
in	O
pairs	O
:	O
one	O
multiplies	O
its	O
input	B-General_Concept
by	O
and	O
passes	O
the	O
result	O
to	O
the	O
right	O
,	O
the	O
next	O
adds	O
and	O
passes	O
the	O
result	O
to	O
the	O
right	O
.	O
</s>
<s>
(	O
Not	O
all	O
algorithms	O
can	O
be	O
implemented	O
as	O
systolic	B-Architecture
arrays	I-Architecture
.	O
</s>
<s>
Often	O
tricks	O
are	O
needed	O
to	O
map	O
such	O
algorithms	O
on	O
to	O
a	O
systolic	B-Architecture
array	I-Architecture
.	O
)	O
</s>
<s>
Cisco	O
PXF	O
network	O
processor	B-Architecture
is	O
internally	O
organized	O
as	O
systolic	B-Architecture
array	I-Architecture
.	O
</s>
<s>
Google	O
’s	O
TPU	B-Device
is	O
also	O
designed	O
around	O
a	O
systolic	B-Architecture
array	I-Architecture
.	O
</s>
<s>
MIT	O
Eyeriss	O
is	O
a	O
systolic	B-Architecture
array	I-Architecture
accelerator	O
for	O
convolutional	O
neural	O
networks	O
.	O
</s>
