<s>
A	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
or	O
system-on-chip	B-Architecture
(	O
SoC	O
;	O
pl	O
.	O
</s>
<s>
These	O
components	O
almost	O
always	O
include	O
on-chip	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
,	O
memory	B-General_Concept
interfaces	B-Protocol
,	O
input/output	B-General_Concept
devices	I-General_Concept
,	O
input/output	B-General_Concept
interfaces	B-Protocol
,	O
and	O
secondary	O
storage	O
interfaces	B-Protocol
,	O
often	O
alongside	O
other	O
components	O
such	O
as	O
radio	B-General_Concept
modems	I-General_Concept
and	O
a	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
(	O
GPU	B-Architecture
)	O
all	O
on	O
a	O
single	O
substrate	B-Architecture
or	O
microchip	O
.	O
</s>
<s>
Higher-performance	O
SoCs	O
are	O
often	O
paired	O
with	O
dedicated	O
and	O
physically	O
separate	O
memory	B-General_Concept
and	O
secondary	O
storage	O
(	O
such	O
as	O
LPDDR	O
and	O
eUFS	B-Device
or	O
eMMC	O
,	O
respectively	O
)	O
chips	O
,	O
that	O
may	O
be	O
layered	O
on	O
top	O
of	O
the	O
SoC	O
in	O
what	O
's	O
known	O
as	O
a	O
package	B-Algorithm
on	I-Algorithm
package	I-Algorithm
(	O
PoP	O
)	O
configuration	O
,	O
or	O
be	O
placed	O
close	O
to	O
the	O
SoC	O
.	O
</s>
<s>
Additionally	O
,	O
SoCs	O
may	O
use	O
separate	O
wireless	O
modems	B-Application
.	O
</s>
<s>
SoCs	O
are	O
in	O
contrast	O
to	O
the	O
common	O
traditional	O
motherboard-based	O
PC	B-Device
architecture	B-General_Concept
,	O
which	O
separates	O
components	O
based	O
on	O
function	O
and	O
connects	O
them	O
through	O
a	O
central	O
interfacing	B-Protocol
circuit	O
board	O
.	O
</s>
<s>
Whereas	O
a	O
motherboard	B-Device
houses	O
and	O
connects	O
detachable	O
or	O
replaceable	O
components	O
,	O
SoCs	O
integrate	O
all	O
of	O
these	O
components	O
into	O
a	O
single	O
integrated	O
circuit	O
.	O
</s>
<s>
An	O
SoC	O
will	O
typically	O
integrate	O
a	O
CPU	O
,	O
graphics	O
and	O
memory	B-General_Concept
interfaces	B-Protocol
,	O
secondary	O
storage	O
and	O
USB	B-Protocol
connectivity	O
,	O
random-access	B-Architecture
interface	O
and	O
read-only	B-Device
memories	I-Device
interface	O
on	O
a	O
single	O
chip	O
,	O
whereas	O
a	O
motherboard	B-Device
would	O
connect	O
these	O
modules	B-Architecture
as	O
discrete	O
components	O
or	O
expansion	B-Device
cards	I-Device
.	O
</s>
<s>
An	O
SoC	O
integrates	O
a	O
microcontroller	B-Architecture
,	O
microprocessor	B-Architecture
or	O
perhaps	O
several	O
processor	O
cores	O
with	O
peripherals	O
like	O
a	O
GPU	B-Architecture
,	O
Wi-Fi	O
and	O
cellular	O
network	O
radio	B-General_Concept
modems	I-General_Concept
,	O
and/or	O
one	O
or	O
more	O
coprocessors	B-General_Concept
.	O
</s>
<s>
Similar	O
to	O
how	O
a	O
microcontroller	B-Architecture
integrates	O
a	O
microprocessor	B-Architecture
with	O
peripheral	O
circuits	O
and	O
memory	B-General_Concept
,	O
an	O
SoC	O
can	O
be	O
seen	O
as	O
integrating	O
a	O
microcontroller	B-Architecture
with	O
even	O
more	O
advanced	O
peripherals	O
.	O
</s>
<s>
Compared	O
to	O
a	O
multi-chip	O
architecture	B-General_Concept
,	O
an	O
SoC	O
with	O
equivalent	O
functionality	O
will	O
have	O
increased	O
performance	O
and	O
reduced	O
power	O
consumption	O
as	O
well	O
as	O
a	O
smaller	O
semiconductor	O
die	O
area	O
.	O
</s>
<s>
By	O
definition	O
,	O
SoC	O
designs	O
are	O
fully	O
or	O
nearly	O
fully	O
integrated	O
across	O
different	O
component	O
modules	B-Architecture
.	O
</s>
<s>
For	O
these	O
reasons	O
,	O
there	O
has	O
been	O
a	O
general	O
trend	O
towards	O
tighter	O
integration	O
of	O
components	O
in	O
the	O
computer	O
hardware	O
industry	O
,	O
in	O
part	O
due	O
to	O
the	O
influence	O
of	O
SoCs	O
and	O
lessons	O
learned	O
from	O
the	O
mobile	O
and	O
embedded	B-Architecture
computing	I-Architecture
markets	O
.	O
</s>
<s>
SoCs	O
can	O
be	O
viewed	O
as	O
part	O
of	O
a	O
larger	O
trend	O
towards	O
embedded	B-Architecture
computing	I-Architecture
and	O
hardware	B-General_Concept
acceleration	I-General_Concept
.	O
</s>
<s>
SoCs	O
are	O
very	O
common	O
in	O
the	O
mobile	O
computing	O
(	O
such	O
as	O
in	O
smartphones	B-Application
and	O
tablet	B-Device
computers	I-Device
)	O
and	O
edge	B-Device
computing	I-Device
markets	O
.	O
</s>
<s>
They	O
are	O
also	O
commonly	O
used	O
in	O
embedded	B-Architecture
systems	I-Architecture
such	O
as	O
WiFi	O
routers	B-Protocol
and	O
the	B-Operating_System
Internet	I-Operating_System
of	I-Operating_System
things	I-Operating_System
.	O
</s>
<s>
SoCs	O
built	O
around	O
a	O
microcontroller	B-Architecture
,	O
</s>
<s>
SoCs	O
built	O
around	O
a	O
microprocessor	B-Architecture
,	O
often	O
found	O
in	O
mobile	O
phones	O
;	O
</s>
<s>
However	O
,	O
they	O
are	O
typically	O
used	O
in	O
mobile	O
computing	O
such	O
as	O
tablets	B-Device
,	O
smartphones	B-Application
,	O
smartwatches	B-Application
and	O
netbooks	B-Device
as	O
well	O
as	O
embedded	B-Architecture
systems	I-Architecture
and	O
in	O
applications	O
where	O
previously	O
microcontrollers	B-Architecture
would	O
be	O
used	O
.	O
</s>
<s>
Where	O
previously	O
only	O
microcontrollers	B-Architecture
could	O
be	O
used	O
,	O
SoCs	O
are	O
rising	O
to	O
prominence	O
in	O
the	O
embedded	B-Architecture
systems	I-Architecture
market	O
.	O
</s>
<s>
Tighter	O
system	O
integration	O
offers	O
better	O
reliability	B-Algorithm
and	O
mean	O
time	O
between	O
failure	O
,	O
and	O
SoCs	O
offer	O
more	O
advanced	O
functionality	O
and	O
computing	O
power	O
than	O
microcontrollers	B-Architecture
.	O
</s>
<s>
Applications	O
include	O
AI	B-General_Concept
acceleration	I-General_Concept
,	O
embedded	B-Architecture
machine	B-General_Concept
vision	I-General_Concept
,	O
data	O
collection	O
,	O
telemetry	O
,	O
vector	B-Operating_System
processing	I-Operating_System
and	O
ambient	B-Operating_System
intelligence	I-Operating_System
.	O
</s>
<s>
Often	O
embedded	B-Architecture
SoCs	O
target	O
the	B-Operating_System
internet	I-Operating_System
of	I-Operating_System
things	I-Operating_System
,	O
industrial	B-Operating_System
internet	I-Operating_System
of	I-Operating_System
things	I-Operating_System
and	O
edge	B-Device
computing	I-Device
markets	O
.	O
</s>
<s>
Mobile	O
computing	O
based	O
SoCs	O
always	O
bundle	O
processors	O
,	O
memories	B-General_Concept
,	O
on-chip	B-General_Concept
caches	I-General_Concept
,	O
wireless	B-General_Concept
networking	I-General_Concept
capabilities	O
and	O
often	O
digital	B-Device
camera	I-Device
hardware	O
and	O
firmware	B-Application
.	O
</s>
<s>
With	O
increasing	O
memory	B-General_Concept
sizes	O
,	O
high	O
end	O
SoCs	O
will	O
often	O
have	O
no	O
memory	B-General_Concept
and	O
flash	B-Device
storage	I-Device
and	O
instead	O
,	O
the	O
memory	B-General_Concept
and	O
flash	B-Device
memory	I-Device
will	O
be	O
placed	O
right	O
next	O
to	O
,	O
or	O
above	O
(	O
package	B-Algorithm
on	I-Algorithm
package	I-Algorithm
)	O
,	O
the	O
SoC	O
.	O
</s>
<s>
Snapdragon	B-Architecture
(	O
list	B-Application
)	O
,	O
used	O
in	O
many	O
LG	O
,	O
Xiaomi	O
,	O
Google	B-Device
Pixel	I-Device
,	O
HTC	B-Application
and	O
Samsung	B-Operating_System
Galaxy	I-Operating_System
smartphones	B-Application
.	O
</s>
<s>
In	O
2018	O
,	O
Snapdragon	B-Architecture
SoCs	I-Architecture
are	O
being	O
used	O
as	O
the	O
backbone	O
of	O
laptop	B-Device
computers	I-Device
running	O
Windows	B-Operating_System
10	I-Operating_System
,	O
marketed	O
as	O
"	O
Always	O
Connected	O
PCs	B-Device
"	O
.	O
</s>
<s>
In	O
1992	O
,	O
Acorn	O
Computers	O
produced	O
the	O
A3010	O
,	O
A3020	O
and	O
A4000	O
range	O
of	O
personal	B-Device
computers	I-Device
with	O
the	O
ARM250	O
SoC	O
.	O
</s>
<s>
It	O
combined	O
the	O
original	O
Acorn	O
ARM2	O
processor	O
with	O
a	O
memory	B-General_Concept
controller	O
(	O
MEMC	O
)	O
,	O
video	O
controller	O
(	O
VIDC	O
)	O
,	O
and	O
I/O	B-General_Concept
controller	O
(	O
IOC	O
)	O
.	O
</s>
<s>
In	O
previous	O
Acorn	O
ARM-powered	O
computers	O
,	O
these	O
were	O
four	O
discrete	O
chips	O
.	O
</s>
<s>
The	O
ARM7500	O
chip	O
was	O
their	O
second-generation	O
SoC	O
,	O
based	O
on	O
the	O
ARM700	O
,	O
VIDC20	O
and	O
IOMD	O
controllers	O
,	O
and	O
was	O
widely	O
licensed	O
in	O
embedded	B-Architecture
devices	I-Architecture
such	O
as	O
set-top-boxes	O
,	O
as	O
well	O
as	O
later	O
Acorn	O
personal	B-Device
computers	I-Device
.	O
</s>
<s>
SoCs	O
are	O
being	O
applied	O
to	O
mainstream	O
personal	B-Device
computers	I-Device
as	O
of	O
2018	O
.	O
</s>
<s>
They	O
are	O
particularly	O
applied	O
to	O
laptops	B-Device
and	O
tablet	B-Device
PCs	I-Device
.	O
</s>
<s>
Tablet	B-Device
and	O
laptop	B-Device
manufacturers	O
have	O
learned	O
lessons	O
from	O
embedded	B-Architecture
systems	I-Architecture
and	O
smartphone	B-Application
markets	O
about	O
reduced	O
power	O
consumption	O
,	O
better	O
performance	O
and	O
reliability	B-Algorithm
from	O
tighter	O
integration	O
of	O
hardware	O
and	O
firmware	B-Application
modules	B-Architecture
,	O
and	O
LTE	O
and	O
other	O
wireless	B-General_Concept
network	I-General_Concept
communications	O
integrated	O
on	O
chip	O
(	O
integrated	O
network	B-Protocol
interface	I-Protocol
controllers	I-Protocol
)	O
.	O
</s>
<s>
ARM-based	O
:	O
</s>
<s>
x86-based	O
:	O
</s>
<s>
An	O
SoC	O
consists	O
of	O
hardware	O
functional	B-General_Concept
units	I-General_Concept
,	O
including	O
microprocessors	B-Architecture
that	O
run	O
software	B-Application
code	I-Application
,	O
as	O
well	O
as	O
a	O
communications	O
subsystem	O
to	O
connect	O
,	O
control	O
,	O
direct	O
and	O
interface	O
between	O
these	O
functional	O
modules	B-Architecture
.	O
</s>
<s>
Processor	O
cores	O
can	O
be	O
a	O
microcontroller	B-Architecture
,	O
microprocessor	B-Architecture
( μP	O
)	O
,	O
digital	B-Architecture
signal	I-Architecture
processor	I-Architecture
(	O
DSP	O
)	O
or	O
application-specific	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
processor	I-General_Concept
(	O
ASIP	O
)	O
core	O
.	O
</s>
<s>
ASIPs	O
have	O
instruction	B-General_Concept
sets	I-General_Concept
that	O
are	O
customized	O
for	O
an	O
application	B-Architecture
domain	I-Architecture
and	O
designed	O
to	O
be	O
more	O
efficient	O
than	O
general-purpose	O
instructions	B-General_Concept
for	O
a	O
specific	O
type	O
of	O
workload	O
.	O
</s>
<s>
Multiprocessor	B-General_Concept
SoCs	I-General_Concept
have	O
more	O
than	O
one	O
processor	O
core	O
by	O
definition	O
.	O
</s>
<s>
Whether	O
single-core	O
,	O
multi-core	B-Architecture
or	O
manycore	B-General_Concept
,	O
SoC	O
processor	O
cores	O
typically	O
use	O
RISC	B-Architecture
instruction	I-Architecture
set	I-Architecture
architectures	O
.	O
</s>
<s>
RISC	B-Architecture
architectures	I-Architecture
are	O
advantageous	O
over	O
CISC	B-Architecture
processors	I-Architecture
for	O
SoCs	O
because	O
they	O
require	O
less	O
digital	O
logic	O
,	O
and	O
therefore	O
less	O
power	O
and	O
area	O
on	O
board	O
,	O
and	O
in	O
the	O
embedded	B-Architecture
and	O
mobile	O
computing	O
markets	O
,	O
area	O
and	O
power	O
are	O
often	O
highly	O
constrained	O
.	O
</s>
<s>
In	O
particular	O
,	O
SoC	O
processor	O
cores	O
often	O
use	O
the	O
ARM	B-Architecture
architecture	I-Architecture
because	O
it	O
is	O
a	O
soft	B-Device
processor	I-Device
specified	O
as	O
an	O
IP	B-Architecture
core	I-Architecture
and	O
is	O
more	O
power	O
efficient	O
than	O
x86	B-Operating_System
.	O
</s>
<s>
SoCs	O
must	O
have	O
semiconductor	B-Architecture
memory	I-Architecture
blocks	O
to	O
perform	O
their	O
computation	O
,	O
as	O
do	O
microcontrollers	B-Architecture
and	O
other	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
Depending	O
on	O
the	O
application	O
,	O
SoC	O
memory	B-General_Concept
may	O
form	O
a	O
memory	B-General_Concept
hierarchy	I-General_Concept
and	O
cache	B-General_Concept
hierarchy	I-General_Concept
.	O
</s>
<s>
In	O
the	O
mobile	O
computing	O
market	O
,	O
this	O
is	O
common	O
,	O
but	O
in	O
many	O
low-power	O
embedded	B-Architecture
microcontrollers	B-Architecture
,	O
this	O
is	O
not	O
necessary	O
.	O
</s>
<s>
Memory	B-General_Concept
technologies	O
for	O
SoCs	O
include	O
read-only	B-Device
memory	I-Device
(	O
ROM	B-Device
)	O
,	O
random-access	B-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
,	O
Electrically	B-General_Concept
Erasable	I-General_Concept
Programmable	I-General_Concept
ROM	I-General_Concept
(	O
EEPROM	B-General_Concept
)	O
and	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
As	O
in	O
other	O
computer	O
systems	O
,	O
RAM	B-Architecture
can	O
be	O
subdivided	O
into	O
relatively	O
faster	O
but	O
more	O
expensive	O
static	B-Architecture
RAM	I-Architecture
(	O
SRAM	O
)	O
and	O
the	O
slower	O
but	O
cheaper	O
dynamic	O
RAM	B-Architecture
(	O
DRAM	O
)	O
.	O
</s>
<s>
When	O
an	O
SoC	O
has	O
a	O
cache	B-General_Concept
hierarchy	I-General_Concept
,	O
SRAM	O
will	O
usually	O
be	O
used	O
to	O
implement	O
processor	B-General_Concept
registers	I-General_Concept
and	O
cores	O
 '	O
built-in	O
caches	B-General_Concept
whereas	O
DRAM	O
will	O
be	O
used	O
for	O
main	O
memory	B-General_Concept
.	O
</s>
<s>
"	O
Main	O
memory	B-General_Concept
"	O
may	O
be	O
specific	O
to	O
a	O
single	O
processor	O
(	O
which	O
can	O
be	O
multi-core	B-Architecture
)	O
when	O
the	O
SoC	O
has	B-General_Concept
multiple	I-General_Concept
processors	I-General_Concept
,	O
in	O
this	O
case	O
it	O
is	O
distributed	B-Operating_System
memory	I-Operating_System
and	O
must	O
be	O
sent	O
via	O
on-chip	O
to	O
be	O
accessed	O
by	O
a	O
different	O
processor	O
.	O
</s>
<s>
For	O
further	O
discussion	O
of	O
multi-processing	O
memory	B-General_Concept
issues	O
,	O
see	O
cache	B-General_Concept
coherence	I-General_Concept
and	O
memory	B-General_Concept
latency	I-General_Concept
.	O
</s>
<s>
SoCs	O
include	O
external	O
interfaces	B-Protocol
,	O
typically	O
for	O
communication	O
protocols	O
.	O
</s>
<s>
These	O
are	O
often	O
based	O
upon	O
industry	O
standards	O
such	O
as	O
USB	B-Protocol
,	O
FireWire	B-Protocol
,	O
Ethernet	O
,	O
USART	O
,	O
SPI	B-Architecture
,	O
HDMI	B-Protocol
,	O
I²C	O
,	O
CSI	O
,	O
etc	O
.	O
</s>
<s>
These	O
interfaces	B-Protocol
will	O
differ	O
according	O
to	O
the	O
intended	O
application	O
.	O
</s>
<s>
Wireless	B-General_Concept
networking	I-General_Concept
protocols	O
such	O
as	O
Wi-Fi	O
,	O
Bluetooth	B-Protocol
,	O
6LoWPAN	B-Protocol
and	O
near-field	O
communication	O
may	O
also	O
be	O
supported	O
.	O
</s>
<s>
When	O
needed	O
,	O
SoCs	O
include	O
analog	O
interfaces	B-Protocol
including	O
analog-to-digital	O
and	O
digital-to-analog	O
converters	O
,	O
often	O
for	O
signal	O
processing	O
.	O
</s>
<s>
These	O
may	O
be	O
able	O
to	O
interface	O
with	O
different	O
types	O
of	O
sensors	O
or	O
actuators	B-Algorithm
,	O
including	O
smart	B-Algorithm
transducers	I-Algorithm
.	O
</s>
<s>
They	O
may	O
interface	O
with	O
application-specific	O
modules	B-Architecture
or	O
shields	O
.	O
</s>
<s>
Digital	B-Architecture
signal	I-Architecture
processor	I-Architecture
(	O
DSP	O
)	O
cores	O
are	O
often	O
included	O
on	O
SoCs	O
.	O
</s>
<s>
They	O
perform	O
signal	O
processing	O
operations	O
in	O
SoCs	O
for	O
sensors	O
,	O
actuators	B-Algorithm
,	O
data	O
collection	O
,	O
data	B-General_Concept
analysis	I-General_Concept
and	O
multimedia	O
processing	O
.	O
</s>
<s>
DSP	O
cores	O
typically	O
feature	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
and	O
single	B-Device
instruction	I-Device
,	I-Device
multiple	I-Device
data	I-Device
(	O
SIMD	B-Device
)	O
instruction	B-General_Concept
set	I-General_Concept
architectures	I-General_Concept
,	O
and	O
are	O
therefore	O
highly	O
amenable	O
to	O
exploiting	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
through	O
parallel	B-Operating_System
processing	I-Operating_System
and	O
superscalar	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
DSP	O
cores	O
most	O
often	O
feature	O
application-specific	O
instructions	B-General_Concept
,	O
and	O
as	O
such	O
are	O
typically	O
application-specific	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
processors	I-General_Concept
(	O
ASIP	O
)	O
.	O
</s>
<s>
Such	O
application-specific	O
instructions	B-General_Concept
correspond	O
to	O
dedicated	O
hardware	O
functional	B-General_Concept
units	I-General_Concept
that	O
compute	O
those	O
instructions	B-General_Concept
.	O
</s>
<s>
Typical	O
DSP	O
instructions	B-General_Concept
include	O
multiply-accumulate	B-Algorithm
,	O
Fast	O
Fourier	O
transform	O
,	O
fused	O
multiply-add	B-Algorithm
,	O
and	O
convolutions	B-Language
.	O
</s>
<s>
SoC	O
peripherals	O
including	O
counter-timers	O
,	O
real-time	O
timers	O
and	O
power-on	B-Application
reset	I-Application
generators	O
.	O
</s>
<s>
SoCs	O
comprise	O
many	O
execution	B-General_Concept
units	I-General_Concept
.	O
</s>
<s>
These	O
units	O
must	O
often	O
send	O
data	O
and	O
instructions	B-General_Concept
back	O
and	O
forth	O
.	O
</s>
<s>
Originally	O
,	O
as	O
with	O
other	O
microcomputer	B-Architecture
technologies	O
,	O
data	B-General_Concept
bus	I-General_Concept
architectures	O
were	O
used	O
,	O
but	O
recently	O
designs	O
based	O
on	O
sparse	O
intercommunication	O
networks	O
known	O
as	O
networks-on-chip	B-Architecture
(	O
NoC	B-Architecture
)	O
have	O
risen	O
to	O
prominence	O
and	O
are	O
forecast	O
to	O
overtake	O
bus	O
architectures	O
for	O
SoC	O
design	O
in	O
the	O
near	O
future	O
.	O
</s>
<s>
Historically	O
,	O
a	O
shared	O
global	O
computer	B-General_Concept
bus	I-General_Concept
typically	O
connected	O
the	O
different	O
components	O
,	O
also	O
called	O
"	O
blocks	O
"	O
of	O
the	O
SoC	O
.	O
</s>
<s>
A	O
very	O
common	O
bus	O
for	O
SoC	O
communications	O
is	O
ARM	B-Architecture
's	O
royalty-free	O
Advanced	B-Architecture
Microcontroller	I-Architecture
Bus	I-Architecture
Architecture	I-Architecture
(	O
AMBA	B-Architecture
)	O
standard	O
.	O
</s>
<s>
Direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
controllers	O
route	O
data	O
directly	O
between	O
external	O
interfaces	B-Protocol
and	O
SoC	O
memory	B-General_Concept
,	O
bypassing	O
the	O
CPU	O
or	O
control	B-General_Concept
unit	I-General_Concept
,	O
thereby	O
increasing	O
the	O
data	O
throughput	O
of	O
the	O
SoC	O
.	O
</s>
<s>
This	O
is	O
similar	O
to	O
some	O
device	B-Application
drivers	I-Application
of	O
peripherals	O
on	O
component-based	O
multi-chip	B-Algorithm
module	I-Algorithm
PC	B-Device
architectures	O
.	O
</s>
<s>
Computer	B-General_Concept
buses	I-General_Concept
are	O
limited	O
in	O
scalability	B-Architecture
,	O
supporting	O
only	O
up	O
to	O
tens	O
of	O
cores	O
(	O
multicore	B-Architecture
)	O
on	O
a	O
single	O
chip	O
.	O
</s>
<s>
Wire	O
delay	O
is	O
not	O
scalable	B-Architecture
due	O
to	O
continued	O
miniaturization	O
,	O
system	O
performance	O
does	B-Architecture
not	I-Architecture
scale	I-Architecture
with	O
the	O
number	O
of	O
cores	O
attached	O
,	O
the	O
SoC	O
's	O
operating	O
frequency	O
must	O
decrease	O
with	O
each	O
additional	O
core	O
attached	O
for	O
power	O
to	O
be	O
sustainable	O
,	O
and	O
long	O
wires	O
consume	O
large	O
amounts	O
of	O
electrical	O
power	O
.	O
</s>
<s>
These	O
challenges	O
are	O
prohibitive	O
to	O
supporting	O
manycore	B-General_Concept
systems	B-Architecture
on	I-Architecture
chip	I-Architecture
.	O
</s>
<s>
In	O
the	O
late	O
2010s	O
,	O
a	O
trend	O
of	O
SoCs	O
implementing	O
communications	O
subsystems	O
in	O
terms	O
of	O
a	O
network-like	O
topology	B-Architecture
instead	O
of	O
bus-based	B-General_Concept
protocols	O
has	O
emerged	O
.	O
</s>
<s>
A	O
trend	O
towards	O
more	B-General_Concept
processor	I-General_Concept
cores	I-General_Concept
on	I-General_Concept
SoCs	I-General_Concept
has	O
caused	O
on-chip	O
communication	O
efficiency	O
to	O
become	O
one	O
of	O
the	O
key	O
factors	O
in	O
determining	O
the	O
overall	O
system	O
performance	O
and	O
cost	O
.	O
</s>
<s>
This	O
has	O
led	O
to	O
the	O
emergence	O
of	O
interconnection	O
networks	O
with	O
router-based	O
packet	B-Protocol
switching	I-Protocol
known	O
as	O
"	O
networks	B-Architecture
on	I-Architecture
chip	I-Architecture
"	O
(	O
NoCs	B-Architecture
)	O
to	O
overcome	O
the	O
bottlenecks	O
of	O
bus-based	B-General_Concept
networks	O
.	O
</s>
<s>
Networks-on-chip	B-Architecture
have	O
advantages	O
including	O
destination	O
-	O
and	O
application-specific	O
routing	B-Protocol
,	O
greater	O
power	O
efficiency	O
and	O
reduced	O
possibility	O
of	O
bus	B-Architecture
contention	I-Architecture
.	O
</s>
<s>
Network-on-chip	B-Architecture
architectures	O
take	O
inspiration	O
from	O
communication	O
protocols	O
like	O
TCP	B-Protocol
and	O
the	O
Internet	B-Protocol
protocol	I-Protocol
suite	I-Protocol
for	O
on-chip	O
communication	O
,	O
although	O
they	O
typically	O
have	O
fewer	O
network	B-Application
layers	I-Application
.	O
</s>
<s>
Optimal	O
network-on-chip	B-Architecture
network	B-Architecture
architectures	I-Architecture
are	O
an	O
ongoing	O
area	O
of	O
much	O
research	O
interest	O
.	O
</s>
<s>
NoC	B-Architecture
architectures	O
range	O
from	O
traditional	O
distributed	B-Architecture
computing	I-Architecture
network	B-Architecture
topologies	I-Architecture
such	O
as	O
torus	B-Operating_System
,	O
hypercube	B-Architecture
,	O
meshes	B-Architecture
and	O
tree	B-Data_Structure
networks	I-Data_Structure
to	O
genetic	O
algorithm	O
scheduling	O
to	O
randomized	B-General_Concept
algorithms	I-General_Concept
such	O
as	O
random	O
walks	O
with	O
branching	O
and	O
randomized	O
time	B-Protocol
to	I-Protocol
live	I-Protocol
(	O
TTL	O
)	O
.	O
</s>
<s>
Many	O
SoC	O
researchers	O
consider	O
NoC	B-Architecture
architectures	O
to	O
be	O
the	O
future	O
of	O
SoC	O
design	O
because	O
they	O
have	O
been	O
shown	O
to	O
efficiently	O
meet	O
power	O
and	O
throughput	O
needs	O
of	O
SoC	O
designs	O
.	O
</s>
<s>
Current	O
NoC	B-Architecture
architectures	O
are	O
two-dimensional	O
.	O
</s>
<s>
2D	O
IC	O
design	O
has	O
limited	O
floorplanning	O
choices	O
as	O
the	O
number	O
of	O
cores	O
in	O
SoCs	O
increase	O
,	O
so	O
as	O
three-dimensional	B-Architecture
integrated	I-Architecture
circuits	I-Architecture
(	O
3DICs	B-Architecture
)	O
emerge	O
,	O
SoC	O
designers	O
are	O
looking	O
towards	O
building	O
three-dimensional	O
on-chip	B-Architecture
networks	I-Architecture
known	O
as	O
3DNoCs	O
.	O
</s>
<s>
A	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
consists	O
of	O
both	O
the	O
hardware	O
,	O
described	O
in	O
,	O
and	O
the	O
software	O
controlling	O
the	O
microcontroller	B-Architecture
,	O
microprocessor	B-Architecture
or	O
digital	B-Architecture
signal	I-Architecture
processor	I-Architecture
cores	O
,	O
peripherals	O
and	O
interfaces	B-Protocol
.	O
</s>
<s>
Most	O
SoCs	O
are	O
developed	O
from	O
pre-qualified	O
hardware	O
component	O
IP	B-Architecture
core	I-Architecture
specifications	I-Architecture
for	O
the	O
hardware	O
elements	O
and	O
execution	B-General_Concept
units	I-General_Concept
,	O
collectively	O
"	O
blocks	O
"	O
,	O
described	O
above	O
,	O
together	O
with	O
software	O
device	B-Application
drivers	I-Application
that	O
may	O
control	O
their	O
operation	O
.	O
</s>
<s>
Of	O
particular	O
importance	O
are	O
the	O
protocol	B-Protocol
stacks	I-Protocol
that	O
drive	O
industry-standard	O
interfaces	B-Protocol
like	O
USB	B-Protocol
.	O
</s>
<s>
The	O
hardware	O
blocks	O
are	O
put	O
together	O
using	O
computer-aided	B-Application
design	I-Application
tools	O
,	O
specifically	O
electronic	O
design	O
automation	O
tools	O
;	O
the	O
software	B-Architecture
modules	I-Architecture
are	O
integrated	O
using	O
a	O
software	O
integrated	B-Application
development	I-Application
environment	I-Application
.	O
</s>
<s>
SoCs	O
components	O
are	O
also	O
often	O
designed	O
in	O
high-level	B-Language
programming	I-Language
languages	I-Language
such	O
as	O
C++	B-Language
,	O
MATLAB	B-Language
or	O
SystemC	B-Language
and	O
converted	O
to	O
RTL	O
designs	O
through	O
high-level	B-General_Concept
synthesis	I-General_Concept
(	O
HLS	O
)	O
tools	O
such	O
as	O
C	B-Application
to	I-Application
HDL	I-Application
or	O
flow	B-Language
to	I-Language
HDL	I-Language
.	O
</s>
<s>
HLS	O
products	O
called	O
"	O
algorithmic	B-General_Concept
synthesis	I-General_Concept
"	O
allow	O
designers	O
to	O
use	O
C++	B-Language
to	O
model	O
and	O
synthesize	O
system	O
,	O
circuit	O
,	O
software	O
and	O
verification	O
levels	O
all	O
in	O
one	O
high	B-Language
level	I-Language
language	I-Language
commonly	O
known	O
to	O
computer	O
engineers	O
in	O
a	O
manner	O
independent	O
of	O
time	O
scales	O
,	O
which	O
are	O
typically	O
specified	O
in	O
HDL	O
.	O
</s>
<s>
Other	O
components	O
can	O
remain	O
software	O
and	O
be	O
compiled	O
and	O
embedded	B-Architecture
onto	O
soft-core	B-Device
processors	I-Device
included	O
in	O
the	O
SoC	O
as	O
modules	B-Architecture
in	O
HDL	O
as	O
IP	B-Architecture
cores	I-Architecture
.	O
</s>
<s>
Once	O
the	O
architecture	B-General_Concept
of	O
the	O
SoC	O
has	O
been	O
defined	O
,	O
any	O
new	O
hardware	O
elements	O
are	O
written	O
in	O
an	O
abstract	O
hardware	O
description	O
language	O
termed	O
register	O
transfer	O
level	O
(	O
RTL	O
)	O
which	O
defines	O
the	O
circuit	O
behavior	O
,	O
or	O
synthesized	O
into	O
RTL	O
from	O
a	O
high	B-Language
level	I-Language
language	I-Language
through	O
high-level	B-General_Concept
synthesis	I-General_Concept
.	O
</s>
<s>
The	O
logic	O
specified	O
to	O
connect	O
these	O
components	O
and	O
convert	O
between	O
possibly	O
different	O
interfaces	B-Protocol
provided	O
by	O
different	O
vendors	O
is	O
called	O
glue	O
logic	O
.	O
</s>
<s>
Chips	O
are	O
verified	O
for	O
validation	O
correctness	O
before	O
being	O
sent	O
to	O
a	O
semiconductor	B-Algorithm
foundry	I-Algorithm
.	O
</s>
<s>
This	O
process	O
is	O
called	O
functional	O
verification	O
and	O
it	O
accounts	O
for	O
a	O
significant	O
portion	O
of	O
the	O
time	O
and	O
energy	O
expended	O
in	O
the	O
chip	B-General_Concept
design	I-General_Concept
life	O
cycle	O
,	O
often	O
quoted	O
as	O
70%	O
.	O
</s>
<s>
With	O
the	O
growing	O
complexity	O
of	O
chips	O
,	O
hardware	B-Language
verification	I-Language
languages	I-Language
like	O
SystemVerilog	B-Language
,	O
SystemC	B-Language
,	O
e	B-Language
,	O
and	O
OpenVera	B-Language
are	O
being	O
used	O
.	O
</s>
<s>
Bugs	B-Error_Name
found	O
in	O
the	O
verification	O
stage	O
are	O
reported	O
to	O
the	O
designer	O
.	O
</s>
<s>
Traditionally	O
,	O
engineers	O
have	O
employed	O
simulation	O
acceleration	O
,	O
emulation	B-Application
or	O
prototyping	O
on	O
reprogrammable	B-Architecture
hardware	I-Architecture
to	O
verify	O
and	O
debug	O
hardware	O
and	O
software	O
for	O
SoC	O
designs	O
prior	O
to	O
the	O
finalization	O
of	O
the	O
design	O
,	O
known	O
as	O
tape-out	O
.	O
</s>
<s>
Field-programmable	B-Architecture
gate	I-Architecture
arrays	I-Architecture
(	O
FPGAs	B-Architecture
)	O
are	O
favored	O
for	O
prototyping	O
SoCs	O
because	O
FPGA	B-Architecture
prototypes	O
are	O
reprogrammable	O
,	O
allow	O
debugging	O
and	O
are	O
more	O
flexible	O
than	O
application-specific	O
integrated	O
circuits	O
(	O
ASICs	O
)	O
.	O
</s>
<s>
With	O
high	O
capacity	O
and	O
fast	O
compilation	O
time	O
,	O
simulation	O
acceleration	O
and	O
emulation	B-Application
are	O
powerful	O
technologies	O
that	O
provide	O
wide	O
visibility	O
into	O
systems	O
.	O
</s>
<s>
Acceleration	O
and	O
emulation	B-Application
boxes	O
are	O
also	O
very	O
large	O
and	O
expensive	O
at	O
over	O
US$1million	O
.	O
</s>
<s>
FPGA	B-Architecture
prototypes	O
,	O
in	O
contrast	O
,	O
use	O
FPGAs	B-Architecture
directly	O
to	O
enable	O
engineers	O
to	O
validate	O
and	O
test	O
at	O
,	O
or	O
close	O
to	O
,	O
a	O
system	O
's	O
full	O
operating	O
frequency	O
with	O
real-world	O
stimuli	O
.	O
</s>
<s>
Tools	O
such	O
as	O
Certus	O
are	O
used	O
to	O
insert	O
probes	O
in	O
the	O
FPGA	B-Architecture
RTL	O
that	O
make	O
signals	O
available	O
for	O
observation	O
.	O
</s>
<s>
This	O
is	O
used	O
to	O
debug	O
hardware	O
,	O
firmware	B-Application
and	O
software	O
interactions	O
across	O
multiple	O
FPGAs	B-Architecture
with	O
capabilities	O
similar	O
to	O
a	O
logic	O
analyzer	O
.	O
</s>
<s>
SoCs	O
must	O
optimize	O
power	O
use	O
,	O
area	O
on	O
die	O
,	O
communication	O
,	O
positioning	O
for	O
locality	B-General_Concept
between	O
modular	B-Architecture
units	O
and	O
other	O
factors	O
.	O
</s>
<s>
If	O
optimization	O
was	O
not	O
necessary	O
,	O
the	O
engineers	O
would	O
use	O
a	O
multi-chip	B-Algorithm
module	I-Algorithm
architecture	B-General_Concept
without	O
accounting	O
for	O
the	O
area	O
use	O
,	O
power	O
consumption	O
or	O
performance	O
of	O
the	O
system	O
to	O
the	O
same	O
extent	O
.	O
</s>
<s>
Therefore	O
,	O
sophisticated	O
optimization	O
algorithms	O
are	O
often	O
required	O
and	O
it	O
may	O
be	O
practical	O
to	O
use	O
approximation	B-Algorithm
algorithms	I-Algorithm
or	O
heuristics	B-Algorithm
in	O
some	O
cases	O
.	O
</s>
<s>
SoC	O
systems	O
often	O
require	O
long	O
battery	O
life	O
(	O
such	O
as	O
smartphones	B-Application
)	O
,	O
can	O
potentially	O
spend	O
months	O
or	O
years	O
without	O
a	O
power	O
source	O
while	O
needing	O
to	O
maintain	O
autonomous	O
function	O
,	O
and	O
often	O
are	O
limited	O
in	O
power	O
use	O
by	O
a	O
high	O
number	O
of	O
embedded	B-Architecture
SoCs	O
being	O
networked	B-Architecture
together	I-Architecture
in	O
an	O
area	O
.	O
</s>
<s>
The	O
amount	O
of	O
energy	O
used	O
in	O
a	O
circuit	O
is	O
the	O
integral	O
of	O
power	O
consumed	O
with	O
respect	O
to	O
time	O
,	O
and	O
the	O
average	B-Algorithm
rate	I-Algorithm
of	O
power	O
consumption	O
is	O
the	O
product	O
of	O
current	O
by	O
voltage	O
.	O
</s>
<s>
SoCs	O
are	O
frequently	O
embedded	B-Architecture
in	O
portable	B-Application
devices	I-Application
such	O
as	O
smartphones	B-Application
,	O
GPS	O
navigation	O
devices	O
,	O
digital	O
watches	O
(	O
including	O
smartwatches	B-Application
)	O
and	O
netbooks	B-Device
.	O
</s>
<s>
Customers	O
want	O
long	O
battery	O
lives	O
for	O
mobile	B-Application
computing	I-Application
devices	I-Application
,	O
another	O
reason	O
that	O
power	O
consumption	O
must	O
be	O
minimized	O
in	O
SoCs	O
.	O
</s>
<s>
Multimedia	O
applications	O
are	O
often	O
executed	O
on	O
these	O
devices	O
,	O
including	O
video	O
games	O
,	O
video	B-Application
streaming	I-Application
,	O
image	B-Algorithm
processing	I-Algorithm
;	O
all	O
of	O
which	O
have	O
grown	O
in	O
computational	O
complexity	O
in	O
recent	O
years	O
with	O
user	O
demands	O
and	O
expectations	O
for	O
higher-quality	O
multimedia	O
.	O
</s>
<s>
Computation	O
is	O
more	O
demanding	O
as	O
expectations	O
move	O
towards	O
3D	B-Algorithm
video	I-Algorithm
at	O
high	B-Algorithm
resolution	I-Algorithm
with	O
multiple	O
standards	O
,	O
so	O
SoCs	O
performing	O
multimedia	O
tasks	B-General_Concept
must	O
be	O
computationally	O
capable	O
platform	O
while	O
being	O
low	O
power	O
to	O
run	O
off	O
a	O
standard	O
mobile	O
battery	O
.	O
</s>
<s>
Many	O
applications	O
such	O
as	O
edge	B-Device
computing	I-Device
,	O
distributed	B-Architecture
processing	I-Architecture
and	O
ambient	B-Operating_System
intelligence	I-Operating_System
require	O
a	O
certain	O
level	O
of	O
computational	O
performance	O
,	O
but	O
power	O
is	O
limited	O
in	O
most	O
SoC	O
environments	O
.	O
</s>
<s>
The	O
ARM	B-Architecture
architecture	I-Architecture
has	O
greater	O
performance	O
per	O
watt	O
than	O
x86	B-Operating_System
in	O
embedded	B-Architecture
systems	I-Architecture
,	O
so	O
it	O
is	O
preferred	O
over	O
x86	B-Operating_System
for	O
most	O
SoC	O
applications	O
requiring	O
an	O
embedded	B-Device
processor	I-Device
.	O
</s>
<s>
The	O
power	O
densities	O
of	O
high	O
speed	O
integrated	O
circuits	O
,	O
particularly	O
microprocessors	B-Architecture
and	O
including	O
SoCs	O
,	O
have	O
become	O
highly	O
uneven	O
.	O
</s>
<s>
Too	O
much	O
waste	O
heat	O
can	O
damage	O
circuits	O
and	O
erode	O
reliability	B-Algorithm
of	O
the	O
circuit	O
over	O
time	O
.	O
</s>
<s>
High	O
temperatures	O
and	O
thermal	O
stress	O
negatively	O
impact	O
reliability	B-Algorithm
,	O
stress	B-Algorithm
migration	I-Algorithm
,	O
decreased	O
mean	O
time	O
between	O
failures	O
,	O
electromigration	O
,	O
wire	B-Algorithm
bonding	I-Algorithm
,	O
metastability	O
and	O
other	O
performance	O
degradation	O
of	O
the	O
SoC	O
over	O
time	O
.	O
</s>
<s>
Because	O
of	O
high	O
transistor	O
counts	O
on	O
modern	O
devices	O
,	O
oftentimes	O
a	O
layout	O
of	O
sufficient	O
throughput	O
and	O
high	O
transistor	O
density	O
is	O
physically	O
realizable	O
from	O
fabrication	B-Architecture
processes	I-Architecture
but	O
would	O
result	O
in	O
unacceptably	O
high	O
amounts	O
of	O
heat	O
in	O
the	O
circuit	O
's	O
volume	O
.	O
</s>
<s>
This	O
can	O
be	O
accomplished	O
by	O
laying	O
out	O
elements	O
with	O
proper	O
proximity	O
and	O
locality	B-General_Concept
to	O
each-other	O
to	O
minimize	O
the	O
interconnection	O
delays	O
and	O
maximize	O
the	O
speed	O
at	O
which	O
data	O
is	O
communicated	O
between	O
modules	B-Architecture
,	O
functional	B-General_Concept
units	I-General_Concept
and	O
memories	B-General_Concept
.	O
</s>
<s>
In	O
general	O
,	O
optimizing	O
to	O
minimize	O
latency	O
is	O
an	O
NP-complete	O
problem	O
equivalent	O
to	O
the	O
boolean	B-Algorithm
satisfiability	I-Algorithm
problem	I-Algorithm
.	O
</s>
<s>
For	O
tasks	B-General_Concept
running	O
on	O
processor	O
cores	O
,	O
latency	O
and	O
throughput	O
can	O
be	O
improved	O
with	O
task	O
scheduling	O
.	O
</s>
<s>
Some	O
tasks	B-General_Concept
run	O
in	O
application-specific	O
hardware	O
units	O
,	O
however	O
,	O
and	O
even	O
task	O
scheduling	O
may	O
not	O
be	O
sufficient	O
to	O
optimize	O
all	O
software-based	O
tasks	B-General_Concept
to	O
meet	O
timing	O
and	O
throughput	O
constraints	O
.	O
</s>
<s>
Systems	B-Architecture
on	I-Architecture
chip	I-Architecture
are	O
modeled	O
with	O
standard	O
hardware	O
verification	B-Application
and	I-Application
validation	I-Application
techniques	O
,	O
but	O
additional	O
techniques	O
are	O
used	O
to	O
model	O
and	O
optimize	O
SoC	O
design	O
alternatives	O
to	O
make	O
the	O
system	O
optimal	O
with	O
respect	O
to	O
multiple-criteria	O
decision	O
analysis	O
on	O
the	O
above	O
optimization	O
targets	O
.	O
</s>
<s>
Task	O
scheduling	O
is	O
an	O
important	O
activity	O
in	O
any	O
computer	O
system	O
with	O
multiple	O
processes	B-Operating_System
or	O
threads	B-Operating_System
sharing	O
a	O
single	O
processor	O
core	O
.	O
</s>
<s>
It	O
is	O
important	O
to	O
reduce	O
and	O
increase	O
for	O
embedded	B-Application
software	I-Application
running	O
on	O
an	O
SoC	O
's	O
.	O
</s>
<s>
Not	O
every	O
important	O
computing	O
activity	O
in	O
a	O
SoC	O
is	O
performed	O
in	O
software	O
running	O
on	O
on-chip	O
processors	O
,	O
but	O
scheduling	O
can	O
drastically	O
improve	O
performance	O
of	O
software-based	O
tasks	B-General_Concept
and	O
other	O
tasks	B-General_Concept
involving	O
shared	B-General_Concept
resources	I-General_Concept
.	O
</s>
<s>
SoCs	O
often	O
schedule	O
tasks	B-General_Concept
according	O
to	O
network	B-Application
scheduling	I-Application
and	O
randomized	B-Algorithm
scheduling	I-Algorithm
algorithms	O
.	O
</s>
<s>
Hardware	O
and	O
software	O
tasks	B-General_Concept
are	O
often	O
pipelined	O
in	O
processor	B-General_Concept
design	I-General_Concept
.	O
</s>
<s>
Pipelining	O
is	O
an	O
important	O
principle	O
for	O
speedup	B-Operating_System
in	O
computer	B-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
They	O
are	O
frequently	O
used	O
in	O
GPUs	B-Architecture
(	O
graphics	B-General_Concept
pipeline	I-General_Concept
)	O
and	O
RISC	B-Architecture
processors	I-Architecture
(	O
evolutions	O
of	O
the	O
classic	B-General_Concept
RISC	I-General_Concept
pipeline	I-General_Concept
)	O
,	O
but	O
are	O
also	O
applied	O
to	O
application-specific	O
tasks	B-General_Concept
such	O
as	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
and	O
multimedia	O
manipulations	O
in	O
the	O
context	O
of	O
SoCs	O
.	O
</s>
<s>
For	O
instance	O
,	O
Little	O
's	O
law	O
allows	O
SoC	O
states	O
and	O
NoC	B-Architecture
buffers	O
to	O
be	O
modeled	O
as	O
arrival	O
processes	B-Operating_System
and	O
analyzed	O
through	O
Poisson	O
random	O
variables	O
and	O
Poisson	O
processes	B-Operating_System
.	O
</s>
<s>
SoC	O
chips	O
are	O
typically	O
fabricated	B-Architecture
using	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
(	O
MOS	O
)	O
technology	O
.	O
</s>
<s>
When	O
all	O
known	O
bugs	B-Error_Name
have	O
been	O
rectified	O
and	O
these	O
have	O
been	O
re-verified	O
and	O
all	O
physical	O
design	O
checks	O
are	O
done	O
,	O
the	O
physical	O
design	O
files	O
describing	O
each	O
layer	O
of	O
the	O
chip	O
are	O
sent	O
to	O
the	O
foundry	B-Algorithm
's	O
mask	O
shop	O
where	O
a	O
full	O
set	O
of	O
glass	O
lithographic	O
masks	O
will	O
be	O
etched	O
.	O
</s>
<s>
These	O
are	O
sent	O
to	O
a	O
wafer	B-Architecture
fabrication	B-Algorithm
plant	I-Algorithm
to	O
create	O
the	O
SoC	O
dice	O
before	O
packaging	O
and	O
testing	O
.	O
</s>
<s>
SoCs	O
can	O
be	O
fabricated	B-Architecture
by	O
several	O
technologies	O
,	O
including	O
:	O
</s>
<s>
ASICs	O
consume	O
less	O
power	O
and	O
are	O
faster	O
than	O
FPGAs	B-Architecture
but	O
cannot	O
be	O
reprogrammed	O
and	O
are	O
expensive	O
to	O
manufacture	O
.	O
</s>
<s>
FPGA	B-Architecture
designs	O
are	O
more	O
suitable	O
for	O
lower	O
volume	O
designs	O
,	O
but	O
after	O
enough	O
units	O
of	O
production	O
ASICs	O
reduce	O
the	O
total	O
cost	O
of	O
ownership	O
.	O
</s>
<s>
SoC	O
designs	O
consume	O
less	O
power	O
and	O
have	O
a	O
lower	O
cost	O
and	O
higher	O
reliability	B-Algorithm
than	O
the	O
multi-chip	O
systems	O
that	O
they	O
replace	O
.	O
</s>
<s>
When	O
it	O
is	O
not	O
feasible	O
to	O
construct	O
an	O
SoC	O
for	O
a	O
particular	O
application	O
,	O
an	O
alternative	O
is	O
a	O
system	B-Algorithm
in	I-Algorithm
package	I-Algorithm
(	O
SiP	O
)	O
comprising	O
a	O
number	O
of	O
chips	O
in	O
a	O
single	O
package	B-Algorithm
.	O
</s>
<s>
Another	O
reason	O
SiP	O
may	O
be	O
preferred	O
is	O
waste	O
heat	O
may	O
be	O
too	O
high	O
in	O
a	O
SoC	O
for	O
a	O
given	O
purpose	O
because	O
functional	O
components	O
are	O
too	O
close	O
together	O
,	O
and	O
in	O
an	O
SiP	O
heat	O
will	O
dissipate	O
better	O
from	O
different	O
functional	O
modules	B-Architecture
since	O
they	O
are	O
physically	O
further	O
apart	O
.	O
</s>
