<s>
A	O
system	B-Architecture
bus	I-Architecture
is	O
a	O
single	O
computer	B-General_Concept
bus	I-General_Concept
that	O
connects	O
the	O
major	O
components	O
of	O
a	O
computer	O
system	O
,	O
</s>
<s>
combining	O
the	O
functions	O
of	O
a	O
data	B-General_Concept
bus	I-General_Concept
to	O
carry	O
information	O
,	O
an	O
address	B-Architecture
bus	I-Architecture
to	O
determine	O
where	O
it	O
should	O
be	O
sent	O
or	O
read	O
from	O
,	O
and	O
a	O
control	B-Architecture
bus	I-Architecture
to	O
determine	O
its	O
operation	O
.	O
</s>
<s>
The	O
system	O
level	O
bus	O
(	O
as	O
distinct	O
from	O
a	O
CPU	O
's	O
internal	O
datapath	B-General_Concept
busses	O
)	O
connects	O
the	O
CPU	O
to	O
memory	B-General_Concept
and	O
I/O	B-General_Concept
devices	I-General_Concept
.	O
</s>
<s>
Typically	O
a	O
system	O
level	O
bus	O
is	O
designed	O
for	O
use	O
as	O
a	O
backplane	B-Architecture
.	O
</s>
<s>
In	O
what	O
became	O
known	O
as	O
the	O
Von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
,	O
a	O
central	O
control	B-General_Concept
unit	I-General_Concept
and	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
,	O
which	O
he	O
called	O
the	O
central	O
arithmetic	O
part	O
)	O
were	O
combined	O
with	O
computer	B-General_Concept
memory	I-General_Concept
and	O
input	B-General_Concept
and	I-General_Concept
output	I-General_Concept
functions	O
to	O
form	O
a	O
stored	O
program	O
computer	O
.	O
</s>
<s>
Soon	O
designs	O
integrated	O
the	O
control	B-General_Concept
unit	I-General_Concept
and	O
ALU	O
into	O
what	O
became	O
known	O
as	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
CPU	O
,	O
memory	B-General_Concept
,	O
and	O
input/output	B-General_Concept
units	O
were	O
each	O
one	O
or	O
more	O
cabinets	O
connected	O
by	O
cables	O
.	O
</s>
<s>
Engineers	O
used	O
the	O
common	O
techniques	O
of	O
standardized	O
bundles	O
of	O
wires	O
and	O
extended	O
the	O
concept	O
as	O
backplanes	B-Architecture
were	O
used	O
to	O
hold	O
printed	O
circuit	O
boards	O
in	O
these	O
early	O
machines	O
.	O
</s>
<s>
To	O
provide	O
even	O
more	O
modularity	O
with	O
reduced	O
cost	O
,	O
memory	B-General_Concept
and	O
I/O	B-General_Concept
buses	O
(	O
and	O
the	O
required	O
control	B-Architecture
and	O
power	O
buses	O
)	O
were	O
sometimes	O
combined	O
into	O
a	O
single	O
unified	O
system	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
Digital	O
Equipment	O
Corporation	O
(	O
DEC	O
)	O
further	O
reduced	O
cost	O
for	O
mass-produced	O
minicomputers	B-Architecture
,	O
and	O
memory-mapped	B-Architecture
I/O	I-Architecture
into	O
the	O
memory	B-General_Concept
bus	O
,	O
so	O
that	O
the	O
devices	O
appeared	O
to	O
be	O
memory	B-General_Concept
locations	O
.	O
</s>
<s>
This	O
was	O
implemented	O
in	O
the	O
Unibus	B-Device
of	O
the	O
PDP-11	B-Device
around	O
1969	O
,	O
eliminating	O
the	O
need	O
for	O
a	O
separate	O
I/O	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
Even	O
computers	O
such	O
as	O
the	O
PDP-8	B-Device
without	O
memory-mapped	B-Architecture
I/O	I-Architecture
were	O
soon	O
implemented	O
with	O
a	O
system	B-Architecture
bus	I-Architecture
,	O
which	O
allowed	O
modules	O
to	O
be	O
plugged	O
into	O
any	O
slot	O
.	O
</s>
<s>
Many	O
early	O
microcomputers	O
(	O
with	O
a	O
CPU	O
generally	O
on	O
a	O
single	O
integrated	O
circuit	O
)	O
were	O
built	O
with	O
a	O
single	O
system	B-Architecture
bus	I-Architecture
,	O
starting	O
with	O
the	O
S-100	B-Architecture
bus	I-Architecture
in	O
the	O
Altair	B-Architecture
8800	I-Architecture
computer	O
system	O
in	O
about	O
1975	O
.	O
</s>
<s>
The	O
IBM	B-Device
PC	I-Device
used	O
the	O
Industry	B-Architecture
Standard	I-Architecture
Architecture	I-Architecture
(	O
ISA	O
)	O
bus	O
as	O
its	O
system	B-Architecture
bus	I-Architecture
in	O
1981	O
.	O
</s>
<s>
The	O
passive	B-Architecture
backplanes	I-Architecture
of	O
early	O
models	O
were	O
replaced	O
with	O
the	O
standard	O
of	O
putting	O
the	O
CPU	O
and	O
RAM	O
on	O
a	O
motherboard	B-Device
,	O
with	O
only	O
optional	O
daughterboards	O
or	O
expansion	B-Device
cards	I-Device
in	O
system	B-Architecture
bus	I-Architecture
slots	O
.	O
</s>
<s>
The	O
Multibus	B-Protocol
became	O
a	O
standard	O
of	O
the	O
Institute	O
of	O
Electrical	O
and	O
Electronics	O
Engineers	O
as	O
IEEE	O
standard	O
796	O
in	O
1983	O
.	O
</s>
<s>
Sun	O
Microsystems	O
developed	O
the	O
SBus	B-Architecture
in	O
1989	O
to	O
support	O
smaller	O
expansion	B-Device
cards	I-Device
.	O
</s>
<s>
The	O
easiest	O
way	O
to	O
implement	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
was	O
to	O
plug	O
in	O
more	O
than	O
one	O
CPU	O
into	O
the	O
shared	O
system	B-Architecture
bus	I-Architecture
,	O
which	O
was	O
used	O
through	O
the	O
1980s	O
.	O
</s>
<s>
Even	O
in	O
very	O
simple	O
systems	O
,	O
at	O
various	O
times	O
the	O
data	B-General_Concept
bus	I-General_Concept
is	O
driven	O
by	O
the	O
program	O
memory	B-General_Concept
,	O
by	O
RAM	O
,	O
and	O
by	O
I/O	B-General_Concept
devices	I-General_Concept
.	O
</s>
<s>
To	O
prevent	O
bus	B-Architecture
contention	I-Architecture
on	O
the	O
data	B-General_Concept
bus	I-General_Concept
,	O
at	O
any	O
one	O
instant	O
only	O
one	O
device	O
drives	O
the	O
data	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
In	O
very	O
simple	O
systems	O
,	O
only	O
the	O
data	B-General_Concept
bus	I-General_Concept
is	O
required	O
to	O
be	O
a	O
bidirectional	O
bus	O
.	O
</s>
<s>
In	O
very	O
simple	O
systems	O
,	O
the	O
memory	B-General_Concept
address	I-General_Concept
register	I-General_Concept
always	O
drives	O
the	O
address	B-Architecture
bus	I-Architecture
,	O
the	O
control	B-General_Concept
unit	I-General_Concept
always	O
drives	O
the	O
control	B-Architecture
bus	I-Architecture
,	O
</s>
<s>
and	O
an	O
address	B-Device
decoder	I-Device
selects	O
which	O
particular	O
device	O
is	O
allowed	O
to	O
drive	O
the	O
data	B-General_Concept
bus	I-General_Concept
during	O
this	O
bus	O
cycle	O
.	O
</s>
<s>
In	O
very	O
simple	O
systems	O
,	O
every	O
instruction	B-General_Concept
cycle	I-General_Concept
starts	O
with	O
a	O
READ	O
memory	B-General_Concept
cycle	O
where	O
program	O
memory	B-General_Concept
drives	O
the	O
instruction	O
onto	O
the	O
data	B-General_Concept
bus	I-General_Concept
while	O
the	O
instruction	B-General_Concept
register	I-General_Concept
latches	O
that	O
instruction	O
from	O
the	O
data	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
Some	O
instructions	O
continue	O
with	O
a	O
WRITE	O
memory	B-General_Concept
cycle	O
where	O
the	O
memory	B-General_Concept
data	I-General_Concept
register	I-General_Concept
drives	O
data	O
onto	O
the	O
data	B-General_Concept
bus	I-General_Concept
into	O
the	O
chosen	O
RAM	O
or	O
I/O	B-General_Concept
device	I-General_Concept
.	O
</s>
<s>
Other	O
instructions	O
continue	O
with	O
another	O
READ	O
memory	B-General_Concept
cycle	O
where	O
the	O
chosen	O
RAM	O
,	O
program	O
memory	B-General_Concept
,	O
or	O
I/O	B-General_Concept
device	I-General_Concept
drives	O
data	O
onto	O
the	O
data	B-General_Concept
bus	I-General_Concept
while	O
the	O
memory	B-General_Concept
data	I-General_Concept
register	I-General_Concept
latches	O
that	O
data	O
from	O
the	O
data	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
More	O
complex	O
systems	O
have	O
a	O
multi-master	B-Architecture
bus	I-Architecture
—	O
not	O
only	O
do	O
they	O
have	O
many	O
devices	O
that	O
each	O
drive	O
the	O
data	B-General_Concept
bus	I-General_Concept
,	O
but	O
also	O
have	O
many	O
bus	B-Architecture
masters	I-Architecture
that	O
each	O
drive	O
the	O
address	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
The	O
address	B-Architecture
bus	I-Architecture
as	O
well	O
as	O
the	O
data	B-General_Concept
bus	I-General_Concept
in	O
bus	B-General_Concept
snooping	I-General_Concept
systems	O
is	O
required	O
to	O
be	O
a	O
bidirectional	O
bus	O
,	O
often	O
implemented	O
as	O
a	O
three-state	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
To	O
prevent	O
bus	B-Architecture
contention	I-Architecture
on	O
the	O
address	B-Architecture
bus	I-Architecture
,	O
a	O
bus	B-Architecture
arbiter	I-Architecture
selects	O
which	O
particular	O
bus	B-Architecture
master	I-Architecture
is	O
allowed	O
to	O
drive	O
the	O
address	B-Architecture
bus	I-Architecture
during	O
this	O
bus	O
cycle	O
.	O
</s>
<s>
The	O
first	O
one	O
came	O
when	O
Intel	O
changed	O
from	O
a	O
single	O
local	B-Architecture
bus	I-Architecture
to	O
the	O
DIB	O
,	O
using	O
the	O
external	O
front-side	B-Architecture
bus	I-Architecture
to	O
the	O
main	O
system	O
memory	B-General_Concept
and	O
I/O	B-General_Concept
devices	I-General_Concept
,	O
and	O
the	O
internal	O
back-side	B-Architecture
bus	I-Architecture
to	O
the	O
L2	O
CPU	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
This	O
was	O
introduced	O
in	O
the	O
Pentium	B-Device
Pro	I-Device
in	O
1995	O
.	O
</s>
<s>
However	O
,	O
the	O
information	O
needed	O
to	O
guarantee	O
the	O
cache	B-General_Concept
coherence	I-General_Concept
of	O
shared	O
data	O
located	O
in	O
different	O
caches	O
have	O
to	O
be	O
sent	O
in	O
broadcast	O
(	O
snooped	O
)	O
to	O
check	O
the	O
other	O
FSB	O
's	O
CPUs	O
 '	O
cache	O
state	O
,	O
reducing	O
the	O
available	O
bandwidth	O
.	O
</s>
<s>
To	O
reduce	O
the	O
coherency	B-General_Concept
traffic	I-General_Concept
,	O
a	O
snoop	B-General_Concept
filter	I-General_Concept
was	O
included	O
in	O
the	O
higher-end	O
chipsets	O
,	O
in	O
order	O
to	O
have	O
cache	O
state	O
information	O
available	O
on-chipset	O
.	O
</s>
<s>
In	O
2007	O
Intel	O
extended	O
the	O
idea	O
of	O
multiple	O
buses	O
in	O
the	O
7300	O
chipset	O
with	O
four	O
independent	O
FSBs	O
,	O
calling	O
it	O
dedicated	O
high-speed	O
interconnects	B-General_Concept
(	O
DHSI	O
)	O
.	O
</s>
<s>
The	O
system	B-Architecture
bus	I-Architecture
approach	O
is	O
obsolete	O
in	O
the	O
modern	O
personal	O
and	O
server	O
computers	O
,	O
which	O
instead	O
use	O
higher-performance	O
interconnection	O
technologies	O
such	O
as	O
HyperTransport	B-Device
and	O
Intel	B-Architecture
QuickPath	I-Architecture
Interconnect	I-Architecture
,	O
while	O
the	O
system	B-Architecture
bus	I-Architecture
architecture	O
continued	O
to	O
be	O
used	O
on	O
simpler	O
embedded	O
microprocessors	O
.	O
</s>
<s>
The	O
systems	O
bus	O
can	O
even	O
be	O
internal	O
to	O
a	O
single	O
integrated	O
circuit	O
,	O
producing	O
a	O
system-on-a-chip	B-Architecture
.	O
</s>
<s>
Examples	O
include	O
AMBA	B-Architecture
,	O
CoreConnect	B-Architecture
,	O
and	O
Wishbone	B-Architecture
.	O
</s>
