<s>
SystemVerilog	B-Language
,	O
standardized	O
as	O
IEEE	B-Language
1800	I-Language
,	O
is	O
a	O
hardware	O
description	O
and	O
hardware	B-Language
verification	I-Language
language	I-Language
used	O
to	O
model	O
,	O
design	B-General_Concept
,	O
simulate	O
,	O
test	O
and	O
implement	O
electronic	O
systems	O
.	O
</s>
<s>
SystemVerilog	B-Language
is	O
based	O
on	O
Verilog	B-Language
and	O
some	O
extensions	O
,	O
and	O
since	O
2008	O
,	O
Verilog	B-Language
is	O
now	O
part	O
of	O
the	O
same	O
IEEE	O
standard	O
.	O
</s>
<s>
It	O
is	O
commonly	O
used	O
in	O
the	O
semiconductor	O
and	O
electronic	O
design	B-General_Concept
industry	O
as	O
an	O
evolution	O
of	O
Verilog	B-Language
.	O
</s>
<s>
SystemVerilog	B-Language
started	O
with	O
the	O
donation	O
of	O
the	O
Superlog	O
language	O
to	O
Accellera	O
in	O
2002	O
by	O
the	O
startup	O
company	O
Co-Design	O
Automation	O
.	O
</s>
<s>
The	O
bulk	O
of	O
the	O
verification	O
functionality	O
is	O
based	O
on	O
the	O
OpenVera	B-Language
language	O
donated	O
by	O
Synopsys	O
.	O
</s>
<s>
In	O
2005	O
,	O
SystemVerilog	B-Language
was	O
adopted	O
as	O
IEEE	O
Standard	O
1800-2005	O
.	O
</s>
<s>
In	O
2009	O
,	O
the	O
standard	O
was	O
merged	O
with	O
the	O
base	O
Verilog	B-Language
(	O
IEEE	O
1364-2005	O
)	O
standard	O
,	O
creating	O
IEEE	O
Standard	O
1800-2009	O
.	O
</s>
<s>
The	O
feature-set	O
of	O
SystemVerilog	B-Language
can	O
be	O
divided	O
into	O
two	O
distinct	O
roles	O
:	O
</s>
<s>
SystemVerilog	B-Language
for	O
register-transfer	O
level	O
(	O
RTL	O
)	O
design	B-General_Concept
is	O
an	O
extension	O
of	O
Verilog-2005	B-Language
;	O
all	O
features	O
of	O
that	O
language	O
are	O
available	O
in	O
SystemVerilog	B-Language
.	O
</s>
<s>
Therefore	O
,	O
Verilog	B-Language
is	O
a	O
subset	O
of	O
SystemVerilog	B-Language
.	O
</s>
<s>
SystemVerilog	B-Language
for	O
verification	O
uses	O
extensive	O
object-oriented	B-Language
programming	I-Language
techniques	O
and	O
is	O
more	O
closely	O
related	O
to	O
Java	B-Language
than	O
Verilog	B-Language
.	O
</s>
<s>
The	O
remainder	O
of	O
this	O
article	O
discusses	O
the	O
features	O
of	O
SystemVerilog	B-Language
not	O
present	O
in	O
Verilog-2005	B-Language
.	O
</s>
<s>
There	O
are	O
two	O
types	O
of	O
data	O
lifetime	O
specified	O
in	O
SystemVerilog	B-Language
:	O
static	B-General_Concept
and	O
automatic	O
.	O
</s>
<s>
Static	B-General_Concept
variables	I-General_Concept
are	O
created	O
at	O
the	O
start	O
of	O
the	O
program	O
's	O
execution	O
and	O
keep	O
the	O
same	O
value	O
during	O
the	O
entire	O
program	O
's	O
lifespan	O
,	O
unless	O
assigned	O
a	O
new	O
value	O
during	O
execution	O
.	O
</s>
<s>
To	O
specify	O
that	O
a	O
variable	O
is	O
static	B-General_Concept
place	O
the	O
"	O
static	B-General_Concept
"	O
keyword	O
in	O
the	O
declaration	O
before	O
the	O
type	O
,	O
e.g.	O
,	O
"	O
static	B-General_Concept
int	O
x	O
;	O
"	O
.	O
</s>
<s>
Enhanced	O
variable	O
types	O
add	O
new	O
capability	O
to	O
Verilog	B-Language
's	O
"	O
reg	O
"	O
type	O
:	O
</s>
<s>
Verilog-1995	O
and	O
-2001	O
limit	O
reg	O
variables	O
to	O
behavioral	O
statements	O
such	O
as	O
RTL	O
code	O
.	O
</s>
<s>
SystemVerilog	B-Language
extends	O
the	O
reg	O
type	O
so	O
it	O
can	O
be	O
driven	O
by	O
a	O
single	O
driver	O
such	O
as	O
gate	O
or	O
module	O
.	O
</s>
<s>
SystemVerilog	B-Language
names	O
this	O
type	O
"	O
logic	O
"	O
to	O
remind	O
users	O
that	O
it	O
has	O
this	O
extra	O
capability	O
and	O
is	O
not	O
a	O
hardware	O
register	O
.	O
</s>
<s>
A	O
signal	O
with	O
more	O
than	O
one	O
driver	O
(	O
such	O
as	O
a	O
tri-state	O
buffer	O
for	O
general-purpose	B-Architecture
input/output	I-Architecture
)	O
needs	O
to	O
be	O
declared	O
a	O
net	O
type	O
such	O
as	O
"	O
wire	O
"	O
so	O
SystemVerilog	B-Language
can	O
resolve	O
the	O
final	O
value	O
.	O
</s>
<s>
Multidimensional	O
packed	B-Application
arrays	I-Application
unify	O
and	O
extend	O
Verilog	B-Language
's	O
notion	O
of	O
"	O
registers	O
"	O
and	O
"	O
memories	O
"	O
:	O
</s>
<s>
Classical	O
Verilog	B-Language
permitted	O
only	O
one	O
dimension	O
to	O
be	O
declared	O
to	O
the	O
left	O
of	O
the	O
variable	O
name	O
.	O
</s>
<s>
SystemVerilog	B-Language
permits	O
any	O
number	O
of	O
such	O
"	O
packed	O
"	O
dimensions	O
.	O
</s>
<s>
A	O
variable	O
of	O
packed	B-Application
array	I-Application
type	O
maps	O
1:1	O
onto	O
an	O
integer	O
arithmetic	O
quantity	O
.	O
</s>
<s>
As	O
in	O
Verilog-2001	B-Language
,	O
any	O
number	O
of	O
unpacked	O
dimensions	O
is	O
permitted	O
.	O
</s>
<s>
Enumerated	B-Language
data	I-Language
types	I-Language
(	O
enums	B-Language
)	O
allow	O
numeric	O
quantities	O
to	O
be	O
assigned	O
meaningful	O
names	O
.	O
</s>
<s>
Variables	O
declared	O
to	O
be	O
of	O
enumerated	B-Language
type	I-Language
cannot	O
be	O
assigned	O
to	O
variables	O
of	O
a	O
different	O
enumerated	B-Language
type	I-Language
without	O
casting	O
.	O
</s>
<s>
This	O
is	O
not	O
true	O
of	O
parameters	O
,	O
which	O
were	O
the	O
preferred	O
implementation	O
technique	O
for	O
enumerated	O
quantities	O
in	O
Verilog-2005	B-Language
:	O
</s>
<s>
As	O
shown	O
above	O
,	O
the	O
designer	O
can	O
specify	O
an	O
underlying	O
arithmetic	O
type	O
(	O
logic	O
 [ 2:0 ] 	O
in	O
this	O
case	O
)	O
which	O
is	O
used	O
to	O
represent	O
the	O
enumeration	B-Language
value	O
.	O
</s>
<s>
The	O
built-in	O
function	O
name( )	O
returns	B-Language
an	O
ASCII	O
string	O
for	O
the	O
current	O
enumerated	O
value	O
,	O
which	O
is	O
useful	O
in	O
validation	O
and	O
testing	O
.	O
</s>
<s>
New	O
integer	O
types	O
:	O
SystemVerilog	B-Language
defines	O
byte	O
,	O
shortint	O
,	O
int	O
and	O
longint	O
as	O
two-state	O
signed	O
integral	O
types	O
having	O
8	O
,	O
16	O
,	O
32	O
,	O
and	O
64	O
bits	O
respectively	O
.	O
</s>
<s>
Two-state	O
types	O
lack	O
the	O
X	O
and	O
Z	O
metavalues	O
of	O
classical	O
Verilog	B-Language
;	O
working	O
with	O
these	O
types	O
may	O
result	O
in	O
faster	O
simulation	O
.	O
</s>
<s>
Structures	O
and	O
unions	O
work	O
much	O
like	O
they	O
do	O
in	O
the	O
C	B-Language
programming	I-Language
language	I-Language
.	O
</s>
<s>
SystemVerilog	B-Language
enhancements	O
include	O
the	O
packed	O
attribute	O
and	O
the	O
tagged	O
attribute	O
.	O
</s>
<s>
The	O
tagged	O
attribute	O
allows	O
runtime	B-Library
tracking	O
of	O
which	O
member(s )	O
of	O
a	O
union	O
are	O
currently	O
in	O
use	O
.	O
</s>
<s>
The	O
packed	O
attribute	O
causes	O
the	O
structure	O
or	O
union	O
to	O
be	O
mapped	O
1:1	O
onto	O
a	O
packed	B-Application
array	I-Application
of	O
bits	O
.	O
</s>
<s>
The	O
contents	O
of	O
struct	B-Language
data	O
types	O
occupy	O
a	O
continuous	O
block	O
of	O
memory	O
with	O
no	O
gaps	O
,	O
similar	O
to	O
bitfields	O
in	O
C	B-Language
and	O
C++	B-Language
:	O
</s>
<s>
As	O
shown	O
in	O
this	O
example	O
,	O
SystemVerilog	B-Language
also	O
supports	O
typedefs	B-Language
,	O
as	O
in	O
C	B-Language
and	O
C++	B-Language
.	O
</s>
<s>
SystemVerilog	B-Language
introduces	O
three	O
new	O
procedural	O
blocks	O
intended	O
to	O
model	O
hardware	O
:	O
always_comb	O
(	O
to	O
model	O
combinational	O
logic	O
)	O
,	O
always_ff	O
(	O
for	O
flip-flops	B-General_Concept
)	O
,	O
and	O
always_latch	O
(	O
for	O
latches	B-General_Concept
)	O
.	O
</s>
<s>
Whereas	O
Verilog	B-Language
used	O
a	O
single	O
,	O
general-purpose	O
always	O
block	O
to	O
model	O
different	O
types	O
of	O
hardware	O
structures	O
,	O
each	O
of	O
SystemVerilog	B-Language
's	O
new	O
blocks	O
is	O
intended	O
to	O
model	O
a	O
specific	O
type	O
of	O
hardware	O
,	O
by	O
imposing	O
semantic	O
restrictions	O
to	O
ensure	O
that	O
hardware	O
described	O
by	O
the	O
blocks	O
matches	O
the	O
intended	O
usage	O
of	O
the	O
model	O
.	O
</s>
<s>
An	O
always_latch	O
block	O
models	O
level-sensitive	O
latches	B-General_Concept
.	O
</s>
<s>
An	O
always_ff	O
block	O
models	O
synchronous	B-Application
logic	I-Application
(	O
especially	O
edge-sensitive	O
sequential	O
logic	O
)	O
:	O
</s>
<s>
Electronic	O
design	B-General_Concept
automation	O
(	O
EDA	O
)	O
tools	O
can	O
verify	O
the	O
design	B-General_Concept
's	O
intent	O
by	O
checking	O
that	O
the	O
hardware	O
model	O
does	O
not	O
violate	O
any	O
block	O
usage	O
semantics	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
new	O
blocks	O
restrict	O
assignment	O
to	O
a	O
variable	O
by	O
allowing	O
only	O
one	O
source	O
,	O
whereas	O
Verilog	B-Language
's	O
always	O
block	O
permitted	O
assignment	O
from	O
multiple	O
procedural	O
sources	O
.	O
</s>
<s>
For	O
small	O
designs	O
,	O
the	O
Verilog	B-Language
port	O
compactly	O
describes	O
a	O
module	O
's	O
connectivity	O
with	O
the	O
surrounding	O
environment	O
.	O
</s>
<s>
But	O
major	O
blocks	O
within	O
a	O
large	O
design	B-General_Concept
hierarchy	O
typically	O
possess	O
port	O
counts	O
in	O
the	O
thousands	O
.	O
</s>
<s>
SystemVerilog	B-Language
introduces	O
concept	O
of	O
interfaces	B-Application
to	O
both	O
reduce	O
the	O
redundancy	O
of	O
port-name	B-Application
declarations	I-Application
between	O
connected	O
modules	O
,	O
as	O
well	O
as	O
group	O
and	O
abstract	O
related	O
signals	O
into	O
a	O
user-declared	O
bundle	O
.	O
</s>
<s>
In	O
addition	O
to	O
the	O
static	B-General_Concept
array	O
used	O
in	O
design	B-General_Concept
,	O
SystemVerilog	B-Language
offers	O
dynamic	B-Data_Structure
arrays	I-Data_Structure
,	O
associative	B-Application
arrays	I-Application
and	O
queues	B-Application
:	O
</s>
<s>
A	O
dynamic	B-Data_Structure
array	I-Data_Structure
works	O
much	O
like	O
an	O
unpacked	O
array	O
,	O
but	O
offers	O
the	O
advantage	O
of	O
being	O
dynamically	O
allocated	O
at	B-Library
runtime	I-Library
(	O
as	O
shown	O
above	O
.	O
)	O
</s>
<s>
Whereas	O
a	O
packed	B-Application
array	I-Application
's	O
size	O
must	O
be	O
known	O
at	O
compile	O
time	O
(	O
from	O
a	O
constant	O
or	O
expression	O
of	O
constants	O
)	O
,	O
the	O
dynamic	B-Data_Structure
array	I-Data_Structure
size	O
can	O
be	O
initialized	O
from	O
another	O
runtime	B-Library
variable	O
,	O
allowing	O
the	O
array	O
to	O
be	O
sized	O
and	O
resize	O
arbitrarily	O
as	O
needed	O
.	O
</s>
<s>
An	O
associative	B-Application
array	I-Application
can	O
be	O
thought	O
of	O
as	O
a	O
binary	B-Language
search	I-Language
tree	I-Language
with	O
a	O
user-specified	B-Language
key	B-Application
type	I-Application
and	I-Application
data	I-Application
type	I-Application
.	O
</s>
<s>
The	O
key	O
implies	O
an	O
ordering	O
;	O
the	O
elements	O
of	O
an	O
associative	B-Application
array	I-Application
can	O
be	O
read	O
out	O
in	O
lexicographic	O
order	O
.	O
</s>
<s>
Finally	O
,	O
a	O
queue	B-Application
provides	O
much	O
of	O
the	O
functionality	O
of	O
the	O
C++	B-Application
STL	I-Application
deque	B-Application
type	O
:	O
elements	O
can	O
be	O
added	O
and	O
removed	O
from	O
either	O
end	O
efficiently	O
.	O
</s>
<s>
These	O
primitives	O
allow	O
the	O
creation	O
of	O
complex	O
data	O
structures	O
required	O
for	O
scoreboarding	B-General_Concept
a	O
large	O
design	B-General_Concept
.	O
</s>
<s>
SystemVerilog	B-Language
provides	O
an	O
object-oriented	B-Language
programming	I-Language
model	O
.	O
</s>
<s>
In	O
SystemVerilog	B-Language
,	O
classes	O
support	O
a	O
single-inheritance	O
model	O
,	O
but	O
may	O
implement	O
functionality	O
similar	O
to	O
multiple-inheritance	O
through	O
the	O
use	O
of	O
so-called	O
"	O
interface	O
classes	O
"	O
(	O
identical	O
in	O
concept	O
to	O
the	O
interface	O
feature	O
of	O
Java	B-Language
)	O
.	O
</s>
<s>
Classes	O
can	B-Language
be	I-Language
parameterized	I-Language
by	I-Language
type	I-Language
,	O
providing	O
the	O
basic	O
function	O
of	O
C++	B-Application
templates	I-Application
.	O
</s>
<s>
However	O
,	O
template	B-Application
specialization	O
and	O
function	O
templates	B-Application
are	O
not	O
supported	O
.	O
</s>
<s>
SystemVerilog	B-Language
's	O
polymorphism	B-Application
features	O
are	O
similar	O
to	O
those	O
of	O
C++	B-Language
:	O
the	O
programmer	O
may	O
specifically	O
write	O
a	O
virtual	B-Application
function	I-Application
to	O
have	O
a	O
derived	O
class	O
gain	O
control	O
of	O
the	O
function	O
.	O
</s>
<s>
See	O
virtual	B-Application
function	I-Application
for	O
further	O
information	O
.	O
</s>
<s>
Encapsulation	B-Application
and	O
data	B-Application
hiding	I-Application
is	O
accomplished	O
using	O
the	O
local	O
and	O
protected	O
keywords	O
,	O
which	O
must	O
be	O
applied	O
to	O
any	O
item	O
that	O
is	O
to	O
be	O
hidden	O
.	O
</s>
<s>
SystemVerilog	B-Language
has	O
automatic	B-General_Concept
garbage	I-General_Concept
collection	I-General_Concept
,	O
so	O
there	O
is	O
no	O
language	O
facility	O
to	O
explicitly	O
destroy	O
instances	O
created	O
by	O
the	O
new	O
operator	O
.	O
</s>
<s>
randc	O
specifies	O
permutation-based	O
randomization	O
,	O
where	O
a	O
variable	O
will	O
take	O
on	O
all	O
possible	O
values	O
once	O
before	O
any	O
value	O
is	O
repeated	O
.	O
</s>
<s>
The	O
two	O
constraints	O
shown	O
are	O
applicable	O
to	O
conforming	O
Ethernet	B-Protocol
frames	I-Protocol
.	O
</s>
<s>
The	O
SystemVerilog	B-Language
constraint	B-Application
solver	I-Application
is	O
required	O
to	O
find	O
a	O
solution	O
if	O
one	O
exists	O
,	O
but	O
makes	O
no	O
guarantees	O
as	O
to	O
the	O
time	O
it	O
will	O
require	O
to	O
do	O
so	O
as	O
this	O
is	O
in	O
general	O
an	O
NP-hard	O
problem	O
(	O
boolean	B-Algorithm
satisfiability	I-Algorithm
)	O
.	O
</s>
<s>
In	O
each	O
SystemVerilog	B-Language
class	O
there	O
are	O
3	O
predefined	O
methods	O
for	O
randomization	O
:	O
pre_randomize	O
,	O
randomize	O
and	O
post_randomize	O
.	O
</s>
<s>
The	O
below	O
code	O
describes	O
and	O
procedurally	O
tests	O
an	O
Ethernet	B-Protocol
frame	I-Protocol
:	O
</s>
<s>
Assertions	O
are	O
useful	O
for	O
verifying	O
properties	O
of	O
a	O
design	B-General_Concept
that	O
manifest	O
themselves	O
after	O
a	O
specific	O
condition	O
or	O
state	O
is	O
reached	O
.	O
</s>
<s>
SystemVerilog	B-Language
has	O
its	O
own	O
assertion	O
specification	O
language	O
,	O
similar	O
to	O
Property	B-Language
Specification	I-Language
Language	I-Language
.	O
</s>
<s>
The	O
subset	O
of	O
SystemVerilog	B-Language
language	O
constructs	O
that	O
serves	O
assertion	O
is	O
commonly	O
called	O
SystemVerilog	B-Language
Assertion	O
or	O
SVA	O
.	O
</s>
<s>
SystemVerilog	B-Language
assertions	O
are	O
built	O
from	O
sequences	O
and	O
properties	O
.	O
</s>
<s>
Sequences	O
consist	O
of	O
boolean	O
expressions	O
augmented	O
with	O
temporal	B-Application
operators	I-Application
.	O
</s>
<s>
These	O
operators	O
allow	O
the	O
designer	O
to	O
express	O
complex	O
relationships	O
among	O
design	B-General_Concept
components	O
.	O
</s>
<s>
In	O
addition	O
to	O
assertions	O
,	O
SystemVerilog	B-Language
supports	O
assumptions	O
and	O
coverage	O
of	O
properties	O
.	O
</s>
<s>
An	O
assumption	O
establishes	O
a	O
condition	O
that	O
a	O
formal	O
logic	O
proving	B-Application
tool	I-Application
must	B-Algorithm
assume	I-Algorithm
to	I-Algorithm
be	I-Algorithm
true	I-Algorithm
.	O
</s>
<s>
Property	O
coverage	O
allows	O
the	O
verification	O
engineer	O
to	O
verify	O
that	O
assertions	O
are	O
accurately	O
monitoring	O
the	O
design	B-General_Concept
.	O
</s>
<s>
Coverage	O
as	O
applied	O
to	O
hardware	B-Language
verification	I-Language
languages	I-Language
refers	O
to	O
the	O
collection	O
of	O
statistics	O
based	O
on	O
sampling	B-Algorithm
events	O
within	O
the	O
simulation	O
.	O
</s>
<s>
Note	O
that	O
this	O
differs	O
from	O
code	B-Application
coverage	I-Application
which	O
instruments	O
the	O
design	B-General_Concept
code	O
to	O
ensure	O
that	O
all	O
lines	O
of	O
code	O
in	O
the	O
design	B-General_Concept
have	O
been	O
executed	O
.	O
</s>
<s>
Functional	O
coverage	O
ensures	O
that	O
all	O
desired	O
corner	O
and	O
edge	O
cases	O
in	O
the	O
design	B-General_Concept
space	O
have	O
been	O
explored	O
.	O
</s>
<s>
A	O
SystemVerilog	B-Language
coverage	O
group	O
creates	O
a	O
database	O
of	O
"	O
bins	O
"	O
that	O
store	O
a	O
histogram	B-Algorithm
of	O
values	O
of	O
an	O
associated	O
variable	O
.	O
</s>
<s>
Cross-coverage	O
can	O
also	O
be	O
defined	O
,	O
which	O
creates	O
a	O
histogram	B-Algorithm
representing	O
the	O
Cartesian	O
product	O
of	O
multiple	O
variables	O
.	O
</s>
<s>
A	O
sampling	B-Algorithm
event	O
controls	O
when	O
a	O
sample	O
is	O
taken	O
.	O
</s>
<s>
The	O
sampling	B-Algorithm
event	O
can	O
be	O
a	O
Verilog	B-Language
event	O
,	O
the	O
entry	O
or	O
exit	O
of	O
a	O
block	O
of	O
code	O
,	O
or	O
a	O
call	O
to	O
the	O
sample	O
method	O
of	O
the	O
coverage	O
group	O
.	O
</s>
<s>
Verilog	B-Language
's	O
'	O
event	O
 '	O
primitive	O
allowed	O
different	O
blocks	O
of	O
procedural	O
statements	O
to	O
trigger	O
each	O
other	O
,	O
but	O
enforcing	O
thread	O
synchronization	O
was	O
up	O
to	O
the	O
programmer	O
's	O
(	O
clever	O
)	O
usage	O
.	O
</s>
<s>
SystemVerilog	B-Language
offers	O
two	O
primitives	O
specifically	O
for	O
interthread	O
synchronization	O
:	O
mailbox	B-Operating_System
and	O
semaphore	B-Operating_System
.	O
</s>
<s>
The	O
mailbox	B-Operating_System
is	O
modeled	O
as	O
a	O
FIFO	B-Operating_System
message	B-Operating_System
queue	I-Operating_System
.	O
</s>
<s>
Optionally	O
,	O
the	O
FIFO	B-Operating_System
can	O
be	O
type-parameterized	B-Language
so	O
that	O
only	O
objects	O
of	O
the	O
specified	O
type	O
may	O
be	O
passed	O
through	O
it	O
.	O
</s>
<s>
Typically	O
,	O
objects	O
are	O
class	O
instances	O
representing	O
transactions	B-Application
:	O
elementary	O
operations	O
(	O
for	O
example	O
,	O
sending	O
a	O
frame	O
)	O
that	O
are	O
executed	O
by	O
the	O
verification	O
components	O
.	O
</s>
<s>
The	O
semaphore	B-Operating_System
is	O
modeled	O
as	O
a	O
counting	B-Operating_System
semaphore	I-Operating_System
.	O
</s>
<s>
In	O
addition	O
to	O
the	O
new	O
features	O
above	O
,	O
SystemVerilog	B-Language
enhances	O
the	O
usability	O
of	O
Verilog	B-Language
's	O
existing	O
language	O
features	O
.	O
</s>
<s>
The	O
procedural	O
assignment	O
operators	O
(<=	O
,	O
=	O
)	O
can	O
now	O
operate	O
directly	B-Application
on	I-Application
arrays	I-Application
.	O
</s>
<s>
Port	O
(	O
inout	O
,	O
input	O
,	O
output	O
)	O
definitions	O
are	O
now	O
expanded	O
to	O
support	O
a	O
wider	O
variety	O
of	O
data	O
types	O
:	O
struct	B-Language
,	O
enum	B-Language
,	O
real	O
,	O
and	O
multi-dimensional	O
types	O
are	O
supported	O
.	O
</s>
<s>
The	O
for	B-Language
loop	I-Language
construct	O
now	O
allows	O
automatic	O
variable	O
declaration	O
inside	O
the	O
for	B-Language
statement	I-Language
.	O
</s>
<s>
SystemVerilog	B-Language
adds	O
a	O
do/while	O
loop	O
to	O
the	O
while	O
loop	O
construct	O
.	O
</s>
<s>
Constant	O
variables	O
,	O
i.e.	O
</s>
<s>
those	O
designated	O
as	O
non-changing	O
during	O
runtime	B-Library
,	O
can	O
be	O
designated	O
by	O
use	O
of	O
const	O
.	O
</s>
<s>
Increment	O
and	O
decrement	O
operators	O
(	O
x++	O
,	O
++x	O
,	O
x--	O
,	O
--x	O
)	O
are	O
supported	O
in	O
SystemVerilog	B-Language
,	O
as	O
are	O
other	O
compound	O
assignment	O
operators	O
(	O
x	O
+	O
=	O
a	O
,	O
x	O
-	O
=	O
a	O
,	O
x	O
*	O
=	O
a	O
,	O
x	O
/	O
=	O
a	O
,	O
x	O
%	O
=	O
a	O
,	O
x	O
<<= a, x >>	O
=	O
a	O
,	O
x	O
&	O
=	O
a	O
,	O
x	O
^	O
=	O
a	O
,	O
x	O
|=	O
a	O
)	O
as	O
in	O
C	B-Language
and	I-Language
descendants	I-Language
.	O
</s>
<s>
The	O
preprocessor	O
has	O
improved	O
`define	B-Language
macro-substitution	O
capabilities	O
,	O
specifically	O
substitution	O
within	O
literal-strings	O
(""	O
)	O
,	O
as	O
well	O
as	O
concatenation	O
of	O
multiple	O
macro-tokens	O
into	O
a	O
single	O
word	O
.	O
</s>
<s>
The	O
fork/join	B-Operating_System
construct	O
has	O
been	O
expanded	O
with	O
join_none	O
and	O
join_any	O
.	O
</s>
<s>
Since	O
it	O
is	O
operating	O
on	O
the	O
original	O
variable	O
itself	O
,	O
rather	O
than	O
a	O
copy	O
of	O
the	O
argument	O
's	O
value	O
,	O
the	O
task/function	O
can	O
modify	O
variables	O
(	O
but	O
not	O
nets	O
)	O
in	O
the	O
caller	O
's	O
scope	O
in	O
real	B-General_Concept
time	I-General_Concept
.	O
</s>
<s>
Functions	O
can	O
now	O
be	O
declared	O
void	O
,	O
which	O
means	O
it	O
returns	B-Language
no	O
value	O
.	O
</s>
<s>
Parameters	O
can	O
be	O
declared	O
any	O
type	O
,	O
including	O
user-defined	O
typedefs	B-Language
.	O
</s>
<s>
Besides	O
this	O
,	O
SystemVerilog	B-Language
allows	O
convenient	O
interface	B-Language
to	I-Language
foreign	I-Language
languages	I-Language
(	O
like	O
C/C	O
++	O
)	O
,	O
by	O
SystemVerilog	B-Language
DPI	I-Language
(	O
Direct	B-Language
Programming	I-Language
Interface	I-Language
)	O
.	O
</s>
<s>
In	O
the	O
design	B-General_Concept
verification	O
role	O
,	O
SystemVerilog	B-Language
is	O
widely	O
used	O
in	O
the	O
chip-design	O
industry	O
.	O
</s>
<s>
The	O
three	O
largest	O
EDA	O
vendors	O
(	O
Cadence	O
Design	B-General_Concept
Systems	O
,	O
Mentor	O
Graphics	O
,	O
Synopsys	O
)	O
have	O
incorporated	O
SystemVerilog	B-Language
into	O
their	O
mixed-language	O
HDL	B-Algorithm
simulators	I-Algorithm
.	O
</s>
<s>
Although	O
no	O
simulator	O
can	O
yet	O
claim	O
support	O
for	O
the	O
entire	O
SystemVerilog	B-Language
Language	O
Reference	O
Manual	O
,	O
making	O
testbench	O
interoperability	O
a	O
challenge	O
,	O
efforts	O
to	O
promote	O
cross-vendor	O
compatibility	O
are	O
underway	O
.	O
</s>
<s>
Synopsys	O
,	O
which	O
had	O
been	O
the	O
first	O
to	O
publish	O
a	O
SystemVerilog	B-Language
class-library	O
(	O
VMM	O
)	O
,	O
subsequently	O
responded	O
by	O
opening	O
its	O
proprietary	O
VMM	O
to	O
the	O
general	O
public	O
.	O
</s>
<s>
Many	O
third-party	O
providers	O
have	O
announced	O
or	O
already	O
released	O
SystemVerilog	B-Language
verification	O
IP	O
.	O
</s>
<s>
In	O
the	O
design	B-General_Concept
synthesis	O
role	O
(	O
transformation	O
of	O
a	O
hardware-design	O
description	O
into	O
a	O
gate-netlist	O
)	O
,	O
SystemVerilog	B-Language
adoption	O
has	O
been	O
slow	O
.	O
</s>
<s>
Many	O
design	B-General_Concept
teams	O
use	O
design	B-General_Concept
flows	O
which	O
involve	O
multiple	O
tools	O
from	O
different	O
vendors	O
.	O
</s>
<s>
Most	O
design	B-General_Concept
teams	O
cannot	O
migrate	O
to	O
SystemVerilog	B-Language
RTL-design	O
until	O
their	O
entire	O
front-end	O
tool	O
suite	O
(	O
linters	B-Device
,	O
formal	O
verification	O
and	O
automated	O
test	O
structure	O
generators	O
)	O
support	O
a	O
common	O
language	O
subset	O
.	O
</s>
