<s>
Synchronous	B-Protocol
Serial	I-Protocol
Interface	I-Protocol
(	O
SSI	O
)	O
is	O
a	O
widely	O
used	O
serial	O
interface	O
standard	O
for	O
industrial	O
applications	O
between	O
a	O
master	B-Operating_System
(	O
e.g.	O
</s>
<s>
controller	O
)	O
and	O
a	O
slave	B-Operating_System
(	O
e.g.	O
</s>
<s>
SSI	O
was	O
originally	O
developed	O
by	O
Max	O
Stegmann	O
GmbH	O
in	O
1984	O
for	O
transmitting	O
the	O
position	O
data	O
of	O
absolute	B-Algorithm
encoders	I-Algorithm
–	O
for	O
this	O
reason	O
,	O
some	O
servo/drive	O
equipment	O
manufacturers	O
refer	O
to	O
their	O
SSI	O
port	O
as	O
a	O
"	O
Stegmann	O
Interface	O
"	O
.	O
</s>
<s>
It	O
is	O
different	O
from	O
the	O
Serial	B-Architecture
Peripheral	I-Architecture
Interface	I-Architecture
Bus	I-Architecture
(	O
SPI	O
)	O
:	O
An	O
SSI	O
bus	O
is	O
differential	O
,	O
simplex	O
,	O
non-multiplexed	O
,	O
and	O
relies	O
on	O
a	O
time-out	O
to	O
frame	O
the	O
data	O
.	O
</s>
<s>
An	O
SPI	B-Architecture
bus	I-Architecture
is	O
single-ended	O
,	O
duplex	O
,	O
and	O
uses	O
a	O
select-line	O
to	O
frame	O
the	O
data	O
.	O
</s>
<s>
However	O
,	O
SPI	O
peripherals	O
on	O
microcontrollers	B-Architecture
can	O
implement	O
SSI	O
with	O
external	O
differential	O
driver-ICs	O
and	O
program-controlled	O
timing	O
.	O
</s>
<s>
In	O
general	O
,	O
as	O
mentioned	O
earlier	O
,	O
it	O
is	O
a	O
point-to-point	O
connection	O
from	O
a	O
master	B-Operating_System
(	O
e.g.	O
,	O
PLC	O
,	O
Microcontroller	B-Architecture
)	O
to	O
a	O
slave	B-Operating_System
(	O
e.g.	O
</s>
<s>
rotary	B-Algorithm
encoders	I-Algorithm
)	O
.	O
</s>
<s>
The	O
master	B-Operating_System
controls	O
the	O
clock	O
sequence	O
,	O
and	O
the	O
slave	B-Operating_System
transmits	O
the	O
current	O
data/value	O
through	O
a	O
shift	O
register	O
.	O
</s>
<s>
When	O
invoked	O
by	O
the	O
master	B-Operating_System
,	O
the	O
data	O
is	O
clocked	O
out	O
from	O
the	O
shift	O
register	O
.	O
</s>
<s>
The	O
master	B-Operating_System
and	O
slave	B-Operating_System
are	O
synchronized	O
by	O
the	O
common	O
clock	O
of	O
the	O
controller	O
.	O
</s>
<s>
It	O
consists	O
of	O
2	O
pairs	O
of	O
wires	O
,	O
one	O
for	O
transmitting	O
the	O
clock	O
signals	O
from	O
the	O
master	B-Operating_System
and	O
the	O
other	O
for	O
transmitting	O
the	O
data	O
from	O
the	O
slave	B-Operating_System
.	O
</s>
<s>
The	O
clock	O
sequences	O
are	O
triggered	O
by	O
the	O
master	B-Operating_System
when	O
the	O
need	O
arises	O
.	O
</s>
<s>
The	O
most	O
straightforward	O
SSI	O
slave	B-Operating_System
interface	O
uses	O
a	O
re-triggerable	O
monostable	O
multivibrator	O
(	O
monoflop	O
)	O
to	O
freeze	O
the	O
current	O
value	O
of	O
the	O
sensor	O
.	O
</s>
<s>
The	O
current	O
frozen	O
values	O
of	O
the	O
slave	B-Operating_System
are	O
stored	O
in	O
Shift	O
registers	O
.	O
</s>
<s>
The	O
design	O
is	O
being	O
revolutionized	O
by	O
integrating	O
microcontrollers	B-Architecture
,	O
FPGAs	O
and	O
ASICs	O
into	O
the	O
interface	O
.	O
</s>
<s>
Readings	O
from	O
multiple	O
slaves	B-Operating_System
(	O
up	O
to	O
three	O
)	O
can	O
be	O
enabled	O
simultaneously	O
by	O
connecting	O
them	O
to	O
a	O
common	O
clock	O
.	O
</s>
<s>
However	O
,	O
to	O
avoid	O
ground	O
loops	O
and	O
electrically	O
isolate	O
the	O
slave	B-Operating_System
,	O
complete	O
galvanic	O
isolation	O
by	O
opto-couplers	O
is	O
needed	O
.	O
</s>
<s>
It	O
is	O
the	O
minimum	O
time	O
required	O
by	O
the	O
slave	B-Operating_System
to	O
realise	O
that	O
the	O
data	O
transmission	O
is	O
complete	O
.	O
</s>
<s>
After	O
tm	O
,	O
the	O
data	O
line	O
goes	O
to	O
idle	O
and	O
the	O
slave	B-Operating_System
starts	O
updating	O
its	O
data	O
in	O
the	O
shift	O
register	O
.	O
</s>
<s>
It	O
is	O
the	O
time	O
delay	O
between	O
two	O
consecutive	O
clock	O
sequences	O
from	O
the	O
master	B-Operating_System
.	O
</s>
<s>
The	O
SSI	O
is	O
initially	O
in	O
the	O
idle	O
mode	O
,	O
where	O
both	O
the	O
data	O
and	O
clock	O
lines	O
stay	O
HIGH	O
,	O
and	O
the	O
slave	B-Operating_System
keeps	O
updating	O
its	O
current	O
data	O
.	O
</s>
<s>
The	O
transmission	O
mode	O
is	O
evoked	O
when	O
the	O
master	B-Operating_System
initiates	O
a	O
train	O
of	O
clock	O
pulses	O
.	O
</s>
<s>
Once	O
the	O
slave	B-Operating_System
receives	O
the	O
beginning	O
of	O
the	O
clock	O
signal	O
(	O
1	O
)	O
,	O
it	O
automatically	O
freezes	O
its	O
current	O
data	O
.	O
</s>
<s>
The	O
slave	B-Operating_System
starts	O
updating	O
its	O
value	O
and	O
the	O
data	O
line	O
is	O
set	O
to	O
HIGH	O
(	O
idle	O
mode	O
)	O
if	O
there	O
are	O
no	O
clock	O
pulses	O
within	O
time	O
,	O
tm	O
.	O
</s>
<s>
Once	O
the	O
slave	B-Operating_System
receives	O
a	O
clock	O
signal	O
at	O
a	O
time	O
,	O
tp	O
(>=	O
tm	O
)	O
,	O
the	O
updated	O
position	O
value	O
is	O
frozen	O
and	O
the	O
transmission	O
of	O
the	O
value	O
begins	O
as	O
described	O
earlier	O
.	O
</s>
<s>
the	O
next	O
clock	O
pulses	O
comes	O
in	O
time	O
tw	O
(	O
<	O
tm	O
)	O
)	O
the	O
value	O
of	O
the	O
slave	B-Operating_System
is	O
not	O
updated	O
.	O
</s>
<s>
The	O
value	O
of	O
the	O
slave	B-Operating_System
is	O
updated	O
only	O
when	O
the	O
timing	O
between	O
two	O
clock	O
pulses	O
is	O
more	O
than	O
the	O
transfer	O
timeout	O
,	O
tm	O
.	O
</s>
<s>
The	O
transmission	O
of	O
data	O
is	O
controlled	O
by	O
the	O
master	B-Operating_System
and	O
the	O
transmission	O
can	O
be	O
interrupted	O
at	O
any	O
time	O
by	O
stopping	O
the	O
clock	O
sequence	O
for	O
a	O
period	O
longer	O
than	O
tm	O
.	O
</s>
<s>
The	O
slave	B-Operating_System
automatically	O
will	O
recognize	O
the	O
transfer	O
timeout	O
and	O
go	O
into	O
idle	O
mode	O
.	O
</s>
<s>
The	O
maximum	O
permissible	O
length	O
of	O
cable	O
separating	O
the	O
master	B-Operating_System
and	O
slave	B-Operating_System
is	O
a	O
function	O
of	O
data	O
signalling	O
rate	O
and	O
is	O
influenced	O
by	O
the	O
tolerable	O
signal	O
distortion	O
,	O
the	O
amount	O
of	O
longitudinally	O
coupled	O
noise	O
and	O
ground	O
potential	O
differences	O
introduced	O
between	O
the	O
master	B-Operating_System
and	O
the	O
slave	B-Operating_System
circuit	O
.	O
</s>
<s>
Slaves	B-Operating_System
use	O
master	B-Operating_System
’s	O
clock	O
and	O
hence	O
do	O
n’t	O
need	O
precision	O
oscillators	O
.	O
</s>
<s>
The	O
SSI	O
allows	O
to	O
connect	O
up	O
to	O
three	O
slaves	B-Operating_System
to	O
a	O
common	O
clock	O
.	O
</s>
<s>
SSI	O
can	O
handle	O
only	O
short	O
distance	O
communication	O
(	O
up	O
to	O
1.2km	O
)	O
and	O
supports	O
only	O
one	O
master	B-Operating_System
device	O
.	O
</s>
<s>
When	O
compared	O
to	O
advanced	O
communication	O
systems	O
based	O
on	O
field	O
buses	O
or	O
Ethernet	O
,	O
SSI	O
is	O
limited	O
to	O
a	O
master	B-Operating_System
slave	I-Operating_System
architecture	I-Operating_System
and	O
a	O
simple	O
point	O
to	O
point	O
communication	O
between	O
a	O
master	B-Operating_System
and	O
a	O
slave	B-Operating_System
.	O
</s>
<s>
Another	O
disadvantage	O
is	O
that	O
there	O
is	O
no	O
hardware	O
slave	B-Operating_System
acknowledgment	O
i.e.	O
</s>
<s>
detection	O
of	O
slave	B-Operating_System
for	O
communication	O
.	O
</s>
