<s>
A	O
superscalar	B-General_Concept
processor	I-General_Concept
is	O
a	O
CPU	B-General_Concept
that	O
implements	O
a	O
form	O
of	O
parallelism	B-Operating_System
called	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
within	O
a	O
single	O
processor	O
.	O
</s>
<s>
In	O
contrast	O
to	O
a	O
scalar	B-General_Concept
processor	I-General_Concept
,	O
which	O
can	O
execute	O
at	O
most	O
one	O
single	O
instruction	O
per	O
clock	O
cycle	O
,	O
a	O
superscalar	B-General_Concept
processor	I-General_Concept
can	O
execute	O
more	O
than	O
one	O
instruction	O
during	O
a	O
clock	O
cycle	O
by	O
simultaneously	O
dispatching	O
multiple	O
instructions	O
to	O
different	O
execution	B-General_Concept
units	I-General_Concept
on	O
the	O
processor	O
.	O
</s>
<s>
Each	O
execution	B-General_Concept
unit	I-General_Concept
is	O
not	O
a	O
separate	O
processor	O
(	O
or	O
a	O
core	O
if	O
the	O
processor	O
is	O
a	O
multi-core	B-Architecture
processor	I-Architecture
)	O
,	O
but	O
an	O
execution	O
resource	O
within	O
a	O
single	O
CPU	B-General_Concept
such	O
as	O
an	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
In	O
Flynn	B-Operating_System
's	I-Operating_System
taxonomy	I-Operating_System
,	O
a	O
single-core	O
superscalar	B-General_Concept
processor	I-General_Concept
is	O
classified	O
as	O
an	O
SISD	B-Operating_System
processor	O
(	O
single	O
instruction	O
stream	O
,	O
single	O
data	O
stream	O
)	O
,	O
though	O
a	O
single-core	O
superscalar	B-General_Concept
processor	I-General_Concept
that	O
supports	O
short	O
vector	B-Operating_System
operations	O
could	O
be	O
classified	O
as	O
SIMD	B-Device
(	O
single	O
instruction	O
stream	O
,	O
multiple	O
data	O
streams	O
)	O
.	O
</s>
<s>
A	O
multi-core	B-Architecture
superscalar	B-General_Concept
processor	I-General_Concept
is	O
classified	O
as	O
an	O
MIMD	B-Operating_System
processor	O
(	O
multiple	O
instruction	O
streams	O
,	O
multiple	O
data	O
streams	O
)	O
.	O
</s>
<s>
While	O
a	O
superscalar	B-General_Concept
CPU	B-General_Concept
is	O
typically	O
also	O
pipelined	B-General_Concept
,	O
superscalar	B-General_Concept
and	O
pipelining	O
execution	O
are	O
considered	O
different	O
performance	O
enhancement	O
techniques	O
.	O
</s>
<s>
The	O
former	O
executes	O
multiple	O
instructions	O
in	O
parallel	O
by	O
using	O
multiple	O
execution	B-General_Concept
units	I-General_Concept
,	O
whereas	O
the	O
latter	O
executes	O
multiple	O
instructions	O
in	O
the	O
same	O
execution	B-General_Concept
unit	I-General_Concept
in	O
parallel	O
by	O
dividing	O
the	O
execution	B-General_Concept
unit	I-General_Concept
into	O
different	O
phases	O
.	O
</s>
<s>
The	O
superscalar	B-General_Concept
technique	O
is	O
traditionally	O
associated	O
with	O
several	O
identifying	O
characteristics	O
(	O
within	O
a	O
given	O
CPU	B-General_Concept
)	O
:	O
</s>
<s>
Seymour	O
Cray	O
's	O
CDC	B-Device
6600	I-Device
from	O
1964	O
is	O
often	O
mentioned	O
as	O
the	O
first	O
superscalar	B-General_Concept
design	O
.	O
</s>
<s>
The	O
1967	O
IBM	B-Device
System/360	I-Device
Model	I-Device
91	I-Device
was	O
another	O
superscalar	B-General_Concept
mainframe	O
.	O
</s>
<s>
The	O
Motorola	O
MC88100	B-General_Concept
(	O
1988	O
)	O
,	O
the	O
Intel	O
i960CA	O
(	O
1989	O
)	O
and	O
the	O
AMD	O
29000-series	O
29050	O
(	O
1990	O
)	O
microprocessors	O
were	O
the	O
first	O
commercial	O
single-chip	O
superscalar	B-General_Concept
microprocessors	O
.	O
</s>
<s>
RISC	B-Architecture
microprocessors	O
like	O
these	O
were	O
the	O
first	O
to	O
have	O
superscalar	B-General_Concept
execution	I-General_Concept
,	O
because	O
RISC	B-Architecture
architectures	I-Architecture
free	O
transistors	O
and	O
die	O
area	O
which	O
can	O
be	O
used	O
to	O
include	O
multiple	O
execution	B-General_Concept
units	I-General_Concept
(	O
this	O
was	O
why	O
RISC	B-Architecture
designs	O
were	O
faster	O
than	O
CISC	B-Architecture
designs	O
through	O
the	O
1980s	O
and	O
into	O
the	O
1990s	O
)	O
.	O
</s>
<s>
Except	O
for	O
CPUs	O
used	O
in	O
low-power	O
applications	O
,	O
embedded	B-Architecture
systems	I-Architecture
,	O
and	O
battery-powered	O
devices	O
,	O
essentially	O
all	O
general-purpose	O
CPUs	O
developed	O
since	O
about	O
1998	O
are	O
superscalar	B-General_Concept
.	O
</s>
<s>
The	O
P5	B-General_Concept
Pentium	B-Device
was	O
the	O
first	O
superscalar	B-General_Concept
x86	B-Operating_System
processor	O
;	O
the	O
Nx586	B-Device
,	O
P6	B-Device
Pentium	B-Device
Pro	I-Device
and	O
AMD	O
K5	O
were	O
among	O
the	O
first	O
designs	O
which	O
decode	O
x86-instructions	O
asynchronously	O
into	O
dynamic	O
microcode-like	O
micro-op	B-General_Concept
sequences	O
prior	O
to	O
actual	O
execution	O
on	O
a	O
superscalar	B-General_Concept
microarchitecture	B-General_Concept
;	O
this	O
opened	O
up	O
for	O
dynamic	O
scheduling	O
of	O
buffered	O
partial	O
instructions	O
and	O
enabled	O
more	O
parallelism	B-Operating_System
to	O
be	O
extracted	O
compared	O
to	O
the	O
more	O
rigid	O
methods	O
used	O
in	O
the	O
simpler	O
P5	B-General_Concept
Pentium	B-Device
;	O
it	O
also	O
simplified	O
speculative	B-General_Concept
execution	I-General_Concept
and	O
allowed	O
higher	O
clock	O
frequencies	O
compared	O
to	O
designs	O
such	O
as	O
the	O
advanced	O
Cyrix	B-General_Concept
6x86	I-General_Concept
.	O
</s>
<s>
The	O
simplest	O
processors	O
are	O
scalar	B-General_Concept
processors	I-General_Concept
.	O
</s>
<s>
Each	O
instruction	O
executed	O
by	O
a	O
scalar	B-General_Concept
processor	I-General_Concept
typically	O
manipulates	O
one	O
or	O
two	O
data	O
items	O
at	O
a	O
time	O
.	O
</s>
<s>
By	O
contrast	O
,	O
each	O
instruction	O
executed	O
by	O
a	O
vector	B-Operating_System
processor	I-Operating_System
operates	O
simultaneously	O
on	O
many	O
data	O
items	O
.	O
</s>
<s>
An	O
analogy	O
is	O
the	O
difference	O
between	O
scalar	O
and	O
vector	B-Operating_System
arithmetic	O
.	O
</s>
<s>
A	O
superscalar	B-General_Concept
processor	I-General_Concept
is	O
a	O
mixture	O
of	O
the	O
two	O
.	O
</s>
<s>
Each	O
instruction	O
processes	O
one	O
data	O
item	O
,	O
but	O
there	O
are	O
multiple	O
execution	B-General_Concept
units	I-General_Concept
within	O
each	O
CPU	B-General_Concept
thus	O
multiple	O
instructions	O
can	O
be	O
processing	O
separate	O
data	O
items	O
concurrently	O
.	O
</s>
<s>
Superscalar	B-General_Concept
CPU	B-General_Concept
design	O
emphasizes	O
improving	O
the	O
instruction	O
dispatcher	O
accuracy	O
,	O
and	O
allowing	O
it	O
to	O
keep	O
the	O
multiple	O
execution	B-General_Concept
units	I-General_Concept
in	O
use	O
at	O
all	O
times	O
.	O
</s>
<s>
While	O
early	O
superscalar	B-General_Concept
CPUs	O
would	O
have	O
two	O
ALUs	O
and	O
a	O
single	O
FPU	B-General_Concept
,	O
a	O
later	O
design	O
such	O
as	O
the	O
PowerPC	B-General_Concept
970	I-General_Concept
includes	O
four	O
ALUs	O
,	O
two	O
FPUs	O
,	O
and	O
two	O
SIMD	B-Device
units	O
.	O
</s>
<s>
A	O
superscalar	B-General_Concept
processor	I-General_Concept
usually	O
sustains	O
an	O
execution	O
rate	O
in	O
excess	O
of	O
one	O
instruction	O
per	O
machine	O
cycle	O
.	O
</s>
<s>
But	O
merely	O
processing	O
multiple	O
instructions	O
concurrently	O
does	O
not	O
make	O
an	O
architecture	O
superscalar	B-General_Concept
,	O
since	O
pipelined	B-General_Concept
,	O
multiprocessor	B-Operating_System
or	O
multi-core	B-Architecture
architectures	O
also	O
achieve	O
that	O
,	O
but	O
with	O
different	O
methods	O
.	O
</s>
<s>
In	O
a	O
superscalar	B-General_Concept
CPU	B-General_Concept
the	O
dispatcher	O
reads	O
instructions	O
from	O
memory	O
and	O
decides	O
which	O
ones	O
can	O
be	O
run	O
in	O
parallel	O
,	O
dispatching	O
each	O
to	O
one	O
of	O
the	O
several	O
execution	B-General_Concept
units	I-General_Concept
contained	O
inside	O
a	O
single	O
CPU	B-General_Concept
.	O
</s>
<s>
Therefore	O
,	O
a	O
superscalar	B-General_Concept
processor	I-General_Concept
can	O
be	O
envisioned	O
having	O
multiple	O
parallel	O
pipelines	O
,	O
each	O
of	O
which	O
is	O
processing	O
instructions	O
simultaneously	O
from	O
a	O
single	O
instruction	O
thread	O
.	O
</s>
<s>
Available	O
performance	O
improvement	O
from	O
superscalar	B-General_Concept
techniques	O
is	O
limited	O
by	O
three	O
key	O
areas	O
:	O
</s>
<s>
Existing	O
binary	O
executable	O
programs	O
have	O
varying	O
degrees	O
of	O
intrinsic	O
parallelism	B-Operating_System
.	O
</s>
<s>
Although	O
the	O
instruction	O
stream	O
may	O
contain	O
no	O
inter-instruction	O
dependencies	O
,	O
a	O
superscalar	B-General_Concept
CPU	B-General_Concept
must	O
nonetheless	O
check	O
for	O
that	O
possibility	O
,	O
since	O
there	O
is	O
no	O
assurance	O
otherwise	O
and	O
failure	O
to	O
detect	O
a	O
dependency	O
would	O
produce	O
incorrect	O
results	O
.	O
</s>
<s>
No	O
matter	O
how	O
advanced	O
the	O
semiconductor	B-Architecture
process	I-Architecture
or	O
how	O
fast	O
the	O
switching	O
speed	O
,	O
this	O
places	O
a	O
practical	O
limit	O
on	O
how	O
many	O
instructions	O
can	O
be	O
simultaneously	O
dispatched	O
.	O
</s>
<s>
While	O
process	O
advances	O
will	O
allow	O
ever	O
greater	O
numbers	O
of	O
execution	B-General_Concept
units	I-General_Concept
(	O
e.g.	O
</s>
<s>
ALUs	O
)	O
,	O
the	O
burden	O
of	O
checking	O
instruction	O
dependencies	O
grows	O
rapidly	O
,	O
as	O
does	O
the	O
complexity	O
of	O
register	B-Architecture
renaming	I-Architecture
circuitry	O
to	O
mitigate	O
some	O
dependencies	O
.	O
</s>
<s>
Collectively	O
the	O
power	B-General_Concept
consumption	I-General_Concept
,	O
complexity	O
and	O
gate	O
delay	O
costs	O
limit	O
the	O
achievable	O
superscalar	B-General_Concept
speedup	O
.	O
</s>
<s>
However	O
even	O
given	O
infinitely	O
fast	O
dependency	O
checking	O
logic	O
on	O
an	O
otherwise	O
conventional	O
superscalar	B-General_Concept
CPU	B-General_Concept
,	O
if	O
the	O
instruction	O
stream	O
itself	O
has	O
many	O
dependencies	O
,	O
this	O
would	O
also	O
limit	O
the	O
possible	O
speedup	O
.	O
</s>
<s>
Thus	O
the	O
degree	O
of	O
intrinsic	O
parallelism	B-Operating_System
in	O
the	O
code	O
stream	O
forms	O
a	O
second	O
limitation	O
.	O
</s>
<s>
Collectively	O
,	O
these	O
limits	O
drive	O
investigation	O
into	O
alternative	O
architectural	O
changes	O
such	O
as	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
,	O
explicitly	B-General_Concept
parallel	I-General_Concept
instruction	I-General_Concept
computing	I-General_Concept
(	O
EPIC	O
)	O
,	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
,	O
and	O
multi-core	B-Architecture
computing	I-Architecture
.	O
</s>
<s>
With	O
VLIW	B-General_Concept
,	O
the	O
burdensome	O
task	O
of	O
dependency	O
checking	O
by	O
hardware	O
logic	O
at	O
run	O
time	O
is	O
removed	O
and	O
delegated	O
to	O
the	O
compiler	B-Language
.	O
</s>
<s>
Explicitly	B-General_Concept
parallel	I-General_Concept
instruction	I-General_Concept
computing	I-General_Concept
(	O
EPIC	O
)	O
is	O
like	O
VLIW	B-General_Concept
with	O
extra	O
cache	O
prefetching	O
instructions	O
.	O
</s>
<s>
Simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
is	O
a	O
technique	O
for	O
improving	O
the	O
overall	O
efficiency	O
of	O
superscalar	B-General_Concept
processors	I-General_Concept
.	O
</s>
<s>
Superscalar	B-General_Concept
processors	I-General_Concept
differ	O
from	O
multi-core	B-Architecture
processors	I-Architecture
in	O
that	O
the	O
several	O
execution	B-General_Concept
units	I-General_Concept
are	O
not	O
entire	O
processors	O
.	O
</s>
<s>
A	O
single	O
processor	O
is	O
composed	O
of	O
finer-grained	O
execution	B-General_Concept
units	I-General_Concept
such	O
as	O
the	O
ALU	B-General_Concept
,	O
integer	O
multiplier	O
,	O
integer	O
shifter	O
,	O
FPU	B-General_Concept
,	O
etc	O
.	O
</s>
<s>
There	O
may	O
be	O
multiple	O
versions	O
of	O
each	O
execution	B-General_Concept
unit	I-General_Concept
to	O
enable	O
execution	O
of	O
many	O
instructions	O
in	O
parallel	O
.	O
</s>
<s>
This	O
differs	O
from	O
a	O
multi-core	B-Architecture
processor	I-Architecture
that	O
concurrently	O
processes	O
instructions	O
from	O
multiple	O
threads	O
,	O
one	O
thread	O
per	O
processing	B-General_Concept
unit	I-General_Concept
(	O
called	O
"	O
core	O
"	O
)	O
.	O
</s>
<s>
It	O
also	O
differs	O
from	O
a	O
pipelined	B-General_Concept
processor	I-General_Concept
,	O
where	O
the	O
multiple	O
instructions	O
can	O
concurrently	O
be	O
in	O
various	O
stages	O
of	O
execution	O
,	O
assembly-line	O
fashion	O
.	O
</s>
<s>
Thus	O
a	O
multicore	B-Architecture
CPU	I-Architecture
is	O
possible	O
where	O
each	O
core	O
is	O
an	O
independent	O
processor	O
containing	O
multiple	O
parallel	O
pipelines	O
,	O
each	O
pipeline	O
being	O
superscalar	B-General_Concept
.	O
</s>
<s>
Some	O
processors	O
also	O
include	O
vector	B-Operating_System
capability	O
.	O
</s>
