<s>
The	O
Super	B-General_Concept
Harvard	I-General_Concept
Architecture	I-General_Concept
Single-Chip	I-General_Concept
Computer	I-General_Concept
(	O
SHARC	B-General_Concept
)	O
is	O
a	O
high	O
performance	O
floating-point	B-Algorithm
and	O
fixed-point	O
DSP	B-Architecture
from	O
Analog	O
Devices	O
.	O
</s>
<s>
SHARC	B-General_Concept
is	O
used	O
in	O
a	O
variety	O
of	O
signal	O
processing	O
applications	O
ranging	O
from	O
audio	O
processing	O
,	O
to	O
single-CPU	O
guided	O
artillery	O
shells	O
to	O
1000-CPU	O
over-the-horizon	O
radar	O
processing	O
computers	O
.	O
</s>
<s>
SHARC	B-General_Concept
processors	O
are	O
typically	O
intended	O
to	O
have	O
a	O
good	O
number	O
of	O
serial	O
links	O
to	O
other	O
SHARC	B-General_Concept
processors	O
nearby	O
,	O
to	O
be	O
used	O
as	O
a	O
low-cost	O
alternative	O
to	O
SMP	B-Operating_System
.	O
</s>
<s>
The	O
SHARC	B-General_Concept
is	O
a	O
Harvard	B-Architecture
architecture	I-Architecture
word-addressed	B-General_Concept
VLIW	B-General_Concept
processor	O
;	O
it	O
knows	O
nothing	O
of	O
8-bit	O
or	O
16-bit	O
values	O
since	O
each	O
address	O
is	O
used	O
to	O
point	O
to	O
a	O
whole	O
32-bit	O
word	O
,	O
not	O
just	O
an	O
octet	O
.	O
</s>
<s>
The	O
word	O
size	O
is	O
48-bit	O
for	O
instructions	O
,	O
32-bit	O
for	O
integers	O
and	O
normal	O
floating-point	B-Algorithm
,	O
and	O
40-bit	O
for	O
extended	O
floating-point	B-Algorithm
.	O
</s>
<s>
A	O
system	O
that	O
does	O
not	O
use	O
40-bit	O
extended	O
floating-point	B-Algorithm
might	O
divide	O
the	O
on-chip	O
memory	O
into	O
two	O
sections	O
,	O
a	O
48-bit	O
one	O
for	O
code	O
and	O
a	O
32-bit	O
one	O
for	O
everything	O
else	O
.	O
</s>
<s>
Off-chip	O
memory	O
can	O
be	O
used	O
with	O
the	O
SHARC	B-General_Concept
.	O
</s>
<s>
If	O
the	O
off-chip	O
memory	O
is	O
configured	O
as	O
32-bit	O
words	O
to	O
avoid	O
waste	O
,	O
then	O
only	O
the	O
on-chip	O
memory	O
may	O
be	O
used	O
for	O
code	O
execution	O
and	O
extended	O
floating-point	B-Algorithm
.	O
</s>
<s>
Operating	B-General_Concept
systems	I-General_Concept
may	O
use	O
overlays	B-General_Concept
to	O
work	O
around	O
this	O
problem	O
,	O
transferring	O
48-bit	O
data	O
to	O
on-chip	O
memory	O
as	O
needed	O
for	O
execution	O
.	O
</s>
<s>
A	O
DMA	B-General_Concept
engine	I-General_Concept
is	O
provided	O
for	O
this	O
.	O
</s>
<s>
True	O
paging	O
is	O
impossible	O
without	O
an	O
external	O
MMU	B-General_Concept
.	O
</s>
<s>
The	O
SHARC	B-General_Concept
has	O
a	O
32-bit	O
word-addressed	B-General_Concept
address	O
space	O
.	O
</s>
<s>
SHARC	B-General_Concept
instructions	O
may	O
contain	O
a	O
32-bit	O
immediate	O
operand	O
.	O
</s>
<s>
Many	O
instructions	O
are	O
conditional	O
,	O
and	O
may	O
be	O
preceded	O
with	O
"	O
if	O
condition	O
"	O
in	O
the	O
assembly	B-Language
language	I-Language
.	O
</s>
<s>
There	O
are	O
a	O
number	O
of	O
condition	O
choices	O
,	O
similar	O
to	O
the	O
choices	O
provided	O
by	O
the	O
x86	B-Operating_System
flags	O
register	O
.	O
</s>
<s>
There	O
are	O
two	O
delay	B-General_Concept
slots	I-General_Concept
.	O
</s>
<s>
The	O
SHARC	B-General_Concept
processor	O
has	O
built-in	O
support	O
for	O
loop	O
control	O
.	O
</s>
<s>
The	O
SHARC	B-General_Concept
has	O
two	O
full	O
sets	O
of	O
general-purpose	O
registers	O
.	O
</s>
<s>
Code	O
can	O
instantly	O
switch	O
between	O
them	O
,	O
allowing	O
for	O
fast	O
context	O
switches	O
between	O
an	O
application	O
and	O
an	O
OS	B-General_Concept
or	O
between	O
two	O
threads	O
.	O
</s>
