<s>
The	O
SuperSPARC	B-Device
is	O
a	O
microprocessor	B-Architecture
that	O
implements	O
the	O
SPARC	B-Architecture
V8	I-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
developed	O
by	O
Sun	O
Microsystems	O
.	O
</s>
<s>
The	O
SuperSPARC	B-Device
contains	O
3.1	O
million	O
transistors	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
by	O
Texas	O
Instruments	O
(	O
TI	O
)	O
at	O
Miho	O
,	O
Japan	O
in	O
a	O
0.8	O
micrometre	O
triple-metal	O
BiCMOS	B-General_Concept
process	O
.	O
</s>
<s>
There	O
are	O
two	O
derivatives	O
of	O
the	O
SuperSPARC	B-Device
:	O
the	O
SuperSPARC+	O
and	O
SuperSPARC-II	O
.	O
</s>
<s>
The	O
SuperSPARC+	O
was	O
developed	O
to	O
remedy	O
some	O
of	O
the	O
design	O
flaws	O
that	O
limited	O
the	O
SuperSPARC	B-Device
's	O
clock	O
frequency	O
and	O
thus	O
performance	O
.	O
</s>
<s>
The	O
SuperSPARC-II	O
,	O
introduced	O
in	O
1994	O
,	O
was	O
a	O
major	O
revision	O
with	O
improvements	O
that	O
enabled	O
the	O
microprocessor	B-Architecture
to	O
reach	O
85MHz	O
in	O
desktop	O
systems	O
and	O
90MHz	O
in	O
the	O
more	O
heavily	O
cooled	O
SPARCserver-1000E	O
.	O
</s>
<s>
SuperSPARC	B-Device
CPU	O
modules	O
are	O
used	O
in	O
both	O
the	O
SPARCstation	B-Architecture
10	I-Architecture
and	O
SPARCstation	B-Architecture
20	I-Architecture
.	O
</s>
<s>
The	O
SuperSPARC-II	O
was	O
replaced	O
in	O
1995	O
by	O
the	O
64-bit	B-Device
UltraSPARC	B-General_Concept
,	O
an	O
implementation	O
of	O
the	O
64-bit	B-Device
SPARC	B-Architecture
V9	I-Architecture
ISA	O
.	O
</s>
