<s>
The	O
SW26010	B-General_Concept
is	O
a	O
260-core	O
manycore	B-General_Concept
processor	I-General_Concept
designed	O
by	O
the	O
Shanghai	O
Integrated	O
Circuit	O
Technology	O
and	O
Industry	O
Promotion	O
Center	O
(	O
ICC	O
for	O
short	O
)	O
(	O
Chinese	O
:	O
上海集成电路技术与产业促进中心	O
( 简称ICC	O
)	O
)	O
.	O
</s>
<s>
It	O
implements	O
the	O
Sunway	B-Device
architecture	I-Device
,	O
a	O
64-bit	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computing	I-Architecture
(	O
RISC	B-Architecture
)	O
architecture	O
designed	O
in	O
China	O
.	O
</s>
<s>
The	O
SW26010	B-General_Concept
has	O
four	O
clusters	O
of	O
64	O
Compute-Processing	O
Elements	O
(	O
CPEs	O
)	O
which	O
are	O
arranged	O
in	O
an	O
eight-by-eight	O
array	O
.	O
</s>
<s>
The	O
CPEs	O
support	O
SIMD	B-Device
instructions	O
and	O
are	O
capable	O
of	O
performing	O
eight	O
double-precision	O
floating-point	B-Algorithm
operations	O
per	O
cycle	O
.	O
</s>
<s>
Each	O
cluster	O
has	O
its	O
own	O
dedicated	O
DDR3	O
SDRAM	O
controller	B-General_Concept
and	O
a	O
memory	B-General_Concept
bank	I-General_Concept
with	O
its	O
own	O
address	B-General_Concept
space	I-General_Concept
.	O
</s>
<s>
The	O
CPE	O
cores	O
feature	O
64KB	O
of	O
scratchpad	B-General_Concept
memory	I-General_Concept
for	O
data	O
and	O
16KB	O
for	O
instructions	O
,	O
and	O
communicate	O
via	O
a	O
network	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
,	O
instead	O
of	O
having	O
a	O
traditional	O
cache	B-General_Concept
hierarchy	I-General_Concept
.	O
</s>
<s>
The	O
MPEs	O
have	O
a	O
more	O
traditional	O
setup	O
,	O
with	O
32KB	O
L1	O
instruction	B-General_Concept
and	O
data	B-General_Concept
caches	I-General_Concept
and	O
a	O
256KB	O
L2	O
cache	O
.	O
</s>
<s>
Finally	O
,	O
the	O
on-chip	B-Architecture
network	I-Architecture
connects	O
to	O
a	O
single	O
system	O
interconnection	O
interface	O
that	O
connects	O
the	O
chip	O
to	O
the	O
outside	O
world	O
.	O
</s>
<s>
The	O
SW26010	B-General_Concept
is	O
used	O
in	O
the	O
Sunway	B-Device
TaihuLight	I-Device
supercomputer	B-Architecture
,	O
which	O
between	O
March	O
and	O
June	O
2018	O
,	O
was	O
the	O
world	O
's	O
fastest	B-Operating_System
supercomputer	I-Operating_System
as	O
ranked	O
by	O
the	O
TOP500	B-Operating_System
project	O
.	O
</s>
<s>
The	O
system	O
uses	O
40,960	O
SW26010s	B-General_Concept
to	O
obtain	O
93.01PFLOPS	O
on	O
the	O
LINPACK	B-Device
benchmark	I-Device
.	O
</s>
<s>
Each	O
CG	O
has	O
its	O
memory	B-General_Concept
controller	I-General_Concept
(	O
MC	O
)	O
,	O
connecting	O
to	O
16GB	O
of	O
DDR4	O
memory	O
with	O
a	O
bandwidth	O
of	O
51.2	O
GB/s	O
.	O
</s>
