<s>
The	O
StrongARM	B-Device
is	O
a	O
family	O
of	O
computer	O
microprocessors	B-Architecture
developed	O
by	O
Digital	O
Equipment	O
Corporation	O
and	O
manufactured	O
in	O
the	O
late	O
1990s	O
which	O
implemented	O
the	O
ARM	B-Architecture
v4	I-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
Intel	O
then	O
continued	O
to	O
manufacture	O
it	O
before	O
replacing	O
it	O
with	O
the	O
StrongARM-derived	O
ARM-based	O
follow-up	O
architecture	O
called	O
XScale	B-Application
in	O
the	O
early	O
2000s	O
.	O
</s>
<s>
According	O
to	O
Allen	O
Baum	O
,	O
the	O
StrongARM	B-Device
traces	O
its	O
history	O
to	O
attempts	O
to	O
make	O
a	O
low-power	O
version	O
of	O
the	O
DEC	B-Device
Alpha	I-Device
,	O
which	O
DEC	O
's	O
engineers	O
quickly	O
concluded	O
was	O
not	O
possible	O
.	O
</s>
<s>
They	O
then	O
became	O
interested	O
in	O
designs	O
dedicated	O
to	O
low-power	O
applications	O
which	O
led	O
them	O
to	O
the	O
ARM	B-Architecture
family	I-Architecture
.	O
</s>
<s>
One	O
of	O
the	O
only	O
major	O
users	O
of	O
the	O
ARM	O
for	O
performance-related	O
products	O
at	O
that	O
time	O
was	O
Apple	O
,	O
whose	O
Newton	B-Device
device	O
was	O
based	O
on	O
the	O
ARM	O
platform	O
.	O
</s>
<s>
The	O
StrongARM	B-Device
was	O
a	O
collaborative	O
project	O
between	O
DEC	O
and	O
Advanced	B-Architecture
RISC	I-Architecture
Machines	I-Architecture
to	O
create	O
a	O
faster	O
ARM	B-Architecture
microprocessor	I-Architecture
.	O
</s>
<s>
The	O
StrongARM	B-Device
was	O
designed	O
to	O
address	O
the	O
upper	O
end	O
of	O
the	O
low-power	O
embedded	O
market	O
,	O
where	O
users	O
needed	O
more	O
performance	O
than	O
the	O
ARM	O
could	O
deliver	O
while	O
being	O
able	O
to	O
accept	O
more	O
external	O
support	O
.	O
</s>
<s>
Targets	O
were	O
devices	O
such	O
as	O
newer	O
personal	B-Application
digital	I-Application
assistants	I-Application
and	O
set-top	O
boxes	O
.	O
</s>
<s>
This	O
design	O
center	O
was	O
led	O
by	O
Dan	O
Dobberpuhl	O
and	O
was	O
the	O
main	O
design	O
site	O
for	O
the	O
StrongARM	B-Device
project	O
.	O
</s>
<s>
The	O
project	O
was	O
set	O
up	O
in	O
1995	O
,	O
and	O
quickly	O
delivered	O
their	O
first	O
design	O
,	O
the	O
SA-110	B-Device
.	O
</s>
<s>
DEC	O
agreed	O
to	O
sell	O
StrongARM	B-Device
to	O
Intel	O
as	O
part	O
of	O
a	O
lawsuit	O
settlement	O
in	O
1997	O
.	O
</s>
<s>
Intel	O
used	O
the	O
StrongARM	B-Device
to	O
replace	O
their	O
ailing	O
line	O
of	O
RISC	O
processors	O
,	O
the	O
i860	B-General_Concept
and	O
i960	B-General_Concept
.	O
</s>
<s>
When	O
the	O
semiconductor	O
division	O
of	O
DEC	O
was	O
sold	O
to	O
Intel	O
,	O
many	O
engineers	O
from	O
the	O
Palo	O
Alto	O
design	O
group	O
moved	O
to	O
SiByte	O
,	O
a	O
start-up	O
company	O
designing	O
MIPS	B-Device
system-on-a-chip	B-Architecture
(	O
SoC	O
)	O
products	O
for	O
the	O
networking	O
market	O
.	O
</s>
<s>
The	O
Austin	O
design	O
group	O
spun	O
off	O
to	O
become	O
Alchemy	B-Device
Semiconductor	I-Device
,	O
another	O
start-up	O
company	O
designing	O
MIPS	B-Device
SoCs	O
for	O
the	O
hand-held	O
market	O
.	O
</s>
<s>
A	O
new	O
StrongARM	B-Device
core	O
was	O
developed	O
by	O
Intel	O
and	O
introduced	O
in	O
2000	O
as	O
the	O
XScale	B-Application
.	O
</s>
<s>
The	O
SA-110	B-Device
was	O
the	O
first	O
microprocessor	B-Architecture
in	O
the	O
StrongARM	B-Device
family	O
.	O
</s>
<s>
Throughout	O
1996	O
,	O
the	O
SA-110	B-Device
was	O
the	O
highest	O
performing	O
microprocessor	B-Architecture
for	O
portable	O
devices	O
.	O
</s>
<s>
Towards	O
the	O
end	O
of	O
1996	O
it	O
was	O
a	O
leading	O
CPU	O
for	O
internet/intranet	O
appliances	O
and	O
thin	B-Device
client	I-Device
systems	O
.	O
</s>
<s>
The	O
SA-110	B-Device
'	O
s	O
first	O
design	O
win	O
was	O
the	O
Apple	B-Device
MessagePad	I-Device
2000	O
.	O
</s>
<s>
It	O
was	O
also	O
used	O
in	O
a	O
number	O
of	O
products	O
including	O
the	O
Acorn	O
Computers	O
Risc	B-Device
PC	I-Device
and	O
Eidos	O
Optima	O
video	O
editing	O
system	O
.	O
</s>
<s>
The	O
SA-110	B-Device
'	O
s	O
lead	O
designers	O
were	O
Daniel	O
W	O
.	O
Dobberpuhl	O
,	O
Gregory	O
W	O
.	O
Hoeppner	O
,	O
Liam	O
Madden	O
,	O
and	O
Richard	O
T	O
.	O
Witek	O
.	O
</s>
<s>
The	O
SA-110	B-Device
had	O
a	O
simple	O
microarchitecture	B-General_Concept
.	O
</s>
<s>
It	O
was	O
a	O
scalar	B-General_Concept
design	O
that	O
executed	O
instructions	O
in-order	B-General_Concept
with	O
a	O
five-stage	O
classic	B-General_Concept
RISC	I-General_Concept
pipeline	I-General_Concept
.	O
</s>
<s>
The	O
microprocessor	B-Architecture
was	O
partitioned	O
into	O
several	O
blocks	O
,	O
the	O
IBOX	O
,	O
EBOX	O
,	O
IMMU	O
,	O
DMMU	O
,	O
BIU	O
,	O
WB	O
and	O
PLL	O
.	O
</s>
<s>
The	O
IBOX	O
contained	O
hardware	O
that	O
operated	O
in	O
the	O
first	O
two	O
stages	O
of	O
the	O
pipeline	O
such	O
as	O
the	O
program	B-General_Concept
counter	I-General_Concept
.	O
</s>
<s>
The	O
IBOX	O
decodes	O
the	O
more	O
complex	O
instructions	O
in	O
the	O
ARM	B-Architecture
instruction	I-Architecture
set	I-Architecture
by	O
translating	O
them	O
into	O
sequences	O
of	O
simpler	O
instructions	O
.	O
</s>
<s>
The	O
SA-110	B-Device
did	O
not	O
have	O
branch	B-General_Concept
prediction	I-General_Concept
hardware	O
,	O
but	O
had	O
mechanisms	O
for	O
their	O
speedy	O
processing	O
.	O
</s>
<s>
The	O
hardware	O
that	O
operates	O
during	O
this	O
stage	O
is	O
contained	O
in	O
the	O
EBOX	O
,	O
which	O
comprises	O
the	O
register	B-General_Concept
file	I-General_Concept
,	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
,	O
barrel	O
shifter	O
,	O
multiplier	O
and	O
condition	O
code	O
logic	O
.	O
</s>
<s>
The	O
register	B-General_Concept
file	I-General_Concept
had	O
three	O
read	O
ports	O
and	O
two	O
write	O
ports	O
.	O
</s>
<s>
The	O
IMMU	O
and	O
DMMU	O
are	O
memory	B-General_Concept
management	I-General_Concept
units	I-General_Concept
for	O
instructions	O
and	O
data	O
,	O
respectively	O
.	O
</s>
<s>
Each	O
MMU	O
contained	O
a	O
32-entry	O
fully	O
associative	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
that	O
can	O
map	O
4KB	O
,	O
64KB	O
or	O
1MB	O
pages	O
.	O
</s>
<s>
The	O
bus	O
interface	O
unit	O
(	O
BIU	O
)	O
provided	O
the	O
SA-110	B-Device
with	O
an	O
external	O
interface	O
.	O
</s>
<s>
It	O
was	O
not	O
designed	O
by	O
DEC	O
,	O
but	O
was	O
contracted	O
to	O
the	O
Centre	O
Suisse	O
d'Electronique	O
et	O
de	O
Microtechnique	O
(	O
CSEM	O
)	O
located	O
in	O
Neuchâtel	O
,	O
Switzerland	B-Protocol
.	O
</s>
<s>
The	O
instruction	O
cache	B-General_Concept
and	O
data	B-General_Concept
cache	I-General_Concept
each	O
have	O
a	O
capacity	O
of	O
16KB	O
and	O
are	O
32-way	O
set-associative	O
and	O
virtually	O
addressed	O
.	O
</s>
<s>
The	O
SA-110	B-Device
was	O
designed	O
to	O
be	O
used	O
with	O
slow	O
(	O
and	O
therefore	O
low-cost	O
)	O
memory	O
and	O
therefore	O
the	O
high	O
set	O
associativity	O
allows	O
a	O
higher	O
hit	O
rate	O
than	O
competing	O
designs	O
,	O
and	O
the	O
use	O
of	O
virtual	O
addresses	O
allows	O
memory	O
to	O
be	O
simultaneously	O
cached	O
and	O
uncached	O
.	O
</s>
<s>
The	O
SA-110	B-Device
contained	O
2.5	O
million	O
transistors	O
and	O
is	O
7.8mm	O
by	O
6.4mm	O
large	O
(	O
49.92mm2	O
)	O
.	O
</s>
<s>
It	O
was	O
fabricated	O
by	O
DEC	O
in	O
its	O
proprietary	O
CMOS-6	O
process	O
at	O
its	O
Fab	B-Algorithm
6	O
fab	B-Algorithm
in	O
Hudson	O
,	O
Massachusetts	O
.	O
</s>
<s>
CMOS-6	O
has	O
a	O
0.35µm	O
feature	O
size	O
,	O
a	O
0.25µm	O
effective	O
channel	O
length	O
but	O
for	O
use	O
with	O
the	O
SA-110	B-Device
,	O
only	O
three	O
levels	O
of	O
aluminium	O
interconnect	O
.	O
</s>
<s>
The	O
SA-110	B-Device
was	O
packaged	O
in	O
a	O
144-pin	O
thin	B-Algorithm
quad	I-Algorithm
flat	I-Algorithm
pack	I-Algorithm
(	O
TQFP	O
)	O
.	O
</s>
<s>
The	O
SA-1100	B-Device
was	O
a	O
derivative	O
of	O
the	O
SA-110	B-Device
developed	O
by	O
DEC	O
.	O
</s>
<s>
Announced	O
in	O
1997	O
,	O
the	O
SA-1100	B-Device
was	O
targeted	O
for	O
portable	O
applications	O
such	O
as	O
PDAs	B-Application
and	O
differs	O
from	O
the	O
SA-110	B-Device
by	O
providing	O
a	O
number	O
of	O
features	O
that	O
are	O
desirable	O
for	O
such	O
applications	O
.	O
</s>
<s>
To	O
accommodate	O
these	O
features	O
,	O
the	O
data	B-General_Concept
cache	I-General_Concept
was	O
reduced	O
in	O
size	O
to	O
8KB	O
.	O
</s>
<s>
The	O
extra	O
features	O
are	O
integrated	O
memory	O
,	O
PCMCIA	B-Architecture
,	O
and	O
color	O
LCD	O
controllers	O
connected	O
to	O
an	O
on-die	O
system	O
bus	O
,	O
and	O
five	O
serial	O
I/O	O
channels	O
that	O
are	O
connected	O
to	O
a	O
peripheral	O
bus	O
attached	O
to	O
the	O
system	O
bus	O
.	O
</s>
<s>
The	O
PCMCIA	B-Architecture
controller	O
supports	O
two	O
slots	O
.	O
</s>
<s>
The	O
memory	O
address	O
and	O
data	O
bus	O
is	O
shared	O
with	O
the	O
PCMCIA	B-Architecture
interface	O
.	O
</s>
<s>
The	O
serial	O
I/O	O
channels	O
implement	O
a	O
slave	O
USB	O
interface	O
,	O
a	O
SDLC	B-Protocol
,	O
two	O
UARTs	O
,	O
an	O
IrDA	O
interface	O
,	O
a	O
MCP	O
,	O
and	O
a	O
synchronous	O
serial	O
port	O
.	O
</s>
<s>
The	O
SA-1100	B-Device
had	O
a	O
companion	O
chip	O
,	O
the	O
SA-1101	O
.	O
</s>
<s>
The	O
SA-1101	O
provided	O
additional	O
peripherals	O
to	O
complement	O
those	O
integrated	O
on	O
the	O
SA-1100	B-Device
such	O
as	O
a	O
video	O
output	O
port	O
,	O
two	O
PS/2	B-Protocol
ports	I-Protocol
,	O
a	O
USB	O
controller	O
and	O
a	O
PCMCIA	B-Architecture
controller	O
that	O
replaces	O
that	O
on	O
the	O
SA-1100	B-Device
.	O
</s>
<s>
It	O
was	O
fabricated	O
at	O
DEC	O
's	O
former	O
Hudson	O
,	O
Massachusetts	O
fabrication	B-Algorithm
plant	I-Algorithm
,	O
which	O
was	O
also	O
sold	O
to	O
Intel	O
.	O
</s>
<s>
The	O
SA-1100	B-Device
contained	O
2.5	O
million	O
transistors	O
and	O
measured	O
8.24mm	O
by	O
9.12mm	O
(	O
75.15mm2	O
)	O
.	O
</s>
<s>
One	O
of	O
the	O
early	O
recipients	O
of	O
this	O
processor	O
was-ill-fated	O
Psion	B-Application
netBook	I-Application
and	O
its	O
more	O
consumer	O
oriented	O
sibling	O
Psion	B-Application
Series	I-Application
7	I-Application
.	O
</s>
<s>
The	O
SA-1110	B-Device
was	O
a	O
derivative	O
of	O
the	O
SA-110	B-Device
developed	O
by	O
Intel	O
.	O
</s>
<s>
It	O
was	O
announced	O
on	O
31	O
March	O
1999	O
,	O
positioned	O
as	O
an	O
alternative	O
to	O
the	O
SA-1100	B-Device
.	O
</s>
<s>
Intel	O
discontinued	O
the	O
SA-1110	B-Device
in	O
early	O
2003	O
.	O
</s>
<s>
The	O
SA-1110	B-Device
was	O
available	O
in	O
133	O
or	O
206MHz	O
versions	O
.	O
</s>
<s>
It	O
differed	O
from	O
the	O
SA-1100	B-Device
by	O
featuring	O
support	O
for	O
66MHz	O
(	O
133MHz	O
version	O
only	O
)	O
or	O
103MHz	O
(	O
206MHz	O
version	O
only	O
)	O
SDRAM	O
.	O
</s>
<s>
The	O
SA-1110	B-Device
was	O
packaged	O
in	O
a	O
256-pin	O
micro	B-Algorithm
ball	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
.	O
</s>
<s>
It	O
was	O
used	O
in	O
mobile	O
phones	O
,	O
personal	B-Application
data	I-Application
assistants	I-Application
(	O
PDAs	B-Application
)	O
such	O
as	O
the	O
Compaq	O
(	O
later	O
HP	O
)	O
iPAQ	B-Application
and	O
HP	B-Operating_System
Jornada	I-Operating_System
,	O
the	O
Sharp	O
SL-5x00	O
Linux	O
Based	O
Platforms	O
and	O
the	O
Simputer	B-Application
.	O
</s>
<s>
The	O
SA-1500	B-Device
was	O
a	O
derivative	O
of	O
the	O
SA-110	B-Device
developed	O
by	O
DEC	O
initially	O
targeted	O
for	O
set-top	O
boxes	O
.	O
</s>
<s>
The	O
SA-1500	B-Device
was	O
available	O
at	O
200	O
to	O
300MHz	O
.	O
</s>
<s>
The	O
SA-1500	B-Device
featured	O
an	O
enhanced	O
SA-110	B-Device
core	O
,	O
an	O
on-chip	O
coprocessor	B-General_Concept
called	O
the	O
Attached	O
Media	O
Processor	O
(	O
AMP	O
)	O
,	O
and	O
an	O
on-chip	O
SDRAM	O
and	O
I/O	O
bus	O
controller	O
.	O
</s>
<s>
The	O
AMP	O
implemented	O
a	O
long	O
instruction	O
word	O
instruction	B-General_Concept
set	I-General_Concept
containing	O
instructions	O
designed	O
for	O
multimedia	O
,	O
such	O
as	O
integer	O
and	O
floating-point	O
multiply	B-Algorithm
–	I-Algorithm
accumulate	I-Algorithm
and	O
SIMD	B-Device
arithmetic	O
.	O
</s>
<s>
Instructions	O
operate	O
on	O
operands	O
from	O
a	O
64-entry	O
36-bit	O
register	B-General_Concept
file	I-General_Concept
,	O
and	O
on	O
a	O
set	O
of	O
control	O
registers	O
.	O
</s>
<s>
The	O
AMP	O
communicates	O
with	O
the	O
SA-110	B-Device
core	O
via	O
an	O
on-chip	O
bus	O
and	O
it	O
shares	O
the	O
data	B-General_Concept
cache	I-General_Concept
with	O
the	O
SA-110	B-Device
.	O
</s>
<s>
The	O
AMP	O
contained	O
an	O
ALU	O
with	O
a	O
shifter	O
,	O
a	O
branch	O
unit	O
,	O
a	O
load/store	O
unit	O
,	O
a	O
multiply	B-Algorithm
–	I-Algorithm
accumulate	I-Algorithm
unit	O
,	O
and	O
a	O
single-precision	O
floating-point	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
SA-1501	O
companion	O
chip	O
provided	O
additional	O
video	O
and	O
audio	O
processing	O
capabilities	O
and	O
various	O
I/O	O
functions	O
such	O
as	O
PS/2	B-Protocol
ports	I-Protocol
,	O
a	O
parallel	O
port	O
,	O
and	O
interfaces	O
for	O
various	O
peripherals	O
.	O
</s>
<s>
The	O
SA-1500	B-Device
contains	O
3.3	O
million	O
transistors	O
and	O
measures	O
60mm2	O
.	O
</s>
<s>
It	O
was	O
packaged	O
in	O
a	O
240-pin	O
metal	O
quad	B-Algorithm
flat	I-Algorithm
package	I-Algorithm
or	O
a	O
256-ball	O
plastic	B-Algorithm
ball	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
.	O
</s>
<s>
The	O
StrongARM	B-Device
latch	B-General_Concept
is	O
an	O
electronic	B-General_Concept
latch	I-General_Concept
circuit	O
topology	O
first	O
proposed	O
by	O
Toshiba	O
engineers	O
Tsuguo	O
Kobayashi	O
et	O
al	O
.	O
</s>
<s>
and	O
got	O
significant	O
attention	O
after	O
being	O
used	O
in	O
StrongARM	B-Device
microprocessors	B-Architecture
.	O
</s>
<s>
It	O
is	O
widely	O
used	O
as	O
a	O
sense	O
amplifier	O
,	O
a	O
comparator	O
,	O
or	O
just	O
a	O
robust	O
latch	B-General_Concept
with	O
high	O
sensitivity	O
.	O
</s>
